[RISCV] Implement vloxseg/vluxseg intrinsics.

[HsiangKai]

Summary

Define vloxseg/vluxseg intrinsics and pseudo instructions. Lower vloxseg/vluxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

[HsiangKai]

Add test cases for rv32. It does not contain all combinations of vlxseg due to the revision will be too large to upload.

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

510

index->indexed

517

index->indexed

970

Make this a FIXME or TODO

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

2775

Make this a FIXME or TODO

[craig.topper]

Does this need earlyclobber? The spec says "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else an illegal instruction exception is raised."

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/vlxseg-rv32.ll

13

This violates "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else an illegal instruction exception is raised." right?

[HsiangKai]

• Address @craig.topper's comments.
• Update to v1.0
• Put test cases into D95193, D95192, D95191, D95190

[craig.topper]

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td

class RISCVSSegLoadMask<int nf>
                                 !add(nf, -1))),
                     !listconcat(!listsplat(LLVMMatchType<0>, nf),
                                 [LLVMPointerToElt<0>,
                                  llvm_anyint_ty,
                                  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                  LLVMMatchType<1>]),
                     [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic;
 
+  // For index segment load
+  // Input: (pointer, index, vl)
+  class RISCVISegLoad<int nf>
+        : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+                                !add(nf, -1))),
+                    [LLVMPointerToElt<0>, llvm_anyvector_ty, llvm_anyint_ty],
+                    [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
+  // For index segment load with mask
+  // Input: (maskedoff, pointer, index, mask, vl)
+  class RISCVISegLoadMask<int nf>
+        : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+                                !add(nf, -1))),
+                    !listconcat(!listsplat(LLVMMatchType<0>, nf),
+                                [LLVMPointerToElt<0>,
+                                 llvm_anyvector_ty,
+                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                 llvm_anyint_ty]),
+                    [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic;
+
   // For unit stride segment store
   // Input: (value, pointer, vl)
   class RISCVUSSegStore<int nf>
         : Intrinsic<[],
                     !listconcat([llvm_anyvector_ty],
                                 !listsplat(LLVMMatchType<0>, !add(nf, -1)),
                                 [LLVMPointerToElt<0>, llvm_anyint_ty]),
                     [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
let TargetPrefix = "riscv" in {
   multiclass RISCVUSSegLoad<int nf> {
     def "int_riscv_" # NAME : RISCVUSSegLoad<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVUSSegLoadMask<nf>;
   }
   multiclass RISCVSSegLoad<int nf> {
     def "int_riscv_" # NAME : RISCVSSegLoad<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVSSegLoadMask<nf>;
   }
+  multiclass RISCVISegLoad<int nf> {
+    def "int_riscv_" # NAME : RISCVISegLoad<nf>;
+    def "int_riscv_" # NAME # "_mask" : RISCVISegLoadMask<nf>;
+  }
   multiclass RISCVUSSegStore<int nf> {
     def "int_riscv_" # NAME : RISCVUSSegStore<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVUSSegStoreMask<nf>;
   }
   multiclass RISCVSSegStore<int nf> {
     def "int_riscv_" # NAME : RISCVSSegStore<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVSSegStoreMask<nf>;
   }
def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
                                      [LLVMMatchType<0>,
                                       LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                       llvm_anyint_ty],
                                      [IntrNoMem]>, RISCVVIntrinsic;
 
   foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
     defm vlseg # nf : RISCVUSSegLoad<nf>;
     defm vlsseg # nf : RISCVSSegLoad<nf>;
+    // In v1.0, it should be vloxseg.
+    defm vlxseg # nf : RISCVISegLoad<nf>;
     defm vsseg # nf : RISCVUSSegStore<nf>;
     defm vssseg # nf : RISCVSSegStore<nf>;
   }
 
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

public:
   bool MatchSLLIUW(SDNode *N) const;
 
   bool selectVSplat(SDValue N, SDValue &SplatVal);
   bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
   bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
 
   void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
   void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
+  void selectVLXSEG(SDNode *Node, unsigned IntNo);
+  void selectVLXSEGMask(SDNode *Node, unsigned IntNo);
   void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
   void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
 
 // Include the pieces autogenerated from the target description.
 #include "RISCVGenDAGISel.inc"
 
 private:
   void doPeepholeLoadStoreADDI();
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (IsStrided) {
     Operands.push_back(Node->getOperand(3));     // Stride.
     Operands.push_back(Node->getOperand(4));     // VL.
   } else {
     Operands.push_back(Node->getOperand(3));     // VL.
   }
   Operands.push_back(SEW);
   Operands.push_back(Node->getOperand(0));       // Chain.
   const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
-      IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+      IntNo, ScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(RISCVVLMUL::LMUL_1));
   SDNode *Load =
       CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
   SDValue SuperReg = SDValue(Load, 0);
   for (unsigned I = 0; I < NF; ++I)
     ReplaceUses(SDValue(Node, I),
                 CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
                                                VT, SuperReg));
 
if (IsStrided) {
     Operands.push_back(Node->getOperand(NF + 5)); // VL.
   } else {
     Operands.push_back(Node->getOperand(NF + 3)); // Mask.
     Operands.push_back(Node->getOperand(NF + 4)); // VL.
   }
   Operands.push_back(SEW);
   Operands.push_back(Node->getOperand(0));        /// Chain.
   const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
-      IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+      IntNo, ScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(RISCVVLMUL::LMUL_1));
+  SDNode *Load =
+      CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
+  SDValue SuperReg = SDValue(Load, 0);
+  for (unsigned I = 0; I < NF; ++I)
+    ReplaceUses(SDValue(Node, I),
+                CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
+                                               VT, SuperReg));
+
+  ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
+  CurDAG->RemoveDeadNode(Node);
+}
+
+void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
+  SDLoc DL(Node);
+  unsigned NF = Node->getNumValues() - 1;
+  EVT VT = Node->getValueType(0);
+  unsigned ScalarSize = VT.getScalarSizeInBits();
+  MVT XLenVT = Subtarget->getXLenVT();
+  RISCVVLMUL LMUL = getLMUL(VT);
+  SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+  SDValue Operands[] = {
+      Node->getOperand(2),     // Base pointer.
+      Node->getOperand(3),     // Index.
+      Node->getOperand(4),     // VL.
+      SEW, Node->getOperand(0) // Chain.
+  };
+
+  EVT IndexVT = Node->getOperand(3)->getValueType(0);
+  RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
+  unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
+  const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+      IntNo, IndexScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(IndexLMUL));
+  SDNode *Load =
+      CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
+  SDValue SuperReg = SDValue(Load, 0);
+  for (unsigned I = 0; I < NF; ++I)
+    ReplaceUses(SDValue(Node, I),
+                CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
+                                               VT, SuperReg));
+
+  ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
+  CurDAG->RemoveDeadNode(Node);
+}
+
+void RISCVDAGToDAGISel::selectVLXSEGMask(SDNode *Node, unsigned IntNo) {
+  SDLoc DL(Node);
+  unsigned NF = Node->getNumValues() - 1;
+  EVT VT = Node->getValueType(0);
+  unsigned ScalarSize = VT.getScalarSizeInBits();
+  MVT XLenVT = Subtarget->getXLenVT();
+  RISCVVLMUL LMUL = getLMUL(VT);
+  SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+  SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
+  SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
+  SDValue Operands[] = {
+      MaskedOff,
+      Node->getOperand(NF + 2), // Base pointer.
+      Node->getOperand(NF + 3), // Index.
+      Node->getOperand(NF + 4), // Mask.
+      Node->getOperand(NF + 5), // VL.
+      SEW,
+      Node->getOperand(0) // Chain.
+  };
+
+  EVT IndexVT = Node->getOperand(NF + 3)->getValueType(0);
+  RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
+  unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
+  const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+      IntNo, IndexScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(IndexLMUL));
   SDNode *Load =
       CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
   SDValue SuperReg = SDValue(Load, 0);
   for (unsigned I = 0; I < NF; ++I)
     ReplaceUses(SDValue(Node, I),
                 CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
                                                VT, SuperReg));
 
if (IsStrided) {
     Operands.push_back(Node->getOperand(3 + NF)); // Stride.
     Operands.push_back(Node->getOperand(4 + NF)); // VL.
   } else {
     Operands.push_back(Node->getOperand(3 + NF)); // VL.
   }
   Operands.push_back(SEW);
   Operands.push_back(Node->getOperand(0));  // Chain.
   const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
-      IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+      IntNo, ScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(RISCVVLMUL::LMUL_1));
   SDNode *Store =
       CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
   ReplaceNode(Node, Store);
 }
 
 void RISCVDAGToDAGISel::selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided) {
   SDLoc DL(Node);
   unsigned NF = Node->getNumOperands() - 5;
if (IsStrided) {
     Operands.push_back(Node->getOperand(5 + NF)); // VL.
   } else {
     Operands.push_back(Node->getOperand(3 + NF)); // Mask.
     Operands.push_back(Node->getOperand(4 + NF)); // VL.
   }
   Operands.push_back(SEW);
   Operands.push_back(Node->getOperand(0));  // Chain.
   const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
-      IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+      IntNo, ScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(RISCVVLMUL::LMUL_1));
   SDNode *Store =
       CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
   ReplaceNode(Node, Store);
 }
 
 void RISCVDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
case ISD::INTRINSIC_W_CHAIN: {
     case Intrinsic::riscv_vlsseg4_mask:
     case Intrinsic::riscv_vlsseg5_mask:
     case Intrinsic::riscv_vlsseg6_mask:
     case Intrinsic::riscv_vlsseg7_mask:
     case Intrinsic::riscv_vlsseg8_mask: {
       selectVLSEGMask(Node, IntNo, /*IsStrided=*/true);
       return;
     }
+    case Intrinsic::riscv_vlxseg2:
+    case Intrinsic::riscv_vlxseg3:
+    case Intrinsic::riscv_vlxseg4:
+    case Intrinsic::riscv_vlxseg5:
+    case Intrinsic::riscv_vlxseg6:
+    case Intrinsic::riscv_vlxseg7:
+    case Intrinsic::riscv_vlxseg8: {
+      selectVLXSEG(Node, IntNo);
+      return;
+    }
+    case Intrinsic::riscv_vlxseg2_mask:
+    case Intrinsic::riscv_vlxseg3_mask:
+    case Intrinsic::riscv_vlxseg4_mask:
+    case Intrinsic::riscv_vlxseg5_mask:
+    case Intrinsic::riscv_vlxseg6_mask:
+    case Intrinsic::riscv_vlxseg7_mask:
+    case Intrinsic::riscv_vlxseg8_mask: {
+      selectVLXSEGMask(Node, IntNo);
+      return;
+    }
     }
     break;
   }
   case ISD::INTRINSIC_VOID: {
     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
     case Intrinsic::riscv_vsseg2:
     case Intrinsic::riscv_vsseg3:

llvm/lib/Target/RISCV/RISCVISelLowering.h

 } // end namespace RISCVVIntrinsicsTable
 
 namespace RISCVZvlssegTable {
 
 struct RISCVZvlsseg {
   unsigned int IntrinsicID;
   unsigned int SEW;
   unsigned int LMUL;
+  unsigned int IndexLMUL;
   unsigned int Pseudo;
 };
 
 using namespace RISCV;
 
 #define GET_RISCVZvlssegTable_DECL
 #include "RISCVGenSearchableTables.inc"
 
 } // namespace RISCVZvlssegTable
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 def RISCVVIntrinsicsTable : GenericTable {
   let FilterClass = "RISCVVIntrinsic";
   let CppTypeName = "RISCVVIntrinsicInfo";
   let Fields = ["IntrinsicID", "ExtendOperand"];
   let PrimaryKey = ["IntrinsicID"];
   let PrimaryKeyName = "getRISCVVIntrinsicInfo";
 }
 
-class RISCVZvlsseg<string IntrName, bits<11> S, bits<3> L> {
+class RISCVZvlsseg<string IntrName, bits<11> S, bits<3> L, bits<3> IL = V_M1.value> {
   Intrinsic IntrinsicID = !cast<Intrinsic>(IntrName);
   bits<11> SEW = S;
   bits<3> LMUL = L;
+  bits<3> IndexLMUL = IL;
   Pseudo Pseudo = !cast<Pseudo>(NAME);
 }
 
 def RISCVZvlssegTable : GenericTable {
   let FilterClass = "RISCVZvlsseg";
-  let Fields = ["IntrinsicID", "SEW", "LMUL", "Pseudo"];
-  let PrimaryKey = ["IntrinsicID", "SEW", "LMUL"];
+  let Fields = ["IntrinsicID", "SEW", "LMUL", "IndexLMUL", "Pseudo"];
+  let PrimaryKey = ["IntrinsicID", "SEW", "LMUL", "IndexLMUL"];
   let PrimaryKeyName = "getPseudo";
 }
 
 //===----------------------------------------------------------------------===//
 // Helpers to define the different pseudo instructions.
 //===----------------------------------------------------------------------===//
 
 class PseudoToVInst<string PseudoInst> {
string VInst = !subst("_M8", "",
                  !subst("_MASK", "",
                  !subst("Pseudo", "", PseudoInst))))))))))))))));
 }
 
 class ToLowerCase<string Upper> {
   string L = !subst("VLSEG", "vlseg",
              !subst("VLSSEG", "vlsseg",
              !subst("VSSEG", "vsseg",
-             !subst("VSSSEG", "vssseg", Upper))));
+             !subst("VSSSEG", "vssseg",
+             !subst("VLXSEG", "vlxseg", Upper)))));
 }
 
 // Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2
 // Example: PseudoVLSEG2E32_V_M2_MASK -> int_riscv_vlseg2_mask
 class PseudoToIntrinsic<string PseudoInst, bit IsMasked> {
   string Intrinsic = !strconcat("int_riscv_",
                         ToLowerCase<
                         !subst("E8", "",
                         !subst("E16", "",
                         !subst("E32", "",
                         !subst("E64", "",
-                        !subst("_V", "", PseudoToVInst<PseudoInst>.VInst)))))>.L,
+                        !subst("EI8", "",
+                        !subst("EI16", "",
+                        !subst("EI32", "",
+                        !subst("EI64", "",
+                        !subst("_V", "", PseudoToVInst<PseudoInst>.VInst)))))))))>.L,
                         !if(IsMasked, "_mask", ""));
 }
 
 // The destination vector register group for a masked vector instruction cannot
 // overlap the source mask register (v0), unless the destination vector register
 // is being written with a mask value (e.g., comparisons) or the scalar result
 // of a reduction.
 class GetVRegNoV0<VReg VRegClass> {
class VPseudoSSegLoadMask<VReg RetClass, bits<11> EEW>:
   let Constraints = "$rd = $merge";
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoISegLoadNoMask<VReg RetClass, VReg IdxClass, bits<11> EEW, bits<3> LMUL>:
+      Pseudo<(outs RetClass:$rd),
+             (ins GPR:$rs1, IdxClass:$offset, GPR:$vl, ixlenimm:$sew),[]>,
+      RISCVVPseudo,
+      RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul, LMUL> {
+  let mayLoad = 1;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoISegLoadMask<VReg RetClass, VReg IdxClass, bits<11> EEW, bits<3> LMUL>:
+      Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+             (ins GetVRegNoV0<RetClass>.R:$merge, GPR:$rs1,
+                  IdxClass:$offset, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+      RISCVVPseudo,
+      RISCVZvlsseg<PseudoToIntrinsic<NAME, true>.Intrinsic, EEW, VLMul, LMUL> {
+  let mayLoad = 1;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Constraints = "$rd = $merge";
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let HasMergeOp = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
 class VPseudoUSSegStoreNoMask<VReg ValClass, bits<11> EEW>:
       Pseudo<(outs),
              (ins ValClass:$rd, GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
   let hasSideEffects = 0;
foreach lmul = MxSet<eew>.m in {
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew>;
         }
       }
     }
   }
 }
 
+multiclass VPseudoISegLoad {
+  foreach idx_eew = EEWList in {  // EEW for index argument.
+    foreach idx_lmul = MxSet<idx_eew>.m in {  // LMUL for index argument.
+      foreach val_lmul = MxList.m in {  // LMUL for the value.
+        defvar IdxLInfo = idx_lmul.MX;
+        defvar IdxVreg = idx_lmul.vrclass;
+        defvar ValLInfo = val_lmul.MX;
+        let VLMul = val_lmul.value in {
+          foreach nf = NFSet<val_lmul>.L in {
+            defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+            def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
+              VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value>;
+            def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
+              VPseudoISegLoadMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value>;
+          }
+        }
+      }
+    }
+  }
+}
+
 multiclass VPseudoUSSegStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       let VLMul = lmul.value in {
         foreach nf = NFSet<lmul>.L in {
           defvar vreg = SegRegClass<lmul, nf>.RC;
           def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew>;
foreach eew = EEWList in {
   defm PseudoVLE # eew # FF : VPseudoUSLoad;
 }
 
 //===----------------------------------------------------------------------===//
 // 7.8. Vector Load/Store Segment Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVLSEG : VPseudoUSSegLoad;
 defm PseudoVLSSEG : VPseudoSSegLoad;
+// In v1.0, it should be PseudoVLOXSEG.
+defm PseudoVLXSEG : VPseudoISegLoad;
 defm PseudoVSSEG : VPseudoUSSegStore;
 defm PseudoVSSSEG : VPseudoSSegStore;
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/vlxseg-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i32)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i32 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}

llvm/test/CodeGen/RISCV/rvv/vlxseg-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlxseg2_nxv16i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
+  ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlxseg2_mask_nxv16i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.nxv16i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+  %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+  ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg2_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg2_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg3_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg3_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i32> @test_vlxseg4_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
+  ret <vscale x 4 x i32> %1
+}
+
+define <vscale x 4 x i32> @test_vlxseg4_mask_nxv4i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.nxv4i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
+  %2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
+  ret <vscale x 4 x i32> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg2_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg2_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg3_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg3_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i8> @test_vlxseg4_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
+  ret <vscale x 16 x i8> %1
+}
+
+define <vscale x 16 x i8> @test_vlxseg4_mask_nxv16i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.nxv16i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
+  %2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
+  ret <vscale x 16 x i8> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg2_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg2_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg3_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg3_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg4_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg4_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg5_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg5_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg6_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg6_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg7_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg7_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i64> @test_vlxseg8_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
+  ret <vscale x 1 x i64> %1
+}
+
+define <vscale x 1 x i64> @test_vlxseg8_mask_nxv1i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.nxv1i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
+  %2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
+  ret <vscale x 1 x i64> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg2_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg2_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg3_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg3_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg4_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg4_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg5_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg5_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg6_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg6_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg7_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg7_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i32> @test_vlxseg8_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
+  ret <vscale x 1 x i32> %1
+}
+
+define <vscale x 1 x i32> @test_vlxseg8_mask_nxv1i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.nxv1i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
+  %2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
+  ret <vscale x 1 x i32> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg2_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg2_mask_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg3_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg3_mask_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i16> @test_vlxseg4_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
+  ret <vscale x 8 x i16> %1
+}
+
+define <vscale x 8 x i16> @test_vlxseg4_mask_nxv8i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.nxv8i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
+  %2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
+  ret <vscale x 8 x i16> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg2_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg2_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg3_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg3_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg4_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg4_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg5_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg5_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg6_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg6_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg7_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg7_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i8> @test_vlxseg8_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
+  ret <vscale x 4 x i8> %1
+}
+
+define <vscale x 4 x i8> @test_vlxseg8_mask_nxv4i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.nxv4i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
+  %2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
+  ret <vscale x 4 x i8> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg2_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg2_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg3_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg3_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg4_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg4_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg5_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg5_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg6_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg6_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg7_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg7_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i16> @test_vlxseg8_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
+  ret <vscale x 1 x i16> %1
+}
+
+define <vscale x 1 x i16> @test_vlxseg8_mask_nxv1i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.nxv1i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
+  %2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
+  ret <vscale x 1 x i16> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg2_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg2_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg3_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg3_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg4_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg4_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg5_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg5_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg6_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg6_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg7_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg7_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i32> @test_vlxseg8_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
+  ret <vscale x 2 x i32> %1
+}
+
+define <vscale x 2 x i32> @test_vlxseg8_mask_nxv2i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.nxv2i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
+  %2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
+  ret <vscale x 2 x i32> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg2_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg2_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg3_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg3_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg4_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg4_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg5_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg5_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg6_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg6_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg7_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg7_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i8> @test_vlxseg8_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
+  ret <vscale x 8 x i8> %1
+}
+
+define <vscale x 8 x i8> @test_vlxseg8_mask_nxv8i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.nxv8i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
+  %2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
+  ret <vscale x 8 x i8> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i64> @test_vlxseg2_nxv4i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
+  ret <vscale x 4 x i64> %1
+}
+
+define <vscale x 4 x i64> @test_vlxseg2_mask_nxv4i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.nxv4i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
+  %2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
+  ret <vscale x 4 x i64> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg2_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg2_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg3_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg3_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg4_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg4_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg5_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg5_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg6_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg6_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg7_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg7_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x i16> @test_vlxseg8_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
+  ret <vscale x 4 x i16> %1
+}
+
+define <vscale x 4 x i16> @test_vlxseg8_mask_nxv4i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.nxv4i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
+  %2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
+  ret <vscale x 4 x i16> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg2_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg2_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg3_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg3_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg4_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg4_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg5_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg5_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg6_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg6_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg7_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg7_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x i8> @test_vlxseg8_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
+  ret <vscale x 1 x i8> %1
+}
+
+define <vscale x 1 x i8> @test_vlxseg8_mask_nxv1i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.nxv1i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
+  %2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
+  ret <vscale x 1 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg2_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg2_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg3_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg3_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg4_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg4_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg5_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg5_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg6_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg6_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg7_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg7_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i8> @test_vlxseg8_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
+  ret <vscale x 2 x i8> %1
+}
+
+define <vscale x 2 x i8> @test_vlxseg8_mask_nxv2i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.nxv2i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
+  %2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
+  ret <vscale x 2 x i8> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i16(i32*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i16(i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i16(i32*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i16(i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i32(i32*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i32(i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i8(i32*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i8(i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i64(i32*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i64(i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i32(i32*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i32(i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i16(i32*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i16(i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i8(i32*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i8(i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i16(i32*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i16(i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i32(i32*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i32(i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i8(i32*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i8(i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i64(i32*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i64(i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv64i8(i32*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv64i8(i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i16(i32*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv4i16(i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i64(i32*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i64(i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i8(i32*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv1i8(i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i8(i32*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i8(i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i32(i32*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv8i32(i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i8(i32*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv32i8(i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i32(i32*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv16i32(i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i16(i32*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i16(i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i64(i32*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x i32> @test_vlxseg2_nxv8i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
+  ret <vscale x 8 x i32> %1
+}
+
+define <vscale x 8 x i32> @test_vlxseg2_mask_nxv8i32_nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.nxv8i32.nxv2i64(i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
+  %2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
+  ret <vscale x 8 x i32> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i16(i8*, <vscale x 16 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i16(i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i16(i8*, <vscale x 32 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i16(i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i32(i8*, <vscale x 4 x i32>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i32(i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i8(i8*, <vscale x 16 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i8(i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i64(i8*, <vscale x 1 x i64>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i64>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i64(i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 1 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i32(i8*, <vscale x 1 x i32>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i32(i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i16(i8*, <vscale x 8 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i16(i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i8(i8*, <vscale x 4 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i8(i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i16(i8*, <vscale x 1 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i16(i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i32(i8*, <vscale x 2 x i32>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i32(i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i8(i8*, <vscale x 8 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i8(i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i64(i8*, <vscale x 4 x i64>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i64>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i64(i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 4 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv64i8(i8*, <vscale x 64 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv64i8(i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i16(i8*, <vscale x 4 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv4i16(i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i64(i8*, <vscale x 8 x i64>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i64>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i64(i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 8 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i8(i8*, <vscale x 1 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv1i8(i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i8(i8*, <vscale x 2 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i8(i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i32(i8*, <vscale x 8 x i32>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv8i32(i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i8(i8*, <vscale x 32 x i8>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv32i8(i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i32(i8*, <vscale x 16 x i32>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv16i32(i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i16(i8*, <vscale x 2 x i16>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i16(i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i64(i8*, <vscale x 2 x i64>, i64)
+declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i64>, <vscale x 32 x i1>, i64)
+
+define <vscale x 32 x i8> @test_vlxseg2_nxv32i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv32i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
+  ret <vscale x 32 x i8> %1
+}
+
+define <vscale x 32 x i8> @test_vlxseg2_mask_nxv32i8_nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 32 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv32i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.nxv32i8.nxv2i64(i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
+  %2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 2 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
+  ret <vscale x 32 x i8> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg2_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg2_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg3_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg3_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg4_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg4_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg5_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg5_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg6_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg6_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg7_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg7_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i16(i16*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i16(i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i32(i16*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i32(i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i8(i16*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i8(i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i64(i16*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i64(i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i32(i16*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i32(i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i16(i16*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i16(i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i8(i16*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i8(i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i16(i16*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i16(i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i32(i16*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i32(i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i8(i16*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i8(i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i64(i16*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i64(i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv64i8(i16*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv64i8(i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i16(i16*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv4i16(i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i64(i16*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i64(i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i8(i16*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv1i8(i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i8(i16*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i8(i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i32(i16*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv8i32(i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i8(i16*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv32i8(i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i32(i16*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv16i32(i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i16(i16*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i16(i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i64(i16*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i16> @test_vlxseg8_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
+  ret <vscale x 2 x i16> %1
+}
+
+define <vscale x 2 x i16> @test_vlxseg8_mask_nxv2i16_nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.nxv2i16.nxv2i64(i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
+  %2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
+  ret <vscale x 2 x i16> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg2_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg2_mask_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg3_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg3_mask_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i16(i64*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i16(i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i16(i64*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i16(i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i32(i64*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i32(i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i8(i64*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i8(i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i64(i64*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i64(i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i32(i64*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i32(i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i16(i64*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i16(i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i8(i64*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i8(i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i16(i64*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i16(i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i32(i64*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i32(i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i8(i64*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i8(i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i64(i64*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i64(i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv64i8(i64*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv64i8(i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i16(i64*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv4i16(i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i64(i64*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i64(i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i8(i64*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv1i8(i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i8(i64*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i8(i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i32(i64*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv8i32(i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i8(i64*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv32i8(i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i32(i64*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv16i32(i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i16(i64*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i16(i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i64(i64*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x i64> @test_vlxseg4_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
+  ret <vscale x 2 x i64> %1
+}
+
+define <vscale x 2 x i64> @test_vlxseg4_mask_nxv2i64_nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.nxv2i64.nxv2i64(i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
+  %2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
+  ret <vscale x 2 x i64> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x half> @test_vlxseg2_nxv16f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv16f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
+  ret <vscale x 16 x half> %1
+}
+
+define <vscale x 16 x half> @test_vlxseg2_mask_nxv16f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv16f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.nxv16f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
+  %2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
+  ret <vscale x 16 x half> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x double> @test_vlxseg2_nxv4f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
+  ret <vscale x 4 x double> %1
+}
+
+define <vscale x 4 x double> @test_vlxseg2_mask_nxv4f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.nxv4f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
+  %2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
+  ret <vscale x 4 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg2_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg2_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg3_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg3_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg4_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg4_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg5_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg5_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg6_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg6_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg7_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg7_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x double> @test_vlxseg8_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
+  ret <vscale x 1 x double> %1
+}
+
+define <vscale x 1 x double> @test_vlxseg8_mask_nxv1f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.nxv1f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
+  %2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
+  ret <vscale x 1 x double> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg2_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg2_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg3_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg3_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg4_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg4_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg5_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg5_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg6_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg6_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg7_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg7_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x float> @test_vlxseg8_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
+  ret <vscale x 2 x float> %1
+}
+
+define <vscale x 2 x float> @test_vlxseg8_mask_nxv2f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.nxv2f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
+  %2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
+  ret <vscale x 2 x float> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg2_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg2_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg3_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg3_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg4_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg4_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg5_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg5_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg6_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg6_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg7_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg7_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x half> @test_vlxseg8_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
+  ret <vscale x 1 x half> %1
+}
+
+define <vscale x 1 x half> @test_vlxseg8_mask_nxv1f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.nxv1f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
+  %2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
+  ret <vscale x 1 x half> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg2_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg2_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg3_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg3_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg4_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg4_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg5_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg5_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg6_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg6_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg7_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg7_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define <vscale x 1 x float> @test_vlxseg8_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
+  ret <vscale x 1 x float> %1
+}
+
+define <vscale x 1 x float> @test_vlxseg8_mask_nxv1f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.nxv1f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
+  %2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
+  ret <vscale x 1 x float> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg2_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg2_mask_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg3_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg3_mask_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x half> @test_vlxseg4_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
+  ret <vscale x 8 x half> %1
+}
+
+define <vscale x 8 x half> @test_vlxseg4_mask_nxv8f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.nxv8f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
+  %2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
+  ret <vscale x 8 x half> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define <vscale x 8 x float> @test_vlxseg2_nxv8f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv8f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v12, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
+  ret <vscale x 8 x float> %1
+}
+
+define <vscale x 8 x float> @test_vlxseg2_mask_nxv8f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv8f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16
+; CHECK-NEXT:    vmv4r.v v8, v4
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v4, (a0), v16, v0.t
+; CHECK-NEXT:    vmv4r.v v16, v8
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.nxv8f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
+  %2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
+  ret <vscale x 8 x float> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg2_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg2_mask_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg3_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg3_mask_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i16(double*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i16(double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i16(double*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i16(double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i32(double*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i32(double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i8(double*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i8(double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i64(double*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i64(double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i32(double*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i32(double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i16(double*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i16(double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i8(double*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i8(double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i16(double*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i16(double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i32(double*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i32(double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i8(double*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i8(double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i64(double*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i64(double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv64i8(double*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv64i8(double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i16(double*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv4i16(double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i64(double*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i64(double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i8(double*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv1i8(double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i8(double*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i8(double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i32(double*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv8i32(double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i8(double*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv32i8(double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i32(double*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv16i32(double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i16(double*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i16(double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i64(double*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x double> @test_vlxseg4_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
+  ret <vscale x 2 x double> %1
+}
+
+define <vscale x 2 x double> @test_vlxseg4_mask_nxv2f64_nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.nxv2f64.nxv2i64(double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
+  %2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
+  ret <vscale x 2 x double> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg2_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg2_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg3_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg3_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg4_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg4_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg5_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg5_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg6_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg6_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg7_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg7_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x half> @test_vlxseg8_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
+  ret <vscale x 4 x half> %1
+}
+
+define <vscale x 4 x half> @test_vlxseg8_mask_nxv4f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.nxv4f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
+  %2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
+  ret <vscale x 4 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg2_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg2_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg3_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg3_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg4_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg4_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg5_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg5_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg5_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg5_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg5ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg6_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg6_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg6_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg6_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg6ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg7_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg7_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg7_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg7_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg7ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i16(half*, <vscale x 16 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i16(half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i16(half*, <vscale x 32 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i16(half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i32(half*, <vscale x 4 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i32(half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i8(half*, <vscale x 16 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i8(half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i64(half*, <vscale x 1 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i64(half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i32(half*, <vscale x 1 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i32(half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i16(half*, <vscale x 8 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i16(half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i8(half*, <vscale x 4 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i8(half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i16(half*, <vscale x 1 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i16(half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i32(half*, <vscale x 2 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i32(half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i8(half*, <vscale x 8 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i8(half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i64(half*, <vscale x 4 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i64(half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv64i8(half*, <vscale x 64 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv64i8(half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i16(half*, <vscale x 4 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv4i16(half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i64(half*, <vscale x 8 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i64(half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i8(half*, <vscale x 1 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv1i8(half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i8(half*, <vscale x 2 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i8(half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i32(half*, <vscale x 8 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv8i32(half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i8(half*, <vscale x 32 x i8>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei8.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv32i8(half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i32(half*, <vscale x 16 x i32>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei32.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv16i32(half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i16(half*, <vscale x 2 x i16>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei16.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i16(half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i64(half*, <vscale x 2 x i64>, i64)
+declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define <vscale x 2 x half> @test_vlxseg8_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg8_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
+  ret <vscale x 2 x half> %1
+}
+
+define <vscale x 2 x half> @test_vlxseg8_mask_nxv2f16_nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg8_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,tu,mu
+; CHECK-NEXT:    vlxseg8ei64.v v1, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v16, v2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.nxv2f16.nxv2i64(half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
+  %2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
+  ret <vscale x 2 x half> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg2_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg2_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg2_mask_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg2_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg2ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg3_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg3_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg3_mask_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg3_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg3ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i16(float*, <vscale x 16 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i16(float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i16(float*, <vscale x 32 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i16(float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i32(float*, <vscale x 4 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i32(float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i8(float*, <vscale x 16 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i8(float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i64(float*, <vscale x 1 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i64(float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i32(float*, <vscale x 1 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i32(float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i16(float*, <vscale x 8 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i16(float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i8(float*, <vscale x 4 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i8(float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i16(float*, <vscale x 1 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i16(float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i32(float*, <vscale x 2 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i32(float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i8(float*, <vscale x 8 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i8(float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i64(float*, <vscale x 4 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i64(float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv64i8(float*, <vscale x 64 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv64i8(float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i16(float*, <vscale x 4 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv4i16(float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i64(float*, <vscale x 8 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i64(float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i8(float*, <vscale x 1 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv1i8(float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i8(float*, <vscale x 2 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i8(float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i32(float*, <vscale x 8 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv8i32(float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i8(float*, <vscale x 32 x i8>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei8.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv32i8(float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i32(float*, <vscale x 16 x i32>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei32.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv16i32(float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i16(float*, <vscale x 2 x i16>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei16.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i16(float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i64(float*, <vscale x 2 x i64>, i64)
+declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define <vscale x 4 x float> @test_vlxseg4_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vlxseg4_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v14, (a0), v16
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
+  ret <vscale x 4 x float> %1
+}
+
+define <vscale x 4 x float> @test_vlxseg4_mask_nxv4f32_nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: test_vlxseg4_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,tu,mu
+; CHECK-NEXT:    vlxseg4ei64.v v2, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v16, v4
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.nxv4f32.nxv2i64(float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  %1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
+  %2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  %3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
+  ret <vscale x 4 x float> %3
+}
+