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Differential D93608

[RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction
ClosedPublic

Authored by arcbbb on Dec 20 2020, 7:40 PM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
evandro
Commits
rGc8874464b5f6: [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction
Summary

Define vslide1up, vslide1down, vfslide1up, and vfslide1down intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Diff Detail

Event Timeline

arcbbb created this revision.Dec 20 2020, 7:40 PM
Herald added subscribers: NickHung, luismarques, apazos and 24 others. · View Herald TranscriptDec 20 2020, 7:40 PM
arcbbb requested review of this revision.Dec 20 2020, 7:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 20 2020, 7:40 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B83094: Diff 313012.Dec 20 2020, 8:34 PM
arcbbb updated this revision to Diff 313101.Dec 21 2020, 6:43 AM

Fixed test failures.

Harbormaster completed remote builds in B83147: Diff 313101.Dec 21 2020, 6:43 AM
craig.topper added inline comments.Dec 21 2020, 9:57 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
1958

Doesn't slide1up need an earlyclobber?

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
13

It would be nice if we used the update_llc_test_checks.py script to generate these tests so we could see whether the source and destination register were the same or not.

craig.topper added inline comments.Dec 21 2020, 10:17 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
1952

Previous predicates closed here. Should these VSLIDE* instructions have a Predicate?

arcbbb updated this revision to Diff 313232.Dec 21 2020, 7:28 PM

Updates:

  1. Fixed missing earlyclobber for VSLIDE1UP pseudos
  2. Added missing Predicate for VSLIDE pseudos
  3. updated tests with update_llc_test_checks.py
Harbormaster completed remote builds in B83216: Diff 313232.Dec 21 2020, 8:07 PM
craig.topper added inline comments.Dec 21 2020, 8:38 PM
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
15

Is the earlyclobber constraint not working here?

arcbbb marked 3 inline comments as done.Dec 21 2020, 10:20 PM
arcbbb added inline comments.
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
15

my local build is not clean. let my rebuild & update this again.

arcbbb updated this revision to Diff 313245.Dec 21 2020, 10:28 PM

Updates the tests and earlyclobber takes effect.

arcbbb updated this revision to Diff 313248.Dec 21 2020, 10:49 PM

updated again

arcbbb marked an inline comment as done.Dec 21 2020, 10:50 PM
Harbormaster completed remote builds in B83221: Diff 313248.Dec 21 2020, 10:50 PM
Harbormaster completed remote builds in B83220: Diff 313245.Dec 21 2020, 11:16 PM
arcbbb updated this revision to Diff 313314.Dec 22 2020, 5:52 AM

rebased

Harbormaster completed remote builds in B83254: Diff 313314.Dec 22 2020, 7:39 AM
craig.topper accepted this revision.Dec 22 2020, 9:46 AM

LGTM

This revision is now accepted and ready to land.Dec 22 2020, 9:46 AM
Closed by commit rGc8874464b5f6: [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction (authored by arcbbb). · Explain WhyDec 22 2020, 6:14 PM
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rGc8874464b5f6: [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction.

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
6 lines
lib/
Target/
RISCV/
21 lines
test/
CodeGen/
RISCV/
rvv/
512 lines
698 lines
523 lines
713 lines
800 lines
978 lines
24 lines
1000 lines

Diff 313464

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 529 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vfsgnj : RISCVBinaryAAX; defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX; defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX; defm vfsgnjx : RISCVBinaryAAX;
defm vslideup : RISCVTernaryAAAX; defm vslideup : RISCVTernaryAAAX;
defm vslidedown : RISCVTernaryAAAX; defm vslidedown : RISCVTernaryAAAX;
defm vslide1up : RISCVBinaryAAX;
defm vslide1down : RISCVBinaryAAX;
defm vfslide1up : RISCVBinaryAAX;
defm vfslide1down : RISCVBinaryAAX;
defm vaaddu : RISCVSaturatingBinaryAAX; defm vaaddu : RISCVSaturatingBinaryAAX;
defm vaadd : RISCVSaturatingBinaryAAX; defm vaadd : RISCVSaturatingBinaryAAX;
defm vasubu : RISCVSaturatingBinaryAAX; defm vasubu : RISCVSaturatingBinaryAAX;
defm vasub : RISCVSaturatingBinaryAAX; defm vasub : RISCVSaturatingBinaryAAX;
defm vsmul : RISCVSaturatingBinaryAAX; defm vsmul : RISCVSaturatingBinaryAAX;
defm vssrl : RISCVSaturatingBinaryAAX; defm vssrl : RISCVSaturatingBinaryAAX;
defm vssra : RISCVSaturatingBinaryAAX; defm vssra : RISCVSaturatingBinaryAAX;
defm vnclipu : RISCVSaturatingBinaryABX; defm vnclipu : RISCVSaturatingBinaryABX;
defm vnclip : RISCVSaturatingBinaryABX; defm vnclip : RISCVSaturatingBinaryABX;
defm vmfeq : RISCVCompare; defm vmfeq : RISCVCompare;
defm vmfne : RISCVCompare; defm vmfne : RISCVCompare;
defm vmflt : RISCVCompare; defm vmflt : RISCVCompare;
defm vmfle : RISCVCompare; defm vmfle : RISCVCompare;
defm vmfgt : RISCVCompare; defm vmfgt : RISCVCompare;
defm vmfge : RISCVCompare; defm vmfge : RISCVCompare;
} // TargetPrefix = "riscv" } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 667 Lines • ▼ Show 20 Linesmulticlass VPseudoBinary<VReg RetClass,
} }
} }
multiclass VPseudoBinaryV_VV { multiclass VPseudoBinaryV_VV {
foreach m = MxList.m in foreach m = MxList.m in
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>; defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>;
} }
multiclass VPseudoBinaryV_VX<bit IsFloat> { multiclass VPseudoBinaryV_VX<bit IsFloat, string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass, defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass,
!if(IsFloat, FPR32, GPR), m>; !if(IsFloat, FPR32, GPR), m, Constraint>;
} }
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> { multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
foreach m = MxList.m in foreach m = MxList.m in
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>; defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>;
} }
// We use earlyclobber here due to // We use earlyclobber here due to
▲ Show 20 Lines • Show All 1,256 Lines • ▼ Show 20 Lines let VLMul = m.value in {
Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def PseudoVFMV_S_F # "_" # m.MX : Pseudo<(outs m.vrclass:$rd), def PseudoVFMV_S_F # "_" # m.MX : Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, FPR32:$rs2, (ins m.vrclass:$rs1, FPR32:$rs2,
GPR:$vl, ixlenimm:$sew), GPR:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
} }
} }
} }
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
craig.topperUnsubmitted
Done
ReplyInline Actions

Previous predicates closed here. Should these VSLIDE* instructions have a Predicate?

craig.topper: Previous predicates closed here. Should these VSLIDE* instructions have a Predicate?
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 17.3. Vector Slide Instructions // 17.3. Vector Slide Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in {
defm PseudoVSLIDEUP : VPseudoTernaryV_VX_VI<uimm5, "@earlyclobber $rd">; defm PseudoVSLIDEUP : VPseudoTernaryV_VX_VI<uimm5, "@earlyclobber $rd">;
craig.topperUnsubmitted
Done
ReplyInline Actions

Doesn't slide1up need an earlyclobber?

craig.topper: Doesn't slide1up need an earlyclobber?
defm PseudoVSLIDEDOWN : VPseudoTernaryV_VX_VI<uimm5>; defm PseudoVSLIDEDOWN : VPseudoTernaryV_VX_VI<uimm5>;
defm PseudoVSLIDE1UP : VPseudoBinaryV_VX</*IsFloat*/false, "@earlyclobber $rd">;
defm PseudoVSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/false>;
} // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in {
defm PseudoVFSLIDE1UP : VPseudoBinaryV_VX</*IsFloat*/true, "@earlyclobber $rd">;
defm PseudoVFSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/true>;
} // Predicates = [HasStdExtV, HasStdExtF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
// Whole-register vector patterns. // Whole-register vector patterns.
▲ Show 20 Lines • Show All 351 Lines • ▼ Show 20 Lines
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 17.3. Vector Slide Instructions // 17.3. Vector Slide Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllIntegerVectors, uimm5>; defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllIntegerVectors, uimm5>;
defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllIntegerVectors, uimm5>; defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllIntegerVectors, uimm5>;
defm "" : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>;
defm "" : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>; defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>;
defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>; defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>;
defm "" : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>;
defm "" : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>;
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half>,
half,
i32);
define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i32 %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x half> @intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
<vscale x 2 x half>,
half,
i32);
define <vscale x 2 x half> @intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i32 %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x half> @intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
<vscale x 4 x half>,
half,
i32);
define <vscale x 4 x half> @intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i32 %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x half> @intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
<vscale x 8 x half>,
half,
i32);
define <vscale x 8 x half> @intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i32 %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x half> @intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
<vscale x 16 x half>,
half,
i32);
define <vscale x 16 x half> @intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i32 %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x half> @intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
<vscale x 32 x half>,
half,
i32);
define <vscale x 32 x half> @intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
<vscale x 32 x half> %0,
half %1,
i32 %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
half,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x half> @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
half %2,
<vscale x 32 x i1> %3,
i32 %4)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
<vscale x 1 x float>,
float,
i32);
define <vscale x 1 x float> @intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
<vscale x 2 x float>,
float,
i32);
define <vscale x 2 x float> @intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
<vscale x 4 x float>,
float,
i32);
define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
<vscale x 8 x float>,
float,
i32);
define <vscale x 8 x float> @intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
<vscale x 16 x float>,
float,
i32);
define <vscale x 16 x float> @intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
<vscale x 16 x float> %0,
float %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
float,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
float %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half>,
half,
i64);
define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i64 %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x half> @intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
<vscale x 2 x half>,
half,
i64);
define <vscale x 2 x half> @intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i64 %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x half> @intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
<vscale x 4 x half>,
half,
i64);
define <vscale x 4 x half> @intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i64 %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x half> @intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
<vscale x 8 x half>,
half,
i64);
define <vscale x 8 x half> @intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i64 %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x half> @intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
<vscale x 16 x half>,
half,
i64);
define <vscale x 16 x half> @intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i64 %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x half> @intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
<vscale x 32 x half>,
half,
i64);
define <vscale x 32 x half> @intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
<vscale x 32 x half> %0,
half %1,
i64 %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
half,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x half> @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
half %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
<vscale x 1 x float>,
float,
i64);
define <vscale x 1 x float> @intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
<vscale x 2 x float>,
float,
i64);
define <vscale x 2 x float> @intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
<vscale x 4 x float>,
float,
i64);
define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
<vscale x 8 x float>,
float,
i64);
define <vscale x 8 x float> @intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
<vscale x 16 x float>,
float,
i64);
define <vscale x 16 x float> @intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
<vscale x 16 x float> %0,
float %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
float,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
float %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64(
<vscale x 1 x double>,
double,
i64);
define <vscale x 1 x double> @intrinsic_vfslide1down_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f64_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfslide1down_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f64_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64(
<vscale x 2 x double>,
double,
i64);
define <vscale x 2 x double> @intrinsic_vfslide1down_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f64_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfslide1down_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f64_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64(
<vscale x 4 x double>,
double,
i64);
define <vscale x 4 x double> @intrinsic_vfslide1down_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f64_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfslide1down_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f64_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64(
<vscale x 8 x double>,
double,
i64);
define <vscale x 8 x double> @intrinsic_vfslide1down_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f64_nxv8f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v16, ft0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64(
<vscale x 8 x double> %0,
double %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
double,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: fmv.d.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu
; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
double %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half>,
half,
i32);
define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
craig.topperUnsubmitted
Done
ReplyInline Actions

It would be nice if we used the update_llc_test_checks.py script to generate these tests so we could see whether the source and destination register were the same or not.

craig.topper: It would be nice if we used the update_llc_test_checks.py script to generate these tests so we…
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
craig.topperUnsubmitted
Done
ReplyInline Actions

Is the earlyclobber constraint not working here?

craig.topper: Is the earlyclobber constraint not working here?
arcbbbAuthorUnsubmitted
Done
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my local build is not clean. let my rebuild & update this again.

arcbbb: my local build is not clean. let my rebuild & update this again.
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i32 %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
<vscale x 2 x half>,
half,
i32);
define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i32 %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x half> @intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
<vscale x 4 x half>,
half,
i32);
define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i32 %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x half> @intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
<vscale x 8 x half>,
half,
i32);
define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v26, v16, ft0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i32 %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x half> @intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
<vscale x 16 x half>,
half,
i32);
define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v28, v16, ft0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i32 %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x half> @intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
<vscale x 32 x half>,
half,
i32);
define <vscale x 32 x half> @intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v8, v16, ft0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
<vscale x 32 x half> %0,
half %1,
i32 %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
half,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x half> @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
half %2,
<vscale x 32 x i1> %3,
i32 %4)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
<vscale x 1 x float>,
float,
i32);
define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
<vscale x 2 x float>,
float,
i32);
define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
<vscale x 4 x float>,
float,
i32);
define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v26, v16, ft0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
<vscale x 8 x float>,
float,
i32);
define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v28, v16, ft0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
<vscale x 16 x float>,
float,
i32);
define <vscale x 16 x float> @intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v8, v16, ft0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
<vscale x 16 x float> %0,
float %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
float,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
float %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half>,
half,
i64);
define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i64 %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
<vscale x 2 x half>,
half,
i64);
define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i64 %2)
ret <vscale x 2 x half> %a
}
declare <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x half> @intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
<vscale x 4 x half>,
half,
i64);
define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i64 %2)
ret <vscale x 4 x half> %a
}
declare <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x half> @intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
<vscale x 8 x half>,
half,
i64);
define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v26, v16, ft0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i64 %2)
ret <vscale x 8 x half> %a
}
declare <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x half> @intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
<vscale x 16 x half>,
half,
i64);
define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v28, v16, ft0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i64 %2)
ret <vscale x 16 x half> %a
}
declare <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x half> @intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
<vscale x 32 x half>,
half,
i64);
define <vscale x 32 x half> @intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v8, v16, ft0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
<vscale x 32 x half> %0,
half %1,
i64 %2)
ret <vscale x 32 x half> %a
}
declare <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
half,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x half> @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: fmv.h.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
half %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
<vscale x 1 x float>,
float,
i64);
define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
<vscale x 2 x float>,
float,
i64);
define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
<vscale x 4 x float>,
float,
i64);
define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v26, v16, ft0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
<vscale x 8 x float>,
float,
i64);
define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v28, v16, ft0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
<vscale x 16 x float>,
float,
i64);
define <vscale x 16 x float> @intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v8, v16, ft0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
<vscale x 16 x float> %0,
float %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
float,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
float %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(
<vscale x 1 x double>,
double,
i64);
define <vscale x 1 x double> @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v25, v16, ft0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(
<vscale x 2 x double>,
double,
i64);
define <vscale x 2 x double> @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v26, v16, ft0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(
<vscale x 4 x double>,
double,
i64);
define <vscale x 4 x double> @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v28, v16, ft0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64(
<vscale x 8 x double>,
double,
i64);
define <vscale x 8 x double> @intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v8, v16, ft0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64(
<vscale x 8 x double> %0,
double %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
double,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: fmv.d.x ft0, a1
; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu
; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
double %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i32);
define <vscale x 1 x i8> @intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i8> @intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i32);
define <vscale x 2 x i8> @intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i8> @intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i32);
define <vscale x 4 x i8> @intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i8> @intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i32);
define <vscale x 8 x i8> @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i8> @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i32);
define <vscale x 16 x i8> @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x i8> @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i32);
define <vscale x 32 x i8> @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x i8> @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i32 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i32);
define <vscale x 64 x i8> @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i32);
define <vscale x 64 x i8> @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e8,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i32 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i32);
define <vscale x 1 x i16> @intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i16> @intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i32);
define <vscale x 2 x i16> @intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i16> @intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i32);
define <vscale x 4 x i16> @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i16> @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i32);
define <vscale x 8 x i16> @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i16> @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i32);
define <vscale x 16 x i16> @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x i16> @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i32);
define <vscale x 32 x i16> @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i32 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x i16> @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i32 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i32);
define <vscale x 1 x i32> @intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i32 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i32);
define <vscale x 2 x i32> @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i32 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i32);
define <vscale x 4 x i32> @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i32 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i32);
define <vscale x 8 x i32> @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i32 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i32);
define <vscale x 16 x i32> @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i32 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x i32> @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x i32> %a
}

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e8,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu
; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i32);
define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i32 %2)
ret <vscale x 1 x i8> %a
}

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v26, v16, a0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v28, v16, a0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v8, v16, a0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e8,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
i64 %4)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v26, v16, a0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v28, v16, a0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v8, v16, a0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e16,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v26, v16, a0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v28, v16, a0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v8, v16, a0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e32,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v25, v16, a0
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v26, v16, a0
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v28, v16, a0
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v8, v16, a0
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu
; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i64> %a
}