This is an archive of the discontinued LLVM Phabricator instance.

Differential D93583

[RISCV] Define vector vfwadd/vfwsub intrinsics.
ClosedPublic

Authored by HsiangKai on Dec 19 2020, 7:15 AM.

Details

Reviewers
craig.topper
evandro
frasercrmck
rogfer01
Commits
rGf86e61d8862f: [RISCV] Define vector vfwadd/vfwsub intrinsics.
Summary

Define vector vfwadd/vfwsub intrinsics and lower them to V
instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Diff Detail

Event Timeline

HsiangKai created this revision.Dec 19 2020, 7:15 AM
Herald added subscribers: NickHung, luismarques, apazos and 24 others. · View Herald TranscriptDec 19 2020, 7:15 AM
HsiangKai requested review of this revision.Dec 19 2020, 7:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 19 2020, 7:15 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B83049: Diff 312938.Dec 19 2020, 7:16 AM
craig.topper accepted this revision.Dec 19 2020, 11:13 AM

LGTM

This revision is now accepted and ready to land.Dec 19 2020, 11:13 AM
This revision was landed with ongoing or failed builds.Dec 20 2020, 2:00 AM
Closed by commit rGf86e61d8862f: [RISCV] Define vector vfwadd/vfwsub intrinsics. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGf86e61d8862f: [RISCV] Define vector vfwadd/vfwsub intrinsics..

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
5 lines
lib/
Target/
RISCV/
152 lines
test/
CodeGen/
RISCV/
rvv/
401 lines
721 lines
401 lines
721 lines
401 lines
721 lines
401 lines
721 lines

Diff 312938

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vwmul : RISCVBinaryABX; defm vwmul : RISCVBinaryABX;
defm vwmulu : RISCVBinaryABX; defm vwmulu : RISCVBinaryABX;
defm vwmulsu : RISCVBinaryABX; defm vwmulsu : RISCVBinaryABX;
defm vfadd : RISCVBinaryAAX; defm vfadd : RISCVBinaryAAX;
defm vfsub : RISCVBinaryAAX; defm vfsub : RISCVBinaryAAX;
defm vfrsub : RISCVBinaryAAX; defm vfrsub : RISCVBinaryAAX;
defm vfwadd : RISCVBinaryABX;
defm vfwsub : RISCVBinaryABX;
defm vfwadd_w : RISCVBinaryAAX;
defm vfwsub_w : RISCVBinaryAAX;
defm vsaddu : RISCVSaturatingBinaryAAX; defm vsaddu : RISCVSaturatingBinaryAAX;
defm vsadd : RISCVSaturatingBinaryAAX; defm vsadd : RISCVSaturatingBinaryAAX;
defm vssubu : RISCVSaturatingBinaryAAX; defm vssubu : RISCVSaturatingBinaryAAX;
defm vssub : RISCVSaturatingBinaryAAX; defm vssub : RISCVSaturatingBinaryAAX;
def int_riscv_vmv_v_v : RISCVUnary; def int_riscv_vmv_v_v : RISCVUnary;
def int_riscv_vmv_v_x : RISCVUnary; def int_riscv_vmv_v_x : RISCVUnary;
Show All 34 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Linesdefset list<VTypeInfoToWide> AllWidenableIntVectors = {
def : VTypeInfoToWide<VI16M4, VI32M8>; def : VTypeInfoToWide<VI16M4, VI32M8>;
def : VTypeInfoToWide<VI32MF2, VI64M1>; def : VTypeInfoToWide<VI32MF2, VI64M1>;
def : VTypeInfoToWide<VI32M1, VI64M2>; def : VTypeInfoToWide<VI32M1, VI64M2>;
def : VTypeInfoToWide<VI32M2, VI64M4>; def : VTypeInfoToWide<VI32M2, VI64M4>;
def : VTypeInfoToWide<VI32M4, VI64M8>; def : VTypeInfoToWide<VI32M4, VI64M8>;
} }
defset list<VTypeInfoToWide> AllWidenableFloatVectors = {
def : VTypeInfoToWide<VF16MF4, VF32MF2>;
def : VTypeInfoToWide<VF16MF2, VF32M1>;
def : VTypeInfoToWide<VF16M1, VF32M2>;
def : VTypeInfoToWide<VF16M2, VF32M4>;
def : VTypeInfoToWide<VF16M4, VF32M8>;
def : VTypeInfoToWide<VF32MF2, VF64M1>;
def : VTypeInfoToWide<VF32M1, VF64M2>;
def : VTypeInfoToWide<VF32M2, VF64M4>;
def : VTypeInfoToWide<VF32M4, VF64M8>;
}
// This class holds the record of the RISCVVPseudoTable below. // This class holds the record of the RISCVVPseudoTable below.
// This represents the information we need in codegen for each pseudo. // This represents the information we need in codegen for each pseudo.
// The definition should be consistent with `struct PseudoInfo` in // The definition should be consistent with `struct PseudoInfo` in
// RISCVBaseInfo.h. // RISCVBaseInfo.h.
class CONST8b<bits<8> val> { class CONST8b<bits<8> val> {
bits<8> V = val; bits<8> V = val;
} }
def InvalidIndex : CONST8b<0x80>; def InvalidIndex : CONST8b<0x80>;
▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
// at least 1, and the overlap is in the highest-numbered part of the // at least 1, and the overlap is in the highest-numbered part of the
// destination register group is legal. Otherwise, it is illegal. // destination register group is legal. Otherwise, it is illegal.
multiclass VPseudoBinaryW_VV { multiclass VPseudoBinaryW_VV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_VX { multiclass VPseudoBinaryW_VX<bit IsFloat> {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _VX : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m, defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.wvrclass, m.vrclass,
!if(!eq(IsFloat, 0), GPR, FPR32), m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WV { multiclass VPseudoBinaryW_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WX { multiclass VPseudoBinaryW_WX<bit IsFloat> {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WX : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, defm !if(!eq(IsFloat, 0), "_WX", "_WF") : VPseudoBinary<m.wvrclass, m.wvrclass,
!if(!eq(IsFloat, 0), GPR, FPR32), m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryV_WV { multiclass VPseudoBinaryV_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesmulticlass VPseudoBinaryV_VV_VX<bit IsFloat = 0> {
defm "" : VPseudoBinaryV_VX<IsFloat>; defm "" : VPseudoBinaryV_VX<IsFloat>;
} }
multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> { multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> {
defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>; defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>;
defm "" : VPseudoBinaryV_VI<ImmType>; defm "" : VPseudoBinaryV_VI<ImmType>;
} }
multiclass VPseudoBinaryW_VV_VX { multiclass VPseudoBinaryW_VV_VX<bit IsFloat = 0> {
defm "" : VPseudoBinaryW_VV; defm "" : VPseudoBinaryW_VV;
defm "" : VPseudoBinaryW_VX; defm "" : VPseudoBinaryW_VX<IsFloat>;
} }
multiclass VPseudoBinaryW_WV_WX { multiclass VPseudoBinaryW_WV_WX<bit IsFloat = 0> {
defm "" : VPseudoBinaryW_WV; defm "" : VPseudoBinaryW_WV;
defm "" : VPseudoBinaryW_WX; defm "" : VPseudoBinaryW_WX<IsFloat>;
} }
multiclass VPseudoBinaryV_VM_XM_IM { multiclass VPseudoBinaryV_VM_XM_IM {
defm "" : VPseudoBinaryV_VM; defm "" : VPseudoBinaryV_VM;
defm "" : VPseudoBinaryV_XM; defm "" : VPseudoBinaryV_XM;
defm "" : VPseudoBinaryV_IM; defm "" : VPseudoBinaryV_IM;
} }
▲ Show 20 Lines • Show All 308 Lines • ▼ Show 20 Linesmulticlass VPatBinaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand imm_type> { list<VTypeInfo> vtilist, Operand imm_type> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatBinary<intrinsic, instruction, "VI", defm : VPatBinary<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.RegClass, imm_type>; vti.RegClass, imm_type>;
} }
multiclass VPatBinaryW_VV<string intrinsic, string instruction> { multiclass VPatBinaryW_VV<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "VV", defm : VPatBinary<intrinsic, instruction, "VV",
Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask, Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,
Vti.SEW, Vti.LMul, Wti.RegClass, Vti.SEW, Vti.LMul, Wti.RegClass,
Vti.RegClass, Vti.RegClass>; Vti.RegClass, Vti.RegClass>;
} }
} }
multiclass VPatBinaryW_VX<string intrinsic, string instruction> { multiclass VPatBinaryW_VX<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "VX", defm : VPatBinary<intrinsic, instruction,
Wti.Vector, Vti.Vector, XLenVT, Vti.Mask, !if(!eq(Vti.Scalar, XLenVT), "VX", "VF"),
Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Vti.LMul, Wti.RegClass, Vti.SEW, Vti.LMul, Wti.RegClass,
Vti.RegClass, GPR>; Vti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryW_WV<string intrinsic, string instruction> { multiclass VPatBinaryW_WV<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "WV", defm : VPatBinary<intrinsic, instruction, "WV",
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
Vti.SEW, Vti.LMul, Wti.RegClass, Vti.SEW, Vti.LMul, Wti.RegClass,
Wti.RegClass, Vti.RegClass>; Wti.RegClass, Vti.RegClass>;
} }
} }
multiclass VPatBinaryW_WX<string intrinsic, string instruction> { multiclass VPatBinaryW_WX<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "WX", defm : VPatBinary<intrinsic, instruction,
Wti.Vector, Wti.Vector, XLenVT, Vti.Mask, !if(!eq(Vti.Scalar, XLenVT), "WX", "WF"),
Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Vti.LMul, Wti.RegClass, Vti.SEW, Vti.LMul, Wti.RegClass,
Wti.RegClass, GPR>; Wti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryV_WV<string intrinsic, string instruction> { multiclass VPatBinaryV_WV<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "WV", defm : VPatBinary<intrinsic, instruction, "WV",
Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
Vti.SEW, Vti.LMul, Vti.RegClass, Vti.SEW, Vti.LMul, Vti.RegClass,
Wti.RegClass, Vti.RegClass>; Wti.RegClass, Vti.RegClass>;
} }
} }
multiclass VPatBinaryV_WX<string intrinsic, string instruction> { multiclass VPatBinaryV_WX<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "WX", defm : VPatBinary<intrinsic, instruction,
Vti.Vector, Wti.Vector, XLenVT, Vti.Mask, !if(!eq(Vti.Scalar, XLenVT), "WX", "WF"),
Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Vti.LMul, Vti.RegClass, Vti.SEW, Vti.LMul, Vti.RegClass,
Wti.RegClass, GPR>; Wti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryV_WI<string intrinsic, string instruction> { multiclass VPatBinaryV_WI<string intrinsic, string instruction,
foreach VtiToWti = AllWidenableIntVectors in { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction, "WI", defm : VPatBinary<intrinsic, instruction, "WI",
Vti.Vector, Wti.Vector, XLenVT, Vti.Mask, Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
Vti.SEW, Vti.LMul, Vti.RegClass, Vti.SEW, Vti.LMul, Vti.RegClass,
Wti.RegClass, uimm5>; Wti.RegClass, uimm5>;
} }
} }
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction, multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist> list<VTypeInfo> vtilist>
{ {
defm "" : VPatBinaryV_VX<intrinsic, instruction, vtilist>; defm "" : VPatBinaryV_VX<intrinsic, instruction, vtilist>;
defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>; defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, simm5>;
} }
multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction> multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist>
{ {
defm "" : VPatBinaryW_VV<intrinsic, instruction>; defm "" : VPatBinaryW_VV<intrinsic, instruction, vtilist>;
defm "" : VPatBinaryW_VX<intrinsic, instruction>; defm "" : VPatBinaryW_VX<intrinsic, instruction, vtilist>;
} }
multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction> multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist>
{ {
defm "" : VPatBinaryW_WV<intrinsic, instruction>; defm "" : VPatBinaryW_WV<intrinsic, instruction, vtilist>;
defm "" : VPatBinaryW_WX<intrinsic, instruction>; defm "" : VPatBinaryW_WX<intrinsic, instruction, vtilist>;
} }
multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction> multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist>
{ {
defm "" : VPatBinaryV_WV<intrinsic, instruction>; defm "" : VPatBinaryV_WV<intrinsic, instruction, vtilist>;
defm "" : VPatBinaryV_WX<intrinsic, instruction>; defm "" : VPatBinaryV_WX<intrinsic, instruction, vtilist>;
defm "" : VPatBinaryV_WI<intrinsic, instruction>; defm "" : VPatBinaryV_WI<intrinsic, instruction, vtilist>;
} }
multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction> multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
{ {
defm "" : VPatBinaryV_VM<intrinsic, instruction>; defm "" : VPatBinaryV_VM<intrinsic, instruction>;
defm "" : VPatBinaryV_XM<intrinsic, instruction>; defm "" : VPatBinaryV_XM<intrinsic, instruction>;
defm "" : VPatBinaryV_IM<intrinsic, instruction>; defm "" : VPatBinaryV_IM<intrinsic, instruction>;
} }
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFADD : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFADD : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
defm PseudoVFSUB : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFSUB : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
defm PseudoVFRSUB : VPseudoBinaryV_VX</*IsFloat=*/1>; defm PseudoVFRSUB : VPseudoBinaryV_VX</*IsFloat=*/1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
defm PseudoVFWADD : VPseudoBinaryW_VV_VX</*IsFloat=*/1>;
defm PseudoVFWSUB : VPseudoBinaryW_VV_VX</*IsFloat=*/1>;
defm PseudoVFWADD : VPseudoBinaryW_WV_WX</*IsFloat=*/1>;
defm PseudoVFWSUB : VPseudoBinaryW_WV_WX</*IsFloat=*/1>;
//===----------------------------------------------------------------------===//
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFMUL : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFMUL : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
defm PseudoVFDIV : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; defm PseudoVFDIV : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
defm PseudoVFRDIV : VPseudoBinaryV_VX</*IsFloat=*/1>; defm PseudoVFRDIV : VPseudoBinaryV_VX</*IsFloat=*/1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vadd", "PseudoVADD", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vsub", "PseudoVSUB", AllIntegerVectors>;
defm "" : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>; defm "" : VPatBinaryV_VX_VI<"int_riscv_vrsub", "PseudoVRSUB", AllIntegerVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.2. Vector Widening Integer Add/Subtract // 12.2. Vector Widening Integer Add/Subtract
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwaddu", "PseudoVWADDU", AllWidenableIntVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsubu", "PseudoVWSUBU", AllWidenableIntVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwadd", "PseudoVWADD", AllWidenableIntVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwsub", "PseudoVWSUB", AllWidenableIntVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU">; defm "" : VPatBinaryW_WV_WX<"int_riscv_vwaddu_w", "PseudoVWADDU", AllWidenableIntVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU">; defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsubu_w", "PseudoVWSUBU", AllWidenableIntVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD">; defm "" : VPatBinaryW_WV_WX<"int_riscv_vwadd_w", "PseudoVWADD", AllWidenableIntVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB">; defm "" : VPatBinaryW_WV_WX<"int_riscv_vwsub_w", "PseudoVWSUB", AllWidenableIntVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions // 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">; defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vadc", "PseudoVADC">;
defm "" : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">; defm "" : VPatBinaryM_VM_XM_IM<"int_riscv_vmadc_carry_in", "PseudoVMADC">;
defm "" : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">; defm "" : VPatBinaryM_V_X_I<"int_riscv_vmadc", "PseudoVMADC">;
Show All 9 Lines
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors, defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,
uimm5>; uimm5>;
defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors, defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
uimm5>; uimm5>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL">; defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>;
defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA">; defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>; defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>;
defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>; defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>;
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmsltu", "PseudoVMSLTU", AllIntegerVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmsltu", "PseudoVMSLTU", AllIntegerVectors>;
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmslt", "PseudoVMSLT", AllIntegerVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmslt", "PseudoVMSLT", AllIntegerVectors>;
Show All 25 Lines
defm "" : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.12. Vector Widening Integer Multiply Instructions // 12.12. Vector Widening Integer Multiply Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU">; defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.17. Vector Integer Move Instructions // 12.17. Vector Integer Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach vti = AllVectors in { foreach vti = AllVectors in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1),
GPR:$vl)), GPR:$vl)),
(!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
Show All 23 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors>;
defm "" : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>; defm "" : VPatBinaryV_VX<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
defm "" : VPatBinaryW_VV_VX<"int_riscv_vfwadd", "PseudoVFWADD", AllWidenableFloatVectors>;
defm "" : VPatBinaryW_VV_VX<"int_riscv_vfwsub", "PseudoVFWSUB", AllWidenableFloatVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vfwadd_w", "PseudoVFWADD", AllWidenableFloatVectors>;
defm "" : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloatVectors>;
//===----------------------------------------------------------------------===//
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>;
defm "" : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>; defm "" : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>;
defm "" : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>; defm "" : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16.f16(
<vscale x 1 x half>,
half,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16.f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd_mask_vf_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16.f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16.f16(
<vscale x 2 x half>,
half,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16.f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd_mask_vf_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16.f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16.f16(
<vscale x 4 x half>,
half,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16.f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd_mask_vf_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16.f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16.f16(
<vscale x 8 x half>,
half,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16.f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd_mask_vf_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16.f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16.f16(
<vscale x 16 x half>,
half,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16.f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd_mask_vf_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16.f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16.f16(
<vscale x 1 x half>,
half,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16.f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd_mask_vf_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f16.f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16.f16(
<vscale x 2 x half>,
half,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16.f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd_mask_vf_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f16.f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16.f16(
<vscale x 4 x half>,
half,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16.f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd_mask_vf_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f16.f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16.f16(
<vscale x 8 x half>,
half,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16.f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd_mask_vf_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f16.f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16.f16(
<vscale x 16 x half>,
half,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16.f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd_mask_vf_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f16.f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f32.f32(
<vscale x 1 x float>,
float,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f32.f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd_mask_vf_nxv1f32_f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f32.f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f32.f32(
<vscale x 2 x float>,
float,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f32.f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd_mask_vf_nxv2f32_f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f32.f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f32.f32(
<vscale x 4 x float>,
float,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f32.f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd_mask_vf_nxv4f32_f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f32.f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f32.f32(
<vscale x 8 x float>,
float,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f32.f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd_mask_vf_nxv8f32_f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f32.f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float>,
half,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float> %0,
half %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wf_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float>,
half,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float> %0,
half %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wf_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float>,
half,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float> %0,
half %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wf_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float>,
half,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float> %0,
half %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wf_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float>,
half,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float> %0,
half %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wf_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd.w_wv_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd.w_wv_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd.w_wv_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_wv_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float>,
half,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float> %0,
half %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wf_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float>,
half,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float> %0,
half %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wf_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float>,
half,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float> %0,
half %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wf_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float>,
half,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float> %0,
half %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wf_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float>,
half,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float> %0,
half %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wf_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
<vscale x 1 x double>,
float,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd.w_wf_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
<vscale x 1 x double> %0,
float %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32(
<vscale x 1 x double>,
<vscale x 1 x double>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwadd.w_mask_wf_nxv1f64_f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.mask.nxv1f64.f32(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
<vscale x 2 x double>,
float,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd.w_wf_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
<vscale x 2 x double> %0,
float %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32(
<vscale x 2 x double>,
<vscale x 2 x double>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwadd.w_mask_wf_nxv2f64_f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.mask.nxv2f64.f32(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
<vscale x 4 x double>,
float,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd.w_wf_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
<vscale x 4 x double> %0,
float %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32(
<vscale x 4 x double>,
<vscale x 4 x double>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwadd.w_mask_wf_nxv4f64_f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.mask.nxv4f64.f32(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
<vscale x 8 x double>,
float,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_wf_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
<vscale x 8 x double> %0,
float %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32(
<vscale x 8 x double>,
<vscale x 8 x double>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wf_nxv8f64_f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.f32(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16.f16(
<vscale x 1 x half>,
half,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16.f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub_mask_vf_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16.f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16.f16(
<vscale x 2 x half>,
half,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16.f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub_mask_vf_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16.f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16.f16(
<vscale x 4 x half>,
half,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16.f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub_mask_vf_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16.f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16.f16(
<vscale x 8 x half>,
half,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16.f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub_mask_vf_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16.f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16.f16(
<vscale x 16 x half>,
half,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16.f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub_mask_vf_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16.f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f16_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f16_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f16_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f16_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f16_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16.f16(
<vscale x 1 x half>,
half,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16.f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub_mask_vf_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f16.f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16.f16(
<vscale x 2 x half>,
half,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16.f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub_mask_vf_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f16.f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16.f16(
<vscale x 4 x half>,
half,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16.f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub_mask_vf_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f16.f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16.f16(
<vscale x 8 x half>,
half,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16.f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub_mask_vf_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f16.f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16.f16(
<vscale x 16 x half>,
half,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16.f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub_mask_vf_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f16.f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f32.f32(
<vscale x 1 x float>,
float,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f32.f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub_mask_vf_nxv1f32_f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f32.f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f32.f32(
<vscale x 2 x float>,
float,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f32.f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub_mask_vf_nxv2f32_f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f32.f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f32.f32(
<vscale x 4 x float>,
float,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f32.f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub_mask_vf_nxv4f32_f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f32.f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f32.f32(
<vscale x 8 x float>,
float,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f32.f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub_mask_vf_nxv8f32_f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f32.f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

  • This file was added.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float>,
half,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float> %0,
half %1,
i32 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
half,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
half %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float>,
half,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float> %0,
half %1,
i32 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
half,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
half %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float>,
half,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float> %0,
half %1,
i32 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
half,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
half %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float>,
half,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float> %0,
half %1,
i32 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
half,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
half %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float>,
half,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float> %0,
half %1,
i32 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
half,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
half %2,
<vscale x 16 x i1> %3,
i32 %4)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

  • This file was added.
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x half> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x half> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x half> %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x half> %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x half> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x half> %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x half> %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x float> %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x float>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x float> %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f32(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x float>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x float> %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f32(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x float> %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x float>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x float> %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f32(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x float> %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float>,
half,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float> %0,
half %1,
i64 %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float>,
<vscale x 1 x float>,
half,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
half %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float>,
half,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float> %0,
half %1,
i64 %2)
ret <vscale x 2 x float> %a
}
declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float>,
<vscale x 2 x float>,
half,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
half %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float>,
half,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float> %0,
half %1,
i64 %2)
ret <vscale x 4 x float> %a
}
declare <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float>,
<vscale x 4 x float>,
half,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
half %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float>,
half,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float> %0,
half %1,
i64 %2)
ret <vscale x 8 x float> %a
}
declare <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float>,
<vscale x 8 x float>,
half,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
half %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float>,
half,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float> %0,
half %1,
i64 %2)
ret <vscale x 16 x float> %a
}
declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float>,
<vscale x 16 x float>,
half,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
half %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x float> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double>,
float,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double> %0,
float %1,
i64 %2)
ret <vscale x 1 x double> %a
}
declare <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(
<vscale x 1 x double>,
<vscale x 1 x double>,
float,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_nxv1f64_f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
float %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double>,
float,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double> %0,
float %1,
i64 %2)
ret <vscale x 2 x double> %a
}
declare <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(
<vscale x 2 x double>,
<vscale x 2 x double>,
float,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_nxv2f64_f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
float %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double>,
float,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double> %0,
float %1,
i64 %2)
ret <vscale x 4 x double> %a
}
declare <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(
<vscale x 4 x double>,
<vscale x 4 x double>,
float,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_nxv4f64_f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
float %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double>,
float,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double> %0,
float %1,
i64 %2)
ret <vscale x 8 x double> %a
}
declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(
<vscale x 8 x double>,
<vscale x 8 x double>,
float,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_nxv8f64_f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
float %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x double> %a
}