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Differential D93048

[RISCV] Define vsub/vrsub intrinsics and refine the multiclass/class.
AbandonedPublic

Authored by HsiangKai on Dec 10 2020, 9:04 AM.

Details

Reviewers
craig.topper
evandro
luismarques
frasercrmck
rogfer01
pshung
Summary

Define vsub/vrsub intrinsics and demonstrate the organization of multiclasses and classes for pseudo instructions and patterns.

The CodeGen strategy is designed by @rogfer01 from BSC.

Diff Detail

Event Timeline

HsiangKai created this revision.Dec 10 2020, 9:04 AM
Herald added subscribers: NickHung, apazos, sameer.abuasal and 23 others. · View Herald TranscriptDec 10 2020, 9:04 AM
HsiangKai requested review of this revision.Dec 10 2020, 9:04 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 10 2020, 9:04 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B81862: Diff 310925.Dec 10 2020, 9:08 AM
HsiangKai added a comment.Dec 10 2020, 9:08 AM

Should I combine this one with D93048?

vsub only has .vv and .vx variants.
vrsub only has .vx and .vi variants.

I use these two instructions to reorganize multiclasses and classes in RISCVInstrInfoVPseudos.td.

These two patches are related. I am not sure whether I should combine them or not.

HsiangKai edited the summary of this revision. (Show Details)Dec 10 2020, 9:12 AM
craig.topper added a comment.Dec 10 2020, 1:50 PM
In D93048#2446197, @HsiangKai wrote:

Should I combine this one with D93048?

vsub only has .vv and .vx variants.
vrsub only has .vx and .vi variants.

I use these two instructions to reorganize multiclasses and classes in RISCVInstrInfoVPseudos.td.

These two patches are related. I am not sure whether I should combine them or not.

I vote to combine them since this redoes a lot of the tablegen classes. It would be better to only have one version to review

craig.topper added a reviewer: pshung.Dec 10 2020, 5:00 PM
HsiangKai mentioned this in D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..Dec 10 2020, 5:30 PM
HsiangKai abandoned this revision.Dec 10 2020, 5:37 PM

Combined into D93013.

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
2 lines
lib/
Target/
RISCV/
230 lines
test/
CodeGen/
RISCV/
rvv/
1499 lines
1763 lines

Diff 310925

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
} }
multiclass riscv_binary { multiclass riscv_binary {
def "int_riscv_" # NAME : RVVBinaryCommon; def "int_riscv_" # NAME : RVVBinaryCommon;
def "int_riscv_" # NAME # "_mask" : RVVBinaryCommonMask; def "int_riscv_" # NAME # "_mask" : RVVBinaryCommonMask;
} }
defm vadd : riscv_binary; defm vadd : riscv_binary;
defm vsub : riscv_binary;
defm vrsub : riscv_binary;
} // TargetPrefix = "riscv" } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Lines
} }
multiclass VPseudoBinary_VV_VX_VI<Operand ImmType = simm5> { multiclass VPseudoBinary_VV_VX_VI<Operand ImmType = simm5> {
defm "" : VPseudoBinaryV_VV; defm "" : VPseudoBinaryV_VV;
defm "" : VPseudoBinaryV_VX; defm "" : VPseudoBinaryV_VX;
defm "" : VPseudoBinaryV_VI<ImmType>; defm "" : VPseudoBinaryV_VI<ImmType>;
} }
multiclass VPseudoBinary_VV_VX {
defm "" : VPseudoBinaryV_VV;
defm "" : VPseudoBinaryV_VX;
}
multiclass VPseudoBinary_VX_VI<Operand ImmType = simm5> {
defm "" : VPseudoBinaryV_VX;
defm "" : VPseudoBinaryV_VI<ImmType>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Helpers to define the different patterns. // Helpers to define the different patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class VPatBinarySDNode<SDNode vop,
multiclass pat_vop_binary<SDNode vop,
string instruction_name, string instruction_name,
ValueType result_type, ValueType result_type,
ValueType op_type, ValueType op_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg RetClass, VReg RetClass,
VReg op_reg_class> VReg op_reg_class> :
{ Pat<(result_type (vop
defvar instruction = !cast<Instruction>(instruction_name#"_VV_"# vlmul.MX);
def : Pat<(result_type (vop
(op_type op_reg_class:$rs1), (op_type op_reg_class:$rs1),
(op_type op_reg_class:$rs2))), (op_type op_reg_class:$rs2))),
(instruction op_reg_class:$rs1, (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
op_reg_class:$rs1,
op_reg_class:$rs2, op_reg_class:$rs2,
VLMax, sew)>; VLMax, sew)>;
}
multiclass pat_vop_binary_common<SDNode vop, multiclass VPatBinarySDNode<SDNode vop, string instruction_name>
string instruction_name,
list<VTypeInfo> vtilist>
{ {
foreach vti = vtilist in foreach vti = AllIntegerVectors in
defm : pat_vop_binary<vop, instruction_name, def : VPatBinarySDNode<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.SEW, vti.Vector, vti.Vector, vti.Mask, vti.SEW,
vti.LMul, vti.RegClass, vti.RegClass>; vti.LMul, vti.RegClass, vti.RegClass>;
} }
multiclass pat_intrinsic_binary<string intrinsic_name, class VPatBinary<string intrinsic_name,
string instruction_name, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> DAGOperand op2_kind> :
{ Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
defvar inst = !cast<Instruction>(instruction_name#_#kind#"_"# vlmul.MX);
defvar inst_mask = !cast<Instruction>(instruction_name#_#kind#"_"# vlmul.MX#"_MASK");
def : Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(i64 GPR:$vl))), (i64 GPR:$vl))),
(inst (op1_type op1_reg_class:$rs1), (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
(op1_type op1_reg_class:$rs1),
ToFPR32<op2_type, op2_kind, "rs2">.ret, ToFPR32<op2_type, op2_kind, "rs2">.ret,
(NoX0 GPR:$vl), sew)>; (NoX0 GPR:$vl), sew)>;
def : Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") class VPatBinaryMask<string intrinsic_name,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
VReg op1_reg_class,
DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(mask_type V0), (mask_type V0),
(i64 GPR:$vl))), (i64 GPR:$vl))),
(inst_mask (result_type result_reg_class:$merge), (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
(result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
ToFPR32<op2_type, op2_kind, "rs2">.ret, ToFPR32<op2_type, op2_kind, "rs2">.ret,
(mask_type V0), (NoX0 GPR:$vl), sew)>; (mask_type V0), (NoX0 GPR:$vl), sew)>;
}
multiclass pat_intrinsic_binary_int_v_vv_vx_vi<string intrinsic_name, multiclass VPatBinary<string intrinsic,
string instruction_name, string inst,
Operand imm_type = simm5> string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
VReg op1_reg_class,
DAGOperand op2_kind>
{ {
def : VPatBinary<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
def : VPatBinaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
}
multiclass VPatBinaryV_VV<string intrinsic, string instruction> {
foreach vti = AllIntegerVectors in foreach vti = AllIntegerVectors in
{ defm : VPatBinary<intrinsic, instruction, "VV",
defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VX", }
multiclass VPatBinaryV_VX<string intrinsic, string instruction> {
foreach vti = AllIntegerVectors in
defm : VPatBinary<intrinsic, instruction, "VX",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.RegClass, GPR>; vti.RegClass, GPR>;
defm : pat_intrinsic_binary<intrinsic_name, instruction_name, "VI", }
multiclass VPatBinaryV_VI<string intrinsic, string instruction, Operand imm_type> {
foreach vti = AllIntegerVectors in
defm : VPatBinary<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.RegClass, imm_type>; vti.RegClass, imm_type>;
} }
multiclass VPatBinary_VV_VX_VI<string intrinsic,
string instruction,
Operand imm_type = simm5>
{
defm "" : VPatBinaryV_VV<intrinsic, instruction>;
defm "" : VPatBinaryV_VX<intrinsic, instruction>;
defm "" : VPatBinaryV_VI<intrinsic, instruction, imm_type>;
}
multiclass VPatBinary_VV_VX<string intrinsic,
string instruction>
{
defm "" : VPatBinaryV_VV<intrinsic, instruction>;
defm "" : VPatBinaryV_VX<intrinsic, instruction>;
}
multiclass VPatBinary_VX_VI<string intrinsic,
string instruction,
Operand imm_type = simm5>
{
defm "" : VPatBinaryV_VX<intrinsic, instruction>;
defm "" : VPatBinaryV_VI<intrinsic, instruction, imm_type>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions and patterns. // Pseudo instructions and patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.1. Vector Single-Width Integer Add and Subtract // 12.1. Vector Single-Width Integer Add and Subtract
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions. // Pseudo instructions.
defm PseudoVADD : VPseudoBinary_VV_VX_VI; defm PseudoVADD : VPseudoBinary_VV_VX_VI;
defm PseudoVSUB : VPseudoBinary_VV_VX;
defm PseudoVRSUB : VPseudoBinary_VX_VI;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Whole-register vector patterns. // Whole-register vector patterns.
defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>; defm "" : VPatBinarySDNode<add, "PseudoVADD">;
defm "" : pat_intrinsic_binary_int_v_vv_vx_vi<"int_riscv_vadd", "PseudoVADD">; defm "" : VPatBinary_VV_VX_VI<"int_riscv_vadd", "PseudoVADD">;
defm "" : VPatBinary_VV_VX<"int_riscv_vsub", "PseudoVSUB">;
defm "" : VPatBinary_VX_VI<"int_riscv_vrsub", "PseudoVRSUB">;
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]

llvm/test/CodeGen/RISCV/rvv/vrsub.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
<vscale x 1 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
i8 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
<vscale x 2 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
i8 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
<vscale x 4 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
i8 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
<vscale x 8 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
i8 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
<vscale x 16 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
i8 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
<vscale x 32 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
i8 undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
<vscale x 64 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
i8 undef,
<vscale x 64 x i1> undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
<vscale x 1 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
i16 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
<vscale x 2 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
i16 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
<vscale x 4 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
i16 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
<vscale x 8 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
i16 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
<vscale x 16 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
i16 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
<vscale x 32 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
i16 undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
<vscale x 1 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
i32 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
<vscale x 2 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
i32 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
<vscale x 4 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
i32 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
<vscale x 8 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
i32 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
<vscale x 16 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
i32 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
<vscale x 1 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
i64 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
<vscale x 2 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
i64 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
<vscale x 4 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
i64 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
<vscale x 8 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
i64 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i64> %a
}
define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
<vscale x 1 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
i8 9,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
<vscale x 2 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 2 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
i8 9,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
<vscale x 4 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 4 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
i8 9,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
<vscale x 8 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 8 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
i8 9,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
<vscale x 16 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 16 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
i8 9,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
<vscale x 32 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 32 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
i8 9,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
<vscale x 64 x i8> undef,
i8 9,
i64 undef)
ret <vscale x 64 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
i8 9,
<vscale x 64 x i1> undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
<vscale x 1 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 1 x i16> %a
}
define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
i16 9,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
<vscale x 2 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 2 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
i16 9,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
<vscale x 4 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 4 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
i16 9,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
<vscale x 8 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 8 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
i16 9,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
<vscale x 16 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 16 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
i16 9,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
<vscale x 32 x i16> undef,
i16 9,
i64 undef)
ret <vscale x 32 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
i16 9,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
<vscale x 1 x i32> undef,
i32 9,
i64 undef)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
i32 9,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
<vscale x 2 x i32> undef,
i32 9,
i64 undef)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
i32 9,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
<vscale x 4 x i32> undef,
i32 9,
i64 undef)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
i32 9,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
<vscale x 8 x i32> undef,
i32 9,
i64 undef)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
i32 9,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
<vscale x 16 x i32> undef,
i32 9,
i64 undef)
ret <vscale x 16 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
i32 9,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
<vscale x 1 x i64> undef,
i64 9,
i64 undef)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
i64 9,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
<vscale x 2 x i64> undef,
i64 9,
i64 undef)
ret <vscale x 2 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
i64 9,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
<vscale x 4 x i64> undef,
i64 9,
i64 undef)
ret <vscale x 4 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
i64 9,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
<vscale x 8 x i64> undef,
i64 9,
i64 undef)
ret <vscale x 8 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
i64 9,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vsub.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i64);
define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i64);
define <vscale x 2 x i8> @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i64);
define <vscale x 4 x i8> @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i64);
define <vscale x 8 x i8> @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i64);
define <vscale x 16 x i8> @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i64);
define <vscale x 32 x i8> @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i64);
define <vscale x 64 x i8> @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
<vscale x 64 x i1> undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i64);
define <vscale x 1 x i16> @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i64);
define <vscale x 2 x i16> @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i64);
define <vscale x 4 x i16> @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i64);
define <vscale x 8 x i16> @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i64);
define <vscale x 16 x i16> @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i64);
define <vscale x 32 x i16> @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i64);
define <vscale x 1 x i32> @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i64);
define <vscale x 2 x i32> @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i64);
define <vscale x 4 x i32> @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i64);
define <vscale x 8 x i32> @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i64);
define <vscale x 16 x i32> @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64);
define <vscale x 1 x i64> @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64);
define <vscale x 2 x i64> @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64);
define <vscale x 4 x i64> @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64);
define <vscale x 8 x i64> @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
i64 undef)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i8> @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
<vscale x 1 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i8> @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> undef,
i8 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i8> @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
<vscale x 2 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i8> @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i8> undef,
i8 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i8> @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
<vscale x 4 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i8> @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i8> undef,
i8 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i8> @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
<vscale x 8 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i8> @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i8> undef,
i8 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i8> @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
<vscale x 16 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i8> @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i8> undef,
i8 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i8> @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
<vscale x 32 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i8> @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i8> undef,
i8 undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
i64);
define <vscale x 64 x i8> @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
<vscale x 64 x i8> undef,
i8 undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
i64);
define <vscale x 64 x i8> @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8
; CHECK: vsetvli {{.*}}, a0, e8,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i8> undef,
i8 undef,
<vscale x 64 x i1> undef,
i64 undef)
ret <vscale x 64 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i16> @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
<vscale x 1 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i16> undef,
i16 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i16> @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
<vscale x 2 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i16> undef,
i16 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i16> @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
<vscale x 4 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i16> undef,
i16 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i16> @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
<vscale x 8 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i16> undef,
i16 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i16> @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
<vscale x 16 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i16> undef,
i16 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
i64);
define <vscale x 32 x i16> @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
<vscale x 32 x i16> undef,
i16 undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16
; CHECK: vsetvli {{.*}}, a0, e16,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i16> undef,
i16 undef,
<vscale x 32 x i1> undef,
i64 undef)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i32> @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
<vscale x 1 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,mf2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i32> undef,
i32 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i32> @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
<vscale x 2 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i32> undef,
i32 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i32> @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
<vscale x 4 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> undef,
i32 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i32> @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
<vscale x 8 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> undef,
i32 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
i64);
define <vscale x 16 x i32> @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
<vscale x 16 x i32> undef,
i32 undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32
; CHECK: vsetvli {{.*}}, a0, e32,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> undef,
i32 undef,
<vscale x 16 x i1> undef,
i64 undef)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
<vscale x 1 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m1
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> undef,
i64 undef,
<vscale x 1 x i1> undef,
i64 undef)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
<vscale x 2 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m2
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> undef,
i64 undef,
<vscale x 2 x i1> undef,
i64 undef)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
<vscale x 4 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m4
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> undef,
i64 undef,
<vscale x 4 x i1> undef,
i64 undef)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
i64);
define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
<vscale x 8 x i64> undef,
i64 undef,
i64 undef)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64() nounwind {
entry:
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64
; CHECK: vsetvli {{.*}}, a0, e64,m8
; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> undef,
i64 undef,
<vscale x 8 x i1> undef,
i64 undef)
ret <vscale x 8 x i64> %a
}