[PowerPC] Lump the constants to save one addis for each constant access

[stefanp]

Summary

For now, we are placing the constant into TOC and whenever it is accessed, we need addis/addi + load. See:

double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }

And this is what we have now:

        addis 2, 12, .TOC.-.Lfunc_gep0@ha
        addi 2, 2, .TOC.-.Lfunc_gep0@l
.Lfunc_lep0:
        .localentry     X, .Lfunc_lep0-.Lfunc_gep0
# %bb.0:                                # %entry
        addis 3, 2, .LCPI0_0@toc@ha
        lfd 0, .LCPI0_0@toc@l(3)             #<-- addi is folding into lfd
        addis 3, 2, .LCPI0_1@toc@ha
        xsmuldp 0, 1, 0
        lfd 1, .LCPI0_1@toc@l(3)
        addis 3, 2, .LCPI0_2@toc@ha
        xsadddp 0, 0, 1
        lfd 1, .LCPI0_2@toc@l(3)
        addis 3, 2, .LCPI0_3@toc@ha
        xsmuldp 0, 0, 1
        lfd 1, .LCPI0_3@toc@l(3)
        xsadddp 1, 0, 1
        blr

It can be optimized as grouping all the constants together into RO data section, so that their relative positions are fixed. Then, create a symbol in TOC which point to that data section. The benefit for this optimization is to reduce the GOT size and improve the performance as the addis is saved. It works like this:

        .section        .data.rel.ro,"aw",@progbits
        .p2align        3                               # -- Begin function X
.LCPI0_0:
        .quad   0x402cc28f5c28f5c3              # double 14.380000000000001
        .quad   0x4002b851eb851eb8              # double 2.3399999999999999
        .quad   0x40120c49ba5e353f              # double 4.5119999999999996
        .quad   0x3ff3ae147ae147ae              # double 1.23
.Lfunc_gep0:
        addis 2, 12, .TOC.-.Lfunc_gep0@ha
        addi 2, 2, .TOC.-.Lfunc_gep0@l
.Lfunc_lep0:
        .localentry     X, .Lfunc_lep0-.Lfunc_gep0
# %bb.0:                                # %entry
        addis 3, 2, .LC0@toc@ha
        ld 3, .LC0@toc@l(3)
        lfd 0, 24(3)
        xsmuldp 0, 1, 0
        lfd 1, 16(3)
        xsadddp 0, 0, 1
        lfd 1, 8(3)
        xsmuldp 0, 0, 1
        lfdx 1, 0, 3
        xsadddp 1, 0, 1
        blr

.LC0:
        .tc .LCPI0_0[TC],.LCPI0_0

This optimization has been discussed before. See PowerPC/README.txt for more information.

Lump the constant pool for each function into ONE pic object, and reference
pieces of it as offsets from the start.  For functions like this (contrived
to have lots of constants obviously):

double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }

We generate:

_X:
        lis r2, ha16(.CPI_X_0)
        lfd f0, lo16(.CPI_X_0)(r2)
        lis r2, ha16(.CPI_X_1)
        lfd f2, lo16(.CPI_X_1)(r2)
        fmadd f0, f1, f0, f2
        lis r2, ha16(.CPI_X_2)
        lfd f1, lo16(.CPI_X_2)(r2)
        lis r2, ha16(.CPI_X_3)
        lfd f2, lo16(.CPI_X_3)(r2)
        fmadd f1, f0, f1, f2
        blr

It would be better to materialize .CPI_X into a register, then use immediates
off of the register to avoid the lis's.  This is even more important in PIC
mode.

Note that this (and the static variable version) is discussed here for GCC:
http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html

Here's another example (the sgn function):
double testf(double a) {
       return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
}

it produces a BB like this:
LBB1_1: ; cond_true
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        lis r2, ha16(LCPI1_1)
        lis r3, ha16(LCPI1_2)
        lfs f2, lo16(LCPI1_2)(r3)
        lfs f3, lo16(LCPI1_1)(r2)
        fsub f0, f0, f1
        fsel f1, f0, f2, f3
        blr

Some limitation:

• If there is only one constant, we will have one extra load with this patch. But the load could be optimized by linker if it merges the TOC. It is not easy inside compiler to handle it as ISEL is done basing on per BB, and we don't know if there are other constants until other BBs are selected. Any thoughts ?
• Lump the constant with the same type. Technical speaking, all the constants could be lumped together as far as the alignment is handle carefully.

[steven.zhang]

Rebase test.

[steven.zhang]

Gentle ping.

[steven.zhang]

Gentle ping ...

[qiucf]

If there is only one constant, we will have one extra load with this patch. But the load could be optimized by linker if it merges the TOC. It is not easy inside compiler to handle it as ISEL is done basing on per BB, and we don't know if there are other constants until other BBs are selected. Any thoughts ?

As discussed, FunctionLoweringInfo is 'global' to SelectionDAG. Can we take advantage of it to record some global information? FunctionLoweringInfo::set has already scanned over each BB, each instruction.

Also, test changes in this patch are really huge. Are they all related?

llvm/test/CodeGen/PowerPC/constant-pool.ll

26

Regression?

[steven.zhang]

That means we have to make it as target independent. I will take a look to see if there is nice way to make it as target independent.

[steven.zhang]

Rebase the patch.

[steven.zhang]

In D91053#2459632, @qiucf wrote:

If there is only one constant, we will have one extra load with this patch. But the load could be optimized by linker if it merges the TOC. It is not easy inside compiler to handle it as ISEL is done basing on per BB, and we don't know if there are other constants until other BBs are selected. Any thoughts ?

As discussed, FunctionLoweringInfo is 'global' to SelectionDAG. Can we take advantage of it to record some global information? FunctionLoweringInfo::set has already scanned over each BB, each instruction.

The FunctionLoweringInfo won't help as we will do the transformation during the DAGCombine and it could remove/add new constants that cause the out of sync.

Also, test changes in this patch are really huge. Are they all related?

Yes, they are all relative as we are changing the basic of access the constant pool.

[steven.zhang]

llvm/test/CodeGen/PowerPC/constant-pool.ll

26

Yes, we will produce an extra load if there is single constant. But the linker will optimize away this extra load.

[nemanjai]

In D91053#2465584, @steven.zhang wrote:

Rebase the patch.

Huh? Something wrong with this rebase? Not only is there an issue with getSize() I pointed out, but there are also uses of non-existent functions:

PPCISelLowering.h:740:61: error: only virtual member functions can be marked 'override'
                            unsigned TargetFlags = 0) const override;
                                                            ^~~~~~~~
PPCISelLowering.cpp:2997:12: error: no member named 'getConstantPool' in 'llvm::TargetLowering'; did you mean simply 'getConstantPool'?
    return TargetLowering::getConstantPool(C, DAG, NewAlign, VT, Alignment,
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           getConstantPool
PPCISelLowering.cpp:2987:28: note: 'getConstantPool' declared here
SDValue PPCTargetLowering::getConstantPool(const Constant *C, SelectionDAG &DAG,
                           ^
PPCISelLowering.cpp:3018:12: error: no member named 'getConstantPool' in 'llvm::TargetLowering'; did you mean simply 'getConstantPool'?
    return TargetLowering::getConstantPool(C, DAG, NewAlign, VT, Alignment,
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           getConstantPool
PPCISelLowering.cpp:2987:28: note: 'getConstantPool' declared here
SDValue PPCTargetLowering::getConstantPool(const Constant *C, SelectionDAG &DAG,
                           ^
3 errors generated.

Also, I don't see adequate testing here (it may be hidden among all the test case changes and I missed it). There should be a test case with multiple constants loaded from the constant pool for all the types as well as for mixed types. AFAICT most of the test changes are single constants getting their own symbol in the TOC - which neither adequately tests this feature nor provides improvements of any kind (as pointed out in the description).

llvm/lib/Target/PowerPC/PPCConstantPoolValue.h

29

If the returned vector is const, why do we copy it?

33

Is this an issue with the particular revision you developed this on? The base class doesn't have this as a virtual member function so compilation fails because of override.

[steven.zhang]

In D91053#2466091, @nemanjai wrote:

In D91053#2465584, @steven.zhang wrote:

Rebase the patch.

Huh? Something wrong with this rebase? Not only is there an issue with getSize() I pointed out, but there are also uses of non-existent functions:

PPCISelLowering.h:740:61: error: only virtual member functions can be marked 'override'
                            unsigned TargetFlags = 0) const override;
                                                            ^~~~~~~~
PPCISelLowering.cpp:2997:12: error: no member named 'getConstantPool' in 'llvm::TargetLowering'; did you mean simply 'getConstantPool'?
    return TargetLowering::getConstantPool(C, DAG, NewAlign, VT, Alignment,
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           getConstantPool
PPCISelLowering.cpp:2987:28: note: 'getConstantPool' declared here
SDValue PPCTargetLowering::getConstantPool(const Constant *C, SelectionDAG &DAG,
                           ^
PPCISelLowering.cpp:3018:12: error: no member named 'getConstantPool' in 'llvm::TargetLowering'; did you mean simply 'getConstantPool'?
    return TargetLowering::getConstantPool(C, DAG, NewAlign, VT, Alignment,
           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           getConstantPool
PPCISelLowering.cpp:2987:28: note: 'getConstantPool' declared here
SDValue PPCTargetLowering::getConstantPool(const Constant *C, SelectionDAG &DAG,
                           ^
3 errors generated.

Also, I don't see adequate testing here (it may be hidden among all the test case changes and I missed it). There should be a test case with multiple constants loaded from the constant pool for all the types as well as for mixed types. AFAICT most of the test changes are single constants getting their own symbol in the TOC - which neither adequately tests this feature nor provides improvements of any kind (as pointed out in the description).

There are two parent revisions that this patch depends on. You need to apply them first. I will add a new test to summarize all the pattern we can handle.

[steven.zhang]

The test you are looking for is llvm/test/CodeGen/PowerPC/constant-pool.ll in fact.

[nemanjai]

In D91053#2467198, @steven.zhang wrote:

In D91053#2466091, @nemanjai wrote:

In D91053#2465584, @steven.zhang wrote:

There are two parent revisions that this patch depends on. You need to apply them first. I will add a new test to summarize all the pattern we can handle.

Which ones? I don't see them listed in "Parent Revisions"

[nemanjai]

In D91053#2467200, @steven.zhang wrote:

The test you are looking for is llvm/test/CodeGen/PowerPC/constant-pool.ll in fact.

Not quite. There seems to only be float/double/double double/vector and only for P9/P10. What happens with:

1. enough constants that the load is widened
2. what happens with -mcpu=pwr8 to see the impact of this when there are no D-Form loads for vectors

Also, the test case with multiple constants should show the constant pool (including alignment).
A simple example exhibiting this behaviour would be something like

void test(double *ArrD, unsigned short *ArrS, float *ArrF) {
// Ensure that these are still widened to 8b + 4b + 2b
  ArrS[0] = 12;
  ArrS[1] = 44;
  ArrS[2] = 8;
  ArrS[3] = 98;
  ArrS[4] = 271;
  ArrS[5] = 888;
  ArrS[6] = 99;

// These are not vectorized, check 4b alignment
  ArrF[0] += 999.88f;
  ArrF[1] += 861.15f;

// These are vectorized, check 16b alignment
  ArrD[0] = 342.2312;
  ArrD[1] = 664435.988;
  ArrD[3] = 12.222;
  ArrD[4] = 12.222;

// Check 8b alignment
  ArrD[5] += 2377.797889;
}

[steven.zhang]

In D91053#2467480, @nemanjai wrote:

In D91053#2467198, @steven.zhang wrote:

In D91053#2466091, @nemanjai wrote:

In D91053#2465584, @steven.zhang wrote:

There are two parent revisions that this patch depends on. You need to apply them first. I will add a new test to summarize all the pattern we can handle.

Which ones? I don't see them listed in "Parent Revisions"

The parent revision is D91050 and D89108.

llvm/lib/Target/PowerPC/PPCConstantPoolValue.h

29

Good catch.

[steven.zhang]

Address comments and add tests in llvm/test/CodeGen/PowerPC/constant-pool.ll to show the padding added for alignment. Also, add the RUN line for Power8 as requested.

[steven.zhang]

In D91053#2467539, @nemanjai wrote:

In D91053#2467200, @steven.zhang wrote:

The test you are looking for is llvm/test/CodeGen/PowerPC/constant-pool.ll in fact.

Not quite. There seems to only be float/double/double double/vector and only for P9/P10. What happens with:

1. enough constants that the load is widened

IIUC, we won't have any impact on the optimization of DAG as what we changed is on the step that legalize the constant pool, which is done after DAGCombine. Anyway, I will add this test point with your test.

2. what happens with -mcpu=pwr8 to see the impact of this when there are no D-Form loads for vectors

It is done.

Also, the test case with multiple constants should show the constant pool (including alignment).

Good suggestion. It is done.

A simple example exhibiting this behaviour would be something like

void test(double *ArrD, unsigned short *ArrS, float *ArrF) {
// Ensure that these are still widened to 8b + 4b + 2b
  ArrS[0] = 12;
  ArrS[1] = 44;
  ArrS[2] = 8;
  ArrS[3] = 98;
  ArrS[4] = 271;
  ArrS[5] = 888;
  ArrS[6] = 99;

// These are not vectorized, check 4b alignment
  ArrF[0] += 999.88f;
  ArrF[1] += 861.15f;

// These are vectorized, check 16b alignment
  ArrD[0] = 342.2312;
  ArrD[1] = 664435.988;
  ArrD[3] = 12.222;
  ArrD[4] = 12.222;

// Check 8b alignment
  ArrD[5] += 2377.797889;
}

Thank for for the test. I have added into constant-pool.ll

[steven.zhang]

The dependent patch changed. Need rebase.

[steven.zhang]

Rebase the patch again.

[qiucf]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1526

Can this also support AIX?

[nemanjai]

I believe this still depends on https://reviews.llvm.org/D91050 which isn't really generating much support. If this is still dependent on that, can you please address the comments on the dependent patch? If it no longer depends on that patch, please commandeer that one as well and abandon it.

[lkail]

A few months ago, steven shared his patch to us. For me, it should be an optimization of TOC layout, it looks odd to me to get it done at isel phase. I think we should figure out a new approach for this. What do you think @nemanjai @qiucf ?

I tend to not pursue this patch and might have a new one to get TOC layout optimization done.

[qiucf]

In D91053#2912191, @lkail wrote:

A few months ago, steven shared his patch to us. For me, it should be an optimization of TOC layout, it looks odd to me to get it done at isel phase. I think we should figure out a new approach for this. What do you think @nemanjai @qiucf ?

I tend to not pursue this patch and might have a new one to get TOC layout optimization done.

I think it's located at DAG because we lower such constant pools stuff there. If this can be target independent (as Eli commented in previous patch) in DAG, or put it after ISel (I guess you mean that?), it's fine to abandon that.

[shchenz]

In D91053#2912214, @qiucf wrote:

In D91053#2912191, @lkail wrote:

A few months ago, steven shared his patch to us. For me, it should be an optimization of TOC layout, it looks odd to me to get it done at isel phase. I think we should figure out a new approach for this. What do you think @nemanjai @qiucf ?

I tend to not pursue this patch and might have a new one to get TOC layout optimization done.

I think it's located at DAG because we lower such constant pools stuff there. If this can be target independent (as Eli commented in previous patch) in DAG, or put it after ISel (I guess you mean that?), it's fine to abandon that.

I don't think after ISEL is a good idea. After ISel, the constant pool and the code pattern to access the constant pool are both settled down. It does not make sense to me to revert or change them later. It is better to generate it like we expect in the first place.

[steven.zhang]

In D91053#2913869, @shchenz wrote:

In D91053#2912214, @qiucf wrote:

In D91053#2912191, @lkail wrote:

A few months ago, steven shared his patch to us. For me, it should be an optimization of TOC layout, it looks odd to me to get it done at isel phase. I think we should figure out a new approach for this. What do you think @nemanjai @qiucf ?

I tend to not pursue this patch and might have a new one to get TOC layout optimization done.

I think it's located at DAG because we lower such constant pools stuff there. If this can be target independent (as Eli commented in previous patch) in DAG, or put it after ISel (I guess you mean that?), it's fine to abandon that.

I don't think after ISEL is a good idea. After ISel, the constant pool and the code pattern to access the constant pool are both settled down. It does not make sense to me to revert or change them later. It is better to generate it like we expect in the first place.

+1

[stefanp]

I'm going to commandeer this patch and rebase it to see if I can revive it.

[nemanjai]

In D91053#3962199, @stefanp wrote:

I'm going to commandeer this patch and rebase it to see if I can revive it.

@stefanp I think you're working on a re-implementation of this. Since the implementation will likely be fundamentally different, perhaps it would be good to just abandon this patch.

[nemanjai]

In D91053#4068538, @nemanjai wrote:

In D91053#3962199, @stefanp wrote:

I'm going to commandeer this patch and rebase it to see if I can revive it.

@stefanp I think you're working on a re-implementation of this. Since the implementation will likely be fundamentally different, perhaps it would be good to just abandon this patch.

I believe you know more about the planned direction for this patch now. Is it time to abandon this or are you plan to re-work this patch in some way?

[stefanp]

Will post a different solution for this soon.
Abandoning this patch now.

llvm/lib/Target/PowerPC/CMakeLists.txt

 add_llvm_target(PowerPCCodeGen
   GISel/PPCInstructionSelector.cpp
   PPCBoolRetToInt.cpp
   PPCAsmPrinter.cpp
   PPCBranchSelector.cpp
   PPCBranchCoalescing.cpp
   PPCCallingConv.cpp
   PPCCCState.cpp
+  PPCConstantPoolValue.cpp
   PPCCTRLoops.cpp
   PPCHazardRecognizers.cpp
   PPCInstrInfo.cpp
   PPCISelDAGToDAG.cpp
   PPCISelLowering.cpp
   PPCEarlyReturn.cpp
   PPCFastISel.cpp
   PPCFrameLowering.cpp
   PPCLoopInstrFormPrep.cpp
   PPCMCInstLower.cpp
   PPCMachineFunctionInfo.cpp
   PPCMachineScheduler.cpp
   PPCMacroFusion.cpp
   PPCMIPeephole.cpp
   PPCRegisterInfo.cpp
+  PPCSelectionDAGInfo.cpp
   PPCSubtarget.cpp
   PPCTargetMachine.cpp
   PPCTargetObjectFile.cpp
   PPCTargetTransformInfo.cpp
   PPCTOCRegDeps.cpp
   PPCTLSDynamicCall.cpp
   PPCVSXCopy.cpp
   PPCReduceCRLogicals.cpp

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/PPCInstPrinter.h"
 #include "MCTargetDesc/PPCMCExpr.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPC.h"
+#include "PPCConstantPoolValue.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "PPCTargetStreamer.h"
 #include "TargetInfo/PowerPCTargetInfo.h"
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
public:
   explicit PPCLinuxAsmPrinter(TargetMachine &TM,
                               std::unique_ptr<MCStreamer> Streamer)
       : PPCAsmPrinter(TM, std::move(Streamer)) {}
 
   StringRef getPassName() const override {
     return "Linux PPC Assembly Printer";
   }
 
+  void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
   void emitStartOfAsmFile(Module &M) override;
   void emitEndOfAsmFile(Module &) override;
 
   void emitFunctionEntryLabel() override;
 
   void emitFunctionBodyStart() override;
   void emitFunctionBodyEnd() override;
   void emitInstruction(const MachineInstr *MI) override;
case PPC::ADDIStocHA8: {
     assert((MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isBlockAddress()) &&
            "Invalid operand for ADDIStocHA8!");
 
     const MCSymbol *MOSymbol = getMCSymbolForTOCPseudoMO(MO, *this);
 
     const bool GlobalToc =
         MO.isGlobal() && Subtarget->isGVIndirectSymbol(MO.getGlobal());
     if (GlobalToc || MO.isJTI() || MO.isBlockAddress() ||
-        (MO.isCPI() && TM.getCodeModel() == CodeModel::Large))
+        (MO.isCPI() && ((MO.getTargetFlags() & PPCII::MO_GOT_FLAG) ||
+                        TM.getCodeModel() == CodeModel::Large)))
       MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
 
     const MCSymbolRefExpr::VariantKind VK =
         IsAIX ? MCSymbolRefExpr::VK_PPC_U : MCSymbolRefExpr::VK_PPC_TOC_HA;
 
     const MCExpr *Exp =
         MCSymbolRefExpr::create(MOSymbol, VK, OutContext);
 
case PPC::LDtocL: {
 
     LLVM_DEBUG(assert(
         (!MO.isGlobal() || Subtarget->isGVIndirectSymbol(MO.getGlobal())) &&
         "LDtocL used on symbol that could be accessed directly is "
         "invalid. Must match ADDIStocHA8."));
 
     const MCSymbol *MOSymbol = getMCSymbolForTOCPseudoMO(MO, *this);
 
-    if (!MO.isCPI() || TM.getCodeModel() == CodeModel::Large)
+    if (!MO.isCPI() || (MO.getTargetFlags() & PPCII::MO_GOT_FLAG) ||
+        TM.getCodeModel() == CodeModel::Large)
       MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
 
     const MCSymbolRefExpr::VariantKind VK =
         IsAIX ? MCSymbolRefExpr::VK_PPC_L : MCSymbolRefExpr::VK_PPC_TOC_LO;
     const MCExpr *Exp =
         MCSymbolRefExpr::create(MOSymbol, VK, OutContext);
     TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);
for (const auto &TOCMapPair : TOC) {
       else
         OutStreamer->emitSymbolValue(TOCEntryTarget, 4);
     }
   }
 
   PPCAsmPrinter::emitEndOfAsmFile(M);
 }
 
+void PPCLinuxAsmPrinter::emitMachineConstantPoolValue(
+    MachineConstantPoolValue *MCPV) {
+  PPCConstantPoolValue *PCPV = static_cast<PPCConstantPoolValue *>(MCPV);
+  const DataLayout &DL = getDataLayout();
+  for (const auto *C : PCPV->getConstants())
+    emitGlobalConstant(DL, C);
+}
+
 /// EmitFunctionBodyStart - Emit a global entry point prefix for ELFv2.
 void PPCLinuxAsmPrinter::emitFunctionBodyStart() {
   // In the ELFv2 ABI, in functions that use the TOC register, we need to
   // provide two entry points.  The ABI guarantees that when calling the
   // local entry point, r2 is set up by the caller to contain the TOC base
   // for this function, and when calling the global entry point, r12 is set
   // up by the caller to hold the address of the global entry point.  We
   // thus emit a prefix sequence along the following lines:

llvm/lib/Target/PowerPC/PPCConstantPoolValue.h

+//===- PPCConstantPoolValue.h - PPC constantpool value ----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the PowerPC specific constantpool value class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H
+#define LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H
+
+#include "llvm/CodeGen/MachineConstantPool.h"
+
+namespace llvm {
+class ConstantFP;
+class PPCConstantPoolValue : public MachineConstantPoolValue {
+  // Lump all the constants into the same constant pool if they have the
+  // same type.
+  SmallVector<const Constant *, 8> ConstantValues;
+
+public:
+  PPCConstantPoolValue(Type *Ty);
+
+  const SmallVector<const Constant *, 8> &getConstants() const {
+    return ConstantValues;
+  }
+
+  unsigned getSizeInBytes(const DataLayout &DL) const override;
+
+  /// Create a new entry in the constant pool or return an existing one for the
+  /// constant.
+  unsigned getConstantIndex(const Constant *C);
+
+  static PPCConstantPoolValue *Create(Type *Ty);
+
+  int getExistingMachineCPValue(MachineConstantPool *CP,
+                                Align Alignment) override;
+
+  void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
+
+  /// print - Implement operator<<
+  void print(raw_ostream &O) const override;
+};
+
+} // end namespace llvm
+#endif // LLVM_LIB_TARGET_PPC_PPCCONSTANTPOOLVALUE_H

llvm/lib/Target/PowerPC/PPCConstantPoolValue.cpp

+//===- PPCConstantPoolValue.cpp - PPC constantpool value ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the PowerPC specific constantpool value class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCConstantPoolValue.h"
+#include "llvm/ADT/FoldingSet.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+PPCConstantPoolValue::PPCConstantPoolValue(Type *Ty)
+    : MachineConstantPoolValue(Ty) {}
+
+PPCConstantPoolValue *PPCConstantPoolValue::Create(Type *Ty) {
+  return new PPCConstantPoolValue(Ty);
+}
+
+unsigned PPCConstantPoolValue::getSizeInBytes(const DataLayout &DL) const {
+  return DL.getTypeAllocSize(getType()) * ConstantValues.size();
+}
+
+unsigned PPCConstantPoolValue::getConstantIndex(const Constant *C) {
+  for (unsigned I = 0, E = ConstantValues.size(); I != E; ++I)
+    if (ConstantValues[I] == C)
+      return I;
+  ConstantValues.push_back(C);
+  return ConstantValues.size() - 1;
+}
+
+int PPCConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
+                                                    Align Alignment) {
+  const std::vector<MachineConstantPoolEntry> &Constants = CP->getConstants();
+  for (unsigned I = 0, E = Constants.size(); I != E; ++I) {
+    if (Constants[I].isMachineConstantPoolEntry() &&
+        Constants[I].getAlign() >= Alignment) {
+      auto *PCPV =
+          static_cast<PPCConstantPoolValue *>(Constants[I].Val.MachineCPVal);
+      if (PCPV->getType() == getType())
+        return I;
+    }
+  }
+  return -1;
+}
+
+void PPCConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+  ID.AddPointer(getType());
+}
+
+void PPCConstantPoolValue::print(raw_ostream &O) const {
+  O << ConstantValues.size() << " x " << *getType();
+}

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (ReplaceFlags) {
         // is insufficient for the instruction encoding.
         if (Alignment < 4 && (RequiresMod4Offset || (Offset % 4) != 0)) {
           LLVM_DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
           continue;
         }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
+        if (CP->isMachineConstantPoolEntry()) {
+          MachineConstantPoolValue *V = CP->getMachineCPVal();
+          ImmOpnd = CurDAG->getTargetConstantPool(V, MVT::i64, CP->getAlign(),
+                                                  Offset, Flags);
+        } else {
           const Constant *C = CP->getConstVal();
           ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlign(),
                                                   Offset, Flags);
         }
       }
+    }
 
     if (FirstOp == 1) // Store
       (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
                                        Base.getOperand(0), N->getOperand(3));
     else // Load
       (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
                                        N->getOperand(2));
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCISelLowering.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPC.h"
 #include "PPCCCState.h"
 #include "PPCCallingConv.h"
+#include "PPCConstantPoolValue.h"
 #include "PPCFrameLowering.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCPerfectShuffle.h"
 #include "PPCRegisterInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/APFloat.h"

 
 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
 static bool isFloatingPointZero(SDValue Op) {
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
     return CFP->getValueAPF().isZero();
   else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
     // Maybe this has already been legalized into the constant pool?
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
+      if (!CP->isMachineConstantPoolEntry())
         if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
           return CFP->getValueAPF().isZero();
   }
   return false;
 }
 
 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode.  Return
 /// true if Op is undef or if it matches the specified value.
 static bool isConstantOrUndef(int Op, int Val) {
   return Op < 0 || Op == Val;
return DAG.getMemIntrinsicNode(
       MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
       MachineMemOperand::MOLoad);
 }
 
 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
+  if (CP->isMachineConstantPoolEntry()) {
+    unsigned TargetFlags = isAccessedAsGotIndirect(Op) ? PPCII::MO_GOT_FLAG : 0;
+    SDValue GA = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
+                                           CP->getAlign(), 0, TargetFlags);
+    setUsesTOCBasePtr(DAG);
+    return getTOCEntry(DAG, SDLoc(CP), GA);
+  }
+
   const Constant *C = CP->getConstVal();
 
   // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
     if (Subtarget.isUsingPCRelativeCalls()) {
       SDLoc DL(CP);
       EVT Ty = getPointerTy(DAG.getDataLayout());
bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
   // indirectly by loading their address from .toc/.got.
   if (CModel == CodeModel::Small || CModel == CodeModel::Large)
     return true;
 
   // JumpTable and BlockAddress are accessed as got-indirect.
   if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA))
     return true;
 
+  // Constant is accessed as got-indirect if it is lumped.
+  if (ConstantPoolSDNode *CPN = dyn_cast<ConstantPoolSDNode>(GA))
+    if (CPN->isMachineConstantPoolEntry())
+      return true;
+
   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA))
     return Subtarget.isGVIndirectSymbol(G->getGlobal());
 
   return false;
 }
 
 bool
 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {

llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h

+//===-- PPCSelectionDAGInfo.h - PPC SelectionDAG Info -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the PPC subclass for SelectionDAGTargetInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class PPCSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+  explicit PPCSelectionDAGInfo() = default;
+
+  SDValue EmitTargetCodeForConstantPool(SelectionDAG &DAG, const Constant *C,
+                                        EVT VT, Align Alignment,
+                                        Align &NewAlign, int Offset,
+                                        bool isTarget,
+                                        unsigned TargetFlags) const override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_PPC_PPCSELECTIONDAGINFO_H

llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp

+//===-- PPCSelectionDAGInfo.cpp - PPC SelectionDAG Info -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the PPCSelectionDAGInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCSelectionDAGInfo.h"
+#include "PPCConstantPoolValue.h"
+#include "PPCSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/Support/CommandLine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ppc-selectiondag-info"
+
+static cl::opt<bool>
+    ConstantLump("ppc-const-lump",
+                 cl::desc("enable/disable constant lump on ppc"), cl::Hidden,
+                 cl::init(true));
+STATISTIC(NumConstantLump, "Number of constant lumped");
+
+SDValue PPCSelectionDAGInfo::EmitTargetCodeForConstantPool(
+    SelectionDAG &DAG, const Constant *C, EVT VT, Align Alignment,
+    Align &NewAlign, int Offset, bool isTarget, unsigned TargetFlags) const {
+  const PPCSubtarget &Subtarget =
+      DAG.getMachineFunction().getSubtarget<PPCSubtarget>();
+
+  // Lump the constant pool for each function into ONE pic object, and reference
+  // pieces of it as offsets from the start. Only do it for 64bit ELF ABI. And
+  // we won't get benefit if PCREL is enabled.
+  if (!Subtarget.is64BitELFABI() || Subtarget.isUsingPCRelativeCalls() ||
+      !ConstantLump)
+    return SDValue();
+
+  // The liveness of MachineConstantPoolValue is per function. We need to query
+  // the right constant pool value from MachineConstantPool.
+  MachineConstantPool *MCP = DAG.getMachineFunction().getConstantPool();
+  unsigned CPIdx = MCP->getConstantPoolIndex(
+      PPCConstantPoolValue::Create(C->getType()),
+      DAG.getDataLayout().getPrefTypeAlign(C->getType()));
+  PPCConstantPoolValue *GAVal = static_cast<PPCConstantPoolValue *>(
+      MCP->getConstants()[CPIdx].Val.MachineCPVal);
+
+  // Lump each constant into one constant pool if they have the same type.
+  SDValue GA =
+      DAG.getConstantPool(GAVal, VT, Alignment, Offset, isTarget, TargetFlags);
+  // TODO - Don't assume that GA must be ConstantPoolSDNode.
+  NewAlign = std::max(Alignment, cast<ConstantPoolSDNode>(GA)->getAlign());
+
+  // Get the offset from the constant pool and give up if it is not 16-bit as
+  // we won't have benefit if the offset doesn't fit the D-Form load imm field.
+  unsigned OffsetInsideCP = GAVal->getConstantIndex(C) * NewAlign.value();
+  if (!isInt<16>(OffsetInsideCP))
+    return SDValue();
+
+  if (OffsetInsideCP)
+    ++NumConstantLump;
+
+  // The address of the constant is the sum of constant pool and the offset
+  // inside it.
+  SDLoc Loc(GA);
+  return DAG.getNode(
+      ISD::ADD, Loc, GA->getValueType(0), GA,
+      DAG.getConstant(OffsetInsideCP, Loc,
+                      Subtarget.isPPC64() ? MVT::i64 : MVT::i32));
+}

llvm/lib/Target/PowerPC/PPCSubtarget.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
 
 #include "PPCFrameLowering.h"
 #include "PPCISelLowering.h"
 #include "PPCInstrInfo.h"
+#include "PPCSelectionDAGInfo.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/MC/MCInstrItineraries.h"
protected:
   bool PredictableSelectIsExpensive;
 
   POPCNTDKind HasPOPCNTD;
 
   const PPCTargetMachine &TM;
   PPCFrameLowering FrameLowering;
   PPCInstrInfo InstrInfo;
   PPCTargetLowering TLInfo;
-  SelectionDAGTargetInfo TSInfo;
+  PPCSelectionDAGInfo TSInfo;
 
   /// GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
 
 public:

llvm/test/CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll

-; RUN: llc -verify-machineinstrs -code-model=small < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-const-lump=false -code-model=small < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; This test check if the TOC entry symbol name won't clash with global .LC0
 ; and .LC2 symbols defined in the module.
 
 @.LC0 = internal global [5 x i8] c".LC0\00"
 @.LC2 = internal global [5 x i8] c".LC2\00"

llvm/test/CodeGen/PowerPC/branch_coalesce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
 
 ; Function Attrs: nounwind
 define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 ; CHECK-LABEL: testBranchCoal:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplwi 6, 0
 ; CHECK-NEXT:    beq 0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    xxlxor 2, 2, 2
-; CHECK-NEXT:    lfd 1, .LCPI0_0@toc@l(3)
-; CHECK-NEXT:    lfd 3, .LCPI0_1@toc@l(4)
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    lfd 1, 8(3)
+; CHECK-NEXT:    lfdx 3, 0, 3
 ; CHECK-NEXT:  .LBB0_2: # %entry
 ; CHECK-NEXT:    xsadddp 0, 1, 2
 ; CHECK-NEXT:    xsadddp 1, 0, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
 ; CHECK-NOCOALESCE:       # %bb.0: # %entry
+; CHECK-NOCOALESCE-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NOCOALESCE-NEXT:    cmplwi 6, 0
+; CHECK-NOCOALESCE-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_5
 ; CHECK-NOCOALESCE-NEXT:  # %bb.1: # %entry
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_6
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_2: # %entry
 ; CHECK-NOCOALESCE-NEXT:    beq 0, .LBB0_4
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_3: # %entry
-; CHECK-NOCOALESCE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-NOCOALESCE-NEXT:    lfd 3, .LCPI0_1@toc@l(3)
+; CHECK-NOCOALESCE-NEXT:    lfdx 3, 0, 3
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_4: # %entry
 ; CHECK-NOCOALESCE-NEXT:    xsadddp 0, 1, 2
 ; CHECK-NOCOALESCE-NEXT:    xsadddp 1, 0, 3
 ; CHECK-NOCOALESCE-NEXT:    blr
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_5: # %entry
-; CHECK-NOCOALESCE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NOCOALESCE-NEXT:    lfd 1, .LCPI0_0@toc@l(3)
+; CHECK-NOCOALESCE-NEXT:    lfd 1, 8(3)
 ; CHECK-NOCOALESCE-NEXT:    beq 0, .LBB0_2
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_6: # %entry
 ; CHECK-NOCOALESCE-NEXT:    xxlxor 2, 2, 2
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_3
 ; CHECK-NOCOALESCE-NEXT:    b .LBB0_4
 
   entry:
 

llvm/test/CodeGen/PowerPC/build-vector-allones.ll

 ; P9LE-NEXT:    blr
 entry:
   ret <1 x i128> <i128 -1>
 }
 
 define <2 x i64> @One2i64() {
 ; P7BE-LABEL: One2i64:
 ; P7BE:       # %bb.0: # %entry
-; P7BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; P7BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; P7BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; P7BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P7BE-NEXT:    lxvd2x vs34, 0, r3
 ; P7BE-NEXT:    blr
 ;
 ; P8LE-LABEL: One2i64:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xxleqv vs34, vs34, vs34
 ; P8LE-NEXT:    blr
 ;

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

entry:
   %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
   %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
   ret <4 x i32> %vecinit3
 }
 
 define <4 x i32> @fromDiffConstsi() {
 ; P9BE-LABEL: fromDiffConstsi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; P9BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC0@toc@ha
+; P9LE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; P8BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC0@toc@ha
+; P8LE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
 }
 
 define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsAi:
entry:
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
-; P9BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC1@toc@ha
+; P9BE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; P8BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
-; P8BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; P8BE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDi:
 ; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; P8LE-NEXT:    addi r3, r4, .LCPI7_0@toc@l
-; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lvx v2, 0, r4
 ; P8LE-NEXT:    vperm v2, v3, v3, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
   %1 = load i32, i32* %arrayidx1, align 4

 
 define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    addi r3, r3, -12
 ; P9BE-NEXT:    lxvx v2, 0, r3
-; P9BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC2@toc@ha
+; P9BE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    addi r3, r3, -12
 ; P9LE-NEXT:    lxvx v2, 0, r3
-; P9LE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC1@toc@ha
+; P9LE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; P9LE-NEXT:    lxvx v3, 0, r3
 ; P9LE-NEXT:    vperm v2, v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDi:
 ; P8BE:       # %bb.0: # %entry
+; P8BE-NEXT:    addis r5, r2, .LC2@toc@ha
 ; P8BE-NEXT:    sldi r4, r4, 2
-; P8BE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
+; P8BE-NEXT:    ld r5, .LC2@toc@l(r5)
 ; P8BE-NEXT:    add r3, r3, r4
-; P8BE-NEXT:    addi r4, r5, .LCPI9_0@toc@l
 ; P8BE-NEXT:    addi r3, r3, -12
-; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
+; P8BE-NEXT:    lxvw4x v3, 0, r5
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDi:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
-; P8LE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
+; P8LE-NEXT:    addis r5, r2, .LC2@toc@ha
 ; P8LE-NEXT:    add r3, r3, r4
 ; P8LE-NEXT:    addi r3, r3, -12
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addi r3, r5, .LCPI9_0@toc@l
-; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    ld r3, .LC2@toc@l(r5)
 ; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lvx v3, 0, r3
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1
entry:
   %conv5 = fptosi float %d to i32
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffConstsConvftoi() {
 ; P9BE-LABEL: fromDiffConstsConvftoi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC3@toc@ha
+; P9BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvftoi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC2@toc@ha
+; P9LE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvftoi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC3@toc@ha
+; P8BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvftoi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC3@toc@ha
+; P8LE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
 }
 
 define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsAConvftoi:
entry:
   %2 = fptosi <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
-; P9BE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC4@toc@ha
+; P9BE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    xvcvspsxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxv v2, 0(r3)
-; P9LE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC3@toc@ha
+; P9LE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; P9LE-NEXT:    lxvx v3, 0, r3
 ; P9LE-NEXT:    vperm v2, v2, v2, v3
 ; P9LE-NEXT:    xvcvspsxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
+; P8BE-NEXT:    addis r4, r2, .LC4@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
-; P8BE-NEXT:    addi r4, r4, .LCPI18_0@toc@l
+; P8BE-NEXT:    ld r4, .LC4@toc@l(r4)
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspsxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
 ; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addis r4, r2, .LC4@toc@ha
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
-; P8LE-NEXT:    addi r3, r4, .LCPI18_0@toc@l
-; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    ld r4, .LC4@toc@l(r4)
 ; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lvx v2, 0, r4
 ; P8LE-NEXT:    vperm v2, v3, v3, v2
 ; P8LE-NEXT:    xvcvspsxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
   %0 = load float, float* %arrayidx, align 4
   %conv = fptosi float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
entry:
   %conv5 = fptosi double %d to i32
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffConstsConvdtoi() {
 ; P9BE-LABEL: fromDiffConstsConvdtoi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI25_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC5@toc@ha
+; P9BE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvdtoi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI25_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC4@toc@ha
+; P9LE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvdtoi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI25_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC5@toc@ha
+; P8BE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvdtoi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI25_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC5@toc@ha
+; P8LE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
 }
 
 define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsAConvdtoi:
entry:
   %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
   %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
   ret <4 x i32> %vecinit3
 }
 
 define <4 x i32> @fromDiffConstsui() {
 ; P9BE-LABEL: fromDiffConstsui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI37_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI37_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC6@toc@ha
+; P9BE-NEXT:    ld r3, .LC6@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI37_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI37_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC5@toc@ha
+; P9LE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI37_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI37_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC6@toc@ha
+; P8BE-NEXT:    ld r3, .LC6@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI37_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI37_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC6@toc@ha
+; P8LE-NEXT:    ld r3, .LC6@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
 }
 
 define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsAui:
entry:
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
-; P9BE-NEXT:    addis r3, r2, .LCPI39_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI39_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC7@toc@ha
+; P9BE-NEXT:    ld r3, .LC7@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r4, r2, .LCPI39_0@toc@ha
+; P8BE-NEXT:    addis r4, r2, .LC7@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
-; P8BE-NEXT:    addi r4, r4, .LCPI39_0@toc@l
+; P8BE-NEXT:    ld r4, .LC7@toc@l(r4)
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDui:
 ; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addis r4, r2, .LC7@toc@ha
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addis r4, r2, .LCPI39_0@toc@ha
-; P8LE-NEXT:    addi r3, r4, .LCPI39_0@toc@l
-; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    ld r4, .LC7@toc@l(r4)
 ; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lvx v2, 0, r4
 ; P8LE-NEXT:    vperm v2, v3, v3, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
   %1 = load i32, i32* %arrayidx1, align 4

 
 define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) {
 ; P9BE-LABEL: fromDiffMemVarDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    addi r3, r3, -12
 ; P9BE-NEXT:    lxvx v2, 0, r3
-; P9BE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC8@toc@ha
+; P9BE-NEXT:    ld r3, .LC8@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    addi r3, r3, -12
 ; P9LE-NEXT:    lxvx v2, 0, r3
-; P9LE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC6@toc@ha
+; P9LE-NEXT:    ld r3, .LC6@toc@l(r3)
 ; P9LE-NEXT:    lxvx v3, 0, r3
 ; P9LE-NEXT:    vperm v2, v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDui:
 ; P8BE:       # %bb.0: # %entry
+; P8BE-NEXT:    addis r5, r2, .LC8@toc@ha
 ; P8BE-NEXT:    sldi r4, r4, 2
-; P8BE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
+; P8BE-NEXT:    ld r5, .LC8@toc@l(r5)
 ; P8BE-NEXT:    add r3, r3, r4
-; P8BE-NEXT:    addi r4, r5, .LCPI41_0@toc@l
 ; P8BE-NEXT:    addi r3, r3, -12
-; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
+; P8BE-NEXT:    lxvw4x v3, 0, r5
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    sldi r4, r4, 2
-; P8LE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
+; P8LE-NEXT:    addis r5, r2, .LC8@toc@ha
 ; P8LE-NEXT:    add r3, r3, r4
 ; P8LE-NEXT:    addi r3, r3, -12
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addi r3, r5, .LCPI41_0@toc@l
-; P8LE-NEXT:    lvx v3, 0, r3
+; P8LE-NEXT:    ld r3, .LC8@toc@l(r5)
 ; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    lvx v3, 0, r3
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1
entry:
   %conv5 = fptoui float %d to i32
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffConstsConvftoui() {
 ; P9BE-LABEL: fromDiffConstsConvftoui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI48_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI48_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC9@toc@ha
+; P9BE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvftoui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI48_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI48_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC7@toc@ha
+; P9LE-NEXT:    ld r3, .LC7@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvftoui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI48_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI48_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC9@toc@ha
+; P8BE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvftoui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI48_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI48_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC9@toc@ha
+; P8LE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
 }
 
 define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsAConvftoui:
entry:
   %2 = fptoui <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
-; P9BE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC10@toc@ha
+; P9BE-NEXT:    ld r3, .LC10@toc@l(r3)
 ; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    vperm v2, v2, v2, v3
 ; P9BE-NEXT:    xvcvspuxws v2, v2
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxv v2, 0(r3)
-; P9LE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC8@toc@ha
+; P9LE-NEXT:    ld r3, .LC8@toc@l(r3)
 ; P9LE-NEXT:    lxvx v3, 0, r3
 ; P9LE-NEXT:    vperm v2, v2, v2, v3
 ; P9LE-NEXT:    xvcvspuxws v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
+; P8BE-NEXT:    addis r4, r2, .LC10@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
-; P8BE-NEXT:    addi r4, r4, .LCPI50_0@toc@l
+; P8BE-NEXT:    ld r4, .LC10@toc@l(r4)
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspuxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
 ; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addis r4, r2, .LC10@toc@ha
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
-; P8LE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
-; P8LE-NEXT:    addi r3, r4, .LCPI50_0@toc@l
-; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    ld r4, .LC10@toc@l(r4)
 ; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lvx v2, 0, r4
 ; P8LE-NEXT:    vperm v2, v3, v3, v2
 ; P8LE-NEXT:    xvcvspuxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
   %0 = load float, float* %arrayidx, align 4
   %conv = fptoui float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
entry:
   %conv5 = fptoui double %d to i32
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @fromDiffConstsConvdtoui() {
 ; P9BE-LABEL: fromDiffConstsConvdtoui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI57_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI57_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC11@toc@ha
+; P9BE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvdtoui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI57_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI57_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC9@toc@ha
+; P9LE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvdtoui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI57_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI57_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC11@toc@ha
+; P8BE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvdtoui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI57_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI57_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC11@toc@ha
+; P8LE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; P8LE-NEXT:    lvx v2, 0, r3
 ; P8LE-NEXT:    blr
 entry:
   ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
 }
 
 define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsAConvdtoui:

 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> zeroinitializer
 }
 
 define <2 x i64> @spltConst1ll() {
 ; P9BE-LABEL: spltConst1ll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC12@toc@ha
+; P9BE-NEXT:    ld r3, .LC12@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst1ll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC10@toc@ha
+; P9LE-NEXT:    ld r3, .LC10@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst1ll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC12@toc@ha
+; P8BE-NEXT:    ld r3, .LC12@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst1ll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI65_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC12@toc@ha
+; P8LE-NEXT:    ld r3, .LC12@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
 define <2 x i64> @spltConst16kll() {
 ; P9BE-LABEL: spltConst16kll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI66_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC13@toc@ha
+; P9BE-NEXT:    ld r3, .LC13@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst16kll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI66_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC11@toc@ha
+; P9LE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst16kll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI66_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC13@toc@ha
+; P8BE-NEXT:    ld r3, .LC13@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst16kll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI66_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI66_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC13@toc@ha
+; P8LE-NEXT:    ld r3, .LC13@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 32767, i64 32767>
 }
 
 define <2 x i64> @spltConst32kll() {
 ; P9BE-LABEL: spltConst32kll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI67_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC14@toc@ha
+; P9BE-NEXT:    ld r3, .LC14@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst32kll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI67_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC12@toc@ha
+; P9LE-NEXT:    ld r3, .LC12@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst32kll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI67_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC14@toc@ha
+; P8BE-NEXT:    ld r3, .LC14@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst32kll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI67_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI67_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC14@toc@ha
+; P8LE-NEXT:    ld r3, .LC14@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 65535, i64 65535>
 }
 
 define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
entry:
   %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
   ret <2 x i64> %vecinit1
 }
 
 define <2 x i64> @fromDiffConstsll() {
 ; P9BE-LABEL: fromDiffConstsll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI69_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI69_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC15@toc@ha
+; P9BE-NEXT:    ld r3, .LC15@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI69_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI69_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC13@toc@ha
+; P9LE-NEXT:    ld r3, .LC13@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI69_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI69_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC15@toc@ha
+; P8BE-NEXT:    ld r3, .LC15@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI69_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI69_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC15@toc@ha
+; P8LE-NEXT:    ld r3, .LC15@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 242, i64 -113>
 }
 
 define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) {
entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltCnstConvftoll() {
 ; P9BE-LABEL: spltCnstConvftoll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI78_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC16@toc@ha
+; P9BE-NEXT:    ld r3, .LC16@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltCnstConvftoll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI78_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC14@toc@ha
+; P9LE-NEXT:    ld r3, .LC14@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltCnstConvftoll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI78_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC16@toc@ha
+; P8BE-NEXT:    ld r3, .LC16@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvftoll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI78_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI78_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC16@toc@ha
+; P8LE-NEXT:    ld r3, .LC16@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
entry:
   %conv1 = fptosi float %b to i64
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @fromDiffConstsConvftoll() {
 ; P9BE-LABEL: fromDiffConstsConvftoll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI80_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI80_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC17@toc@ha
+; P9BE-NEXT:    ld r3, .LC17@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvftoll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI80_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI80_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC15@toc@ha
+; P9LE-NEXT:    ld r3, .LC15@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvftoll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI80_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI80_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC17@toc@ha
+; P8BE-NEXT:    ld r3, .LC17@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvftoll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI80_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI80_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC17@toc@ha
+; P8LE-NEXT:    ld r3, .LC17@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 24, i64 234>
 }
 
 define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) {
entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltCnstConvdtoll() {
 ; P9BE-LABEL: spltCnstConvdtoll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI87_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC18@toc@ha
+; P9BE-NEXT:    ld r3, .LC18@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltCnstConvdtoll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI87_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC16@toc@ha
+; P9LE-NEXT:    ld r3, .LC16@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltCnstConvdtoll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI87_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC18@toc@ha
+; P8BE-NEXT:    ld r3, .LC18@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvdtoll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI87_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI87_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC18@toc@ha
+; P8LE-NEXT:    ld r3, .LC18@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
entry:
   %conv1 = fptosi double %b to i64
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @fromDiffConstsConvdtoll() {
 ; P9BE-LABEL: fromDiffConstsConvdtoll:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI89_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI89_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC19@toc@ha
+; P9BE-NEXT:    ld r3, .LC19@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvdtoll:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI89_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI89_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC17@toc@ha
+; P9LE-NEXT:    ld r3, .LC17@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvdtoll:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI89_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI89_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC19@toc@ha
+; P8BE-NEXT:    ld r3, .LC19@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvdtoll:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI89_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI89_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC19@toc@ha
+; P8LE-NEXT:    ld r3, .LC19@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 24, i64 234>
 }
 
 define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) {

 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> zeroinitializer
 }
 
 define <2 x i64> @spltConst1ull() {
 ; P9BE-LABEL: spltConst1ull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI97_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC20@toc@ha
+; P9BE-NEXT:    ld r3, .LC20@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst1ull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI97_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC18@toc@ha
+; P9LE-NEXT:    ld r3, .LC18@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst1ull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI97_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC20@toc@ha
+; P8BE-NEXT:    ld r3, .LC20@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst1ull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI97_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI97_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC20@toc@ha
+; P8LE-NEXT:    ld r3, .LC20@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
 define <2 x i64> @spltConst16kull() {
 ; P9BE-LABEL: spltConst16kull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI98_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC21@toc@ha
+; P9BE-NEXT:    ld r3, .LC21@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst16kull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI98_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC19@toc@ha
+; P9LE-NEXT:    ld r3, .LC19@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst16kull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI98_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC21@toc@ha
+; P8BE-NEXT:    ld r3, .LC21@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst16kull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI98_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI98_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC21@toc@ha
+; P8LE-NEXT:    ld r3, .LC21@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 32767, i64 32767>
 }
 
 define <2 x i64> @spltConst32kull() {
 ; P9BE-LABEL: spltConst32kull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI99_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC22@toc@ha
+; P9BE-NEXT:    ld r3, .LC22@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltConst32kull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI99_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC20@toc@ha
+; P9LE-NEXT:    ld r3, .LC20@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltConst32kull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI99_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC22@toc@ha
+; P8BE-NEXT:    ld r3, .LC22@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltConst32kull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI99_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI99_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC22@toc@ha
+; P8LE-NEXT:    ld r3, .LC22@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 65535, i64 65535>
 }
 
 define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
entry:
   %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
   ret <2 x i64> %vecinit1
 }
 
 define <2 x i64> @fromDiffConstsull() {
 ; P9BE-LABEL: fromDiffConstsull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI101_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI101_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC23@toc@ha
+; P9BE-NEXT:    ld r3, .LC23@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI101_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI101_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC21@toc@ha
+; P9LE-NEXT:    ld r3, .LC21@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI101_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI101_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC23@toc@ha
+; P8BE-NEXT:    ld r3, .LC23@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI101_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI101_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC23@toc@ha
+; P8LE-NEXT:    ld r3, .LC23@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 242, i64 -113>
 }
 
 define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) {
entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltCnstConvftoull() {
 ; P9BE-LABEL: spltCnstConvftoull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI110_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC24@toc@ha
+; P9BE-NEXT:    ld r3, .LC24@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltCnstConvftoull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI110_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC22@toc@ha
+; P9LE-NEXT:    ld r3, .LC22@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltCnstConvftoull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI110_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC24@toc@ha
+; P8BE-NEXT:    ld r3, .LC24@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvftoull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI110_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI110_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC24@toc@ha
+; P8LE-NEXT:    ld r3, .LC24@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
entry:
   %conv1 = fptoui float %b to i64
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @fromDiffConstsConvftoull() {
 ; P9BE-LABEL: fromDiffConstsConvftoull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI112_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI112_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC25@toc@ha
+; P9BE-NEXT:    ld r3, .LC25@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvftoull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI112_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI112_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC23@toc@ha
+; P9LE-NEXT:    ld r3, .LC23@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvftoull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI112_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI112_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC25@toc@ha
+; P8BE-NEXT:    ld r3, .LC25@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvftoull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI112_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI112_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC25@toc@ha
+; P8LE-NEXT:    ld r3, .LC25@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 24, i64 234>
 }
 
 define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) {
entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltCnstConvdtoull() {
 ; P9BE-LABEL: spltCnstConvdtoull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI119_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC26@toc@ha
+; P9BE-NEXT:    ld r3, .LC26@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltCnstConvdtoull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI119_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC24@toc@ha
+; P9LE-NEXT:    ld r3, .LC24@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltCnstConvdtoull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI119_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC26@toc@ha
+; P8BE-NEXT:    ld r3, .LC26@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltCnstConvdtoull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI119_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI119_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC26@toc@ha
+; P8LE-NEXT:    ld r3, .LC26@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 4, i64 4>
 }
 
 define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
entry:
   %conv1 = fptoui double %b to i64
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @fromDiffConstsConvdtoull() {
 ; P9BE-LABEL: fromDiffConstsConvdtoull:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    addis r3, r2, .LCPI121_0@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI121_0@toc@l
+; P9BE-NEXT:    addis r3, r2, .LC27@toc@ha
+; P9BE-NEXT:    ld r3, .LC27@toc@l(r3)
 ; P9BE-NEXT:    lxvx v2, 0, r3
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffConstsConvdtoull:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    addis r3, r2, .LCPI121_0@toc@ha
-; P9LE-NEXT:    addi r3, r3, .LCPI121_0@toc@l
+; P9LE-NEXT:    addis r3, r2, .LC25@toc@ha
+; P9LE-NEXT:    ld r3, .LC25@toc@l(r3)
 ; P9LE-NEXT:    lxvx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffConstsConvdtoull:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    addis r3, r2, .LCPI121_0@toc@ha
-; P8BE-NEXT:    addi r3, r3, .LCPI121_0@toc@l
+; P8BE-NEXT:    addis r3, r2, .LC27@toc@ha
+; P8BE-NEXT:    ld r3, .LC27@toc@l(r3)
 ; P8BE-NEXT:    lxvd2x v2, 0, r3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffConstsConvdtoull:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI121_0@toc@ha
-; P8LE-NEXT:    addi r3, r3, .LCPI121_0@toc@l
+; P8LE-NEXT:    addis r3, r2, .LC27@toc@ha
+; P8LE-NEXT:    ld r3, .LC27@toc@l(r3)
 ; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    blr
 entry:
   ret <2 x i64> <i64 24, i64 234>
 }
 
 define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) {

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ;
 ; CHECK-P9-LABEL: testmrghb2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrghb2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 8, i32 25, i32 9, i32 26, i32 10, i32 27, i32 11, i32 28, i32 12, i32 29, i32 13, i32 30, i32 14, i32 31, i32 15>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrghh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {

 ;
 ; CHECK-P9-LABEL: testmrghh2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrghh2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 8, i32 9, i32 26, i32 27, i32 10, i32 11, i32 28, i32 29, i32 12, i32 13, i32 30, i32 31, i32 14, i32 15>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {

 ;
 ; CHECK-P9-LABEL: testmrglb2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglb2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 0, i32 17, i32 1, i32 18, i32 2, i32 19, i32 3, i32 20, i32 4, i32 21, i32 5, i32 22, i32 6, i32 23, i32 7>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {

 ;
 ; CHECK-P9-LABEL: testmrglh2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglh2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 0, i32 1, i32 18, i32 19, i32 2, i32 3, i32 20, i32 21, i32 4, i32 5, i32 22, i32 23, i32 6, i32 7>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrghw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {

 ;
 ; CHECK-P9-LABEL: testmrghw2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrghw2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {

 ;
 ; CHECK-P9-LABEL: testmrglw2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglw2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI11_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI11_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC5@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC5@toc@l(r3)
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 4, i32 5, i32 6, i32 7>
   ret <16 x i8> %shuffle
 }
 

 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglb3:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
+; CHECK-NOVSX-NEXT:    addis r4, r2, .LC6@toc@ha
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
-; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI12_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI12_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r4
+; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
+; CHECK-NOVSX-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
+; CHECK-NOVSX-NEXT:    lvx v3, 0, r4
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %0 = load <8 x i8>, <8 x i8>* %a, align 8
   %1 = zext <8 x i8> %0 to <8 x i16>
   ret <8 x i16> %1
 }

 ;
 ; CHECK-P9-LABEL: no_crash_bitcast:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: no_crash_bitcast:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI14_0@toc@ha
+; CHECK-NOVSX-NEXT:    addis r4, r2, .LC7@toc@ha
 ; CHECK-NOVSX-NEXT:    stw r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
-; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI14_0@toc@l
+; CHECK-NOVSX-NEXT:    ld r4, .LC7@toc@l(r4)
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %cast = bitcast i32 %a to <4 x i8>
   %ret = shufflevector <4 x i8> %cast, <4 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %ret
 }
 
 define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: replace_undefs_in_splat:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: replace_undefs_in_splat:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI15_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-NOVSX-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-NOVSX-NEXT:    addis r4, r2, .LC9@toc@ha
+; CHECK-NOVSX-NEXT:    ld r3, .LC8@toc@l(r3)
+; CHECK-NOVSX-NEXT:    ld r4, .LC9@toc@l(r4)
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addi r3, r4, .LCPI15_1@toc@l
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
+; CHECK-NOVSX-NEXT:    lvx v4, 0, r4
 ; CHECK-NOVSX-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x i32> %vecins1
 }
 
 define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI16_0@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC1@toc@ha
 ; CHECK-P8-NEXT:    sldi r4, r4, 2
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI16_0@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-P8-NEXT:    lxsiwzx v2, r3, r4
 ; CHECK-P8-NEXT:    lvx v3, 0, r5
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    sldi r4, r4, 2
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P9-NEXT:    lxsiwzx v2, r3, r4
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    sldi r4, r4, 2
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2

 ;
 ; CHECK-P9-LABEL: testSplat8:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxvdsx v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testSplat8:
 ; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    addis r4, r2, .LC10@toc@ha
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
-; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI19_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI19_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
+; CHECK-NOVSX-NEXT:    ld r4, .LC10@toc@l(r4)
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
+; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %0 = load <8 x i8>, <8 x i8>* %ptr, align 8
   %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %1 = bitcast <16 x i8> %vecinit30 to <2 x i64>
   ret <2 x i64> %1
 }
 
 declare double @dummy() local_unnamed_addr
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 ; Infinite loop identified in D62963.
 define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {
 ; CHECK-LABEL: fneg_fdiv_splat:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; CHECK-NEXT:    xxspltd 0, 1, 0
-; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NEXT:    xvredp 2, 0
+; CHECK-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-NEXT:    xxswapd 1, 1
 ; CHECK-NEXT:    xxlor 3, 1, 1
 ; CHECK-NEXT:    xvnmsubadp 3, 0, 2
 ; CHECK-NEXT:    xvmaddadp 2, 2, 3
 ; CHECK-NEXT:    xvnmsubadp 1, 0, 2
 ; CHECK-NEXT:    xvnmaddadp 2, 2, 1
 ; CHECK-NEXT:    xvmuldp 34, 34, 2
 ; CHECK-NEXT:    xvmuldp 35, 35, 2
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
   %div = fdiv reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
   %sub = fsub reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/constant-pool.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
 ; RUN:   -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
+; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P8
+
+; CHECK-P9: .section  .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        2
+; CHECK-P9-LABEL: .LCPI0_0:
+; CHECK-P9: .long   0x007fffe1
 
  define float @FloatConstantPool() {
 ; CHECK-LABEL: FloatConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfs f1, .LCPI0_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: FloatConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f1, 0(r3)
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: FloatConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-P8-NEXT:    lfsx f1, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret float 0x380FFFF840000000
 }
 
+; CHECK-P9: .section  .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI1_0:
+; CHECK-P9: .quad   0x000ffffe2e8159d0
+
  define double @DoubleConstantPool() {
 ; CHECK-LABEL: DoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfd f1, .LCPI1_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: DoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI1_0@toc@l(r3)
+; CHECK-P9-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC1@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r3)
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: DoubleConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC1@toc@l(r3)
+; CHECK-P8-NEXT:    lfdx f1, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret double 2.225070e-308
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI2_0:
+; CHECK-P9: .quad   0x800d16974fd9d27b
+; CHECK-P9: .quad   0x03600000dba876cc
+
  define ppc_fp128 @LongDoubleConstantPool() {
 ; CHECK-LABEL: LongDoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfd f1, .LCPI2_0@PCREL(0), 1
 ; CHECK-NEXT:    plfd f2, .LCPI2_1@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: LongDoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI2_0@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
-; CHECK-P9-NEXT:    lfd f2, .LCPI2_1@toc@l(r3)
+; CHECK-P9-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC2@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 8(r3)
+; CHECK-P9-NEXT:    lfd f2, 0(r3)
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: LongDoubleConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC2@toc@l(r3)
+; CHECK-P8-NEXT:    lfd f1, 8(r3)
+; CHECK-P8-NEXT:    lfdx f2, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI3_0:
+; CHECK-P9: .quad   0x3c00ffffc5d02b3a
+; CHECK-P9: .quad   0x0000000000000000
+
  define fp128 @__Float128ConstantPool() {
 ; CHECK-LABEL: __Float128ConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI3_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: __Float128ConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: __Float128ConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lis r3, 15360
+; CHECK-P8-NEXT:    li r4, 0
+; CHECK-P8-NEXT:    ori r3, r3, 65535
+; CHECK-P8-NEXT:    sldi r3, r3, 32
+; CHECK-P8-NEXT:    oris r3, r3, 50640
+; CHECK-P8-NEXT:    ori r3, r3, 11066
+; CHECK-P8-NEXT:    blr
 entry:
   ret fp128 0xL00000000000000003C00FFFFC5D02B3A
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI4_0:
+; CHECK-P9-NEXT: .byte   128
+; CHECK-P9-NEXT: .byte   129
+; CHECK-P9-NEXT: .byte   130
+; CHECK-P9-NEXT: .byte   131
+; CHECK-P9-NEXT: .byte   132
+; CHECK-P9-NEXT: .byte   133
+; CHECK-P9-NEXT: .byte   134
+; CHECK-P9-NEXT: .byte   135
+; CHECK-P9-NEXT: .byte   136
+; CHECK-P9-NEXT: .byte   137
+; CHECK-P9-NEXT: .byte   138
+; CHECK-P9-NEXT: .byte   139
+; CHECK-P9-NEXT: .byte   140
+; CHECK-P9-NEXT: .byte   141
+; CHECK-P9-NEXT: .byte   142
+; CHECK-P9-NEXT: .byte   143
  define <16 x i8> @VectorCharConstantPool() {
 ; CHECK-LABEL: VectorCharConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI4_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorCharConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorCharConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC3@toc@l(r3)
+; CHECK-P8-NEXT:    lxvw4x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI5_0:
+; CHECK-P9-NEXT: .short  32768
+; CHECK-P9-NEXT: .short  32769
+; CHECK-P9-NEXT: .short  32770
+; CHECK-P9-NEXT: .short  32771
+; CHECK-P9-NEXT: .short  32772
+; CHECK-P9-NEXT: .short  32773
+; CHECK-P9-NEXT: .short  32774
+; CHECK-P9-NEXT: .short  32775
  define <8 x i16> @VectorShortConstantPool() {
 ; CHECK-LABEL: VectorShortConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI5_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorShortConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC5@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorShortConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC4@toc@l(r3)
+; CHECK-P8-NEXT:    lxvw4x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: p2align        4
+; CHECK-P9-LABEL:.LCPI6_0:
+; CHECK-P9-NEXT:.long   2147483648
+; CHECK-P9-NEXT:.long   2147483649
+; CHECK-P9-NEXT:.long   2147483650
+; CHECK-P9-NEXT:.long   2147483651
  define <4 x i32> @VectorIntConstantPool() {
 ; CHECK-LABEL: VectorIntConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI6_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorIntConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC6@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC6@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorIntConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC5@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC5@toc@l(r3)
+; CHECK-P8-NEXT:    lxvw4x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI7_0:
+; CHECK-P9-NEXT:  .quad   -9223372036854775808
+; CHECK-P9-NEXT:  .quad   -9223372036854775807
  define <2 x i64> @VectorLongLongConstantPool() {
 ; CHECK-LABEL: VectorLongLongConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI7_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorLongLongConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC7@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC7@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorLongLongConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC6@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC6@toc@l(r3)
+; CHECK-P8-NEXT:    lxvd2x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: p2align        4
+; CHECK-P9-LABEL: .LCPI8_0:
+; CHECK-P9-NEXT: .quad   -2
+; CHECK-P9-NEXT: .quad   -9223372036854775808
  define <1 x i128> @VectorInt128ConstantPool() {
 ; CHECK-LABEL: VectorInt128ConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI8_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorInt128ConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI8_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC8@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorInt128ConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC7@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC7@toc@l(r3)
+; CHECK-P8-NEXT:    lxvd2x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <1 x i128> <i128 -27670116110564327424>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI9_0:
+; CHECK-P9-NEXT: .long   0x007fffe1
+; CHECK-P9-NEXT: .long   0x007ffd5f
+; CHECK-P9-NEXT: .long   0x021fffd9
+; CHECK-P9-NEXT: .long   0x021ffcb6
  define <4 x float> @VectorFloatConstantPool() {
 ; CHECK-LABEL: VectorFloatConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI9_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorFloatConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC9@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC9@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorFloatConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC8@toc@l(r3)
+; CHECK-P8-NEXT:    lxvw4x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI10_0:
+; CHECK-P9-NEXT: .quad   0x000ffffe2e8159d0
+; CHECK-P9-NEXT: .quad   0x000fffdd31a00c6d
  define <2 x double> @VectorDoubleConstantPool() {
 ; CHECK-LABEL: VectorDoubleConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI10_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: VectorDoubleConstantPool:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC10@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC10@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs34, 0, r3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: VectorDoubleConstantPool:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC9@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC9@toc@l(r3)
+; CHECK-P8-NEXT:    lxvd2x vs34, 0, r3
+; CHECK-P8-NEXT:    blr
 entry:
   ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI11_0:
+; CHECK-P9-NEXT: .quad   0x4002c083126e978d
+; CHECK-P9-NEXT: .quad   0x400ac083126e978d
 define double @two_constants(double %a) {
 ; CHECK-LABEL: two_constants:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfd f0, .LCPI11_0@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f0, f1, f0
 ; CHECK-NEXT:    plfd f1, .LCPI11_1@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f1, f0, f1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: two_constants:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI11_0@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI11_0@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI11_1@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC11@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC11@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f0, 8(r3)
 ; CHECK-P9-NEXT:    xsadddp f0, f1, f0
-; CHECK-P9-NEXT:    lfd f1, .LCPI11_1@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r3)
 ; CHECK-P9-NEXT:    xsadddp f1, f0, f1
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: two_constants:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC10@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC10@toc@l(r3)
+; CHECK-P8-NEXT:    lfd f0, 8(r3)
+; CHECK-P8-NEXT:    xsadddp f0, f1, f0
+; CHECK-P8-NEXT:    lfdx f1, 0, r3
+; CHECK-P8-NEXT:    xsadddp f1, f0, f1
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd double %a, 3.344000e+00
   %1 = fadd double %0, 2.344000e+00
   ret double %1
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI12_0:
+; CHECK-P9-NEXT: .quad   0x40123851eb851eb8
+; CHECK-P9-NEXT: .quad   0x4023c28f5c28f5c3
 define double @two_constants_two_bb(i32 %m, double %a) {
 ; CHECK-LABEL: two_constants_two_bb:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmplwi r3, 0
 ; CHECK-NEXT:    beq cr0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    plfd f1, .LCPI12_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %if.end
 ; CHECK-NEXT:    plfd f0, .LCPI12_1@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f1, f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: two_constants_two_bb:
 ; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    addis r4, r2, .LC12@toc@ha
 ; CHECK-P9-NEXT:    cmplwi r3, 0
+; CHECK-P9-NEXT:    ld r4, .LC12@toc@l(r4)
 ; CHECK-P9-NEXT:    beq cr0, .LBB12_2
 ; CHECK-P9-NEXT:  # %bb.1:
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-P9-NEXT:    lfd f1, .LCPI12_0@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r4)
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB12_2: # %if.end
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI12_1@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI12_1@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f0, 8(r4)
 ; CHECK-P9-NEXT:    xsadddp f1, f1, f0
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: two_constants_two_bb:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    cmplwi r3, 0
+; CHECK-P8-NEXT:    addis r3, r2, .LC11@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC11@toc@l(r3)
+; CHECK-P8-NEXT:    beq cr0, .LBB12_2
+; CHECK-P8-NEXT:  # %bb.1:
+; CHECK-P8-NEXT:    lfdx f1, 0, r3
+; CHECK-P8-NEXT:    blr
+; CHECK-P8-NEXT:  .LBB12_2: # %if.end
+; CHECK-P8-NEXT:    lfd f0, 8(r3)
+; CHECK-P8-NEXT:    xsadddp f1, f1, f0
+; CHECK-P8-NEXT:    blr
 entry:
   %tobool.not = icmp eq i32 %m, 0
   br i1 %tobool.not, label %if.end, label %return
 
 if.end:
   %add = fadd double %a, 9.880000e+00
   br label %return
 
 return:
   %retval.0 = phi double [ %add, %if.end ], [ 4.555000e+00, %entry ]
   ret double %retval.0
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI13_0:
+; CHECK-P9-NEXT: .quad   0x400326e978d4fdf4
+; CHECK-P9-NEXT: .quad   0x4002c083126e978d
+; CHECK-P9-NEXT: .quad   0x400ac083126e978d
 define double @three_constants_f64(double %a, double %c) {
 ; CHECK-LABEL: three_constants_f64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfd f0, .LCPI13_0@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f0, f1, f0
 ; CHECK-NEXT:    plfd f1, .LCPI13_1@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f0, f0, f1
 ; CHECK-NEXT:    plfd f1, .LCPI13_2@PCREL(0), 1
 ; CHECK-NEXT:    xsadddp f1, f0, f1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f64:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P9-NEXT:    lfd f0, .LCPI13_0@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_1@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC13@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC13@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f0, 16(r3)
 ; CHECK-P9-NEXT:    xsadddp f0, f1, f0
-; CHECK-P9-NEXT:    lfd f1, .LCPI13_1@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI13_2@toc@ha
+; CHECK-P9-NEXT:    lfd f1, 8(r3)
 ; CHECK-P9-NEXT:    xsadddp f0, f0, f1
-; CHECK-P9-NEXT:    lfd f1, .LCPI13_2@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r3)
 ; CHECK-P9-NEXT:    xsadddp f1, f0, f1
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: three_constants_f64:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC12@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC12@toc@l(r3)
+; CHECK-P8-NEXT:    lfd f0, 16(r3)
+; CHECK-P8-NEXT:    xsadddp f0, f1, f0
+; CHECK-P8-NEXT:    lfd f1, 8(r3)
+; CHECK-P8-NEXT:    xsadddp f0, f0, f1
+; CHECK-P8-NEXT:    lfdx f1, 0, r3
+; CHECK-P8-NEXT:    xsadddp f1, f0, f1
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd double %a, 3.344000e+00
   %1 = fadd double %0, 2.344000e+00
   %2 = fadd double %1, 2.394000e+00
   ret double %2
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        2
+; CHECK-P9-LABEL: .LCPI14_0:
+; CHECK-P9-NEXT: .long   0x4091bb8f
+; CHECK-P9-NEXT: .long   0x4091cc8f
+; CHECK-P9-NEXT: .long   0x4091c28f
 define float @three_constants_f32(float %a, float %c) {
 ; CHECK-LABEL: three_constants_f32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxspltidp vs0, 1083294351
 ; CHECK-NEXT:    xsaddsp f0, f1, f0
 ; CHECK-NEXT:    xxspltidp vs1, 1083296911
 ; CHECK-NEXT:    xsaddsp f0, f0, f1
 ; CHECK-NEXT:    xxspltidp vs1, 1083292559
 ; CHECK-NEXT:    xsaddsp f1, f0, f1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f32:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P9-NEXT:    lfs f0, .LCPI14_0@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_1@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC14@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC14@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f0, 8(r3)
 ; CHECK-P9-NEXT:    xsaddsp f0, f1, f0
-; CHECK-P9-NEXT:    lfs f1, .LCPI14_1@toc@l(r3)
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI14_2@toc@ha
+; CHECK-P9-NEXT:    lfs f1, 4(r3)
 ; CHECK-P9-NEXT:    xsaddsp f0, f0, f1
-; CHECK-P9-NEXT:    lfs f1, .LCPI14_2@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f1, 0(r3)
 ; CHECK-P9-NEXT:    xsaddsp f1, f0, f1
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: three_constants_f32:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC13@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC13@toc@l(r3)
+; CHECK-P8-NEXT:    lfs f0, 8(r3)
+; CHECK-P8-NEXT:    xsaddsp f0, f1, f0
+; CHECK-P8-NEXT:    lfs f1, 4(r3)
+; CHECK-P8-NEXT:    xsaddsp f0, f0, f1
+; CHECK-P8-NEXT:    lfsx f1, 0, r3
+; CHECK-P8-NEXT:    xsaddsp f1, f0, f1
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd float %a, 0x40123851E0000000
   %1 = fadd float %0, 0x40123991E0000000
   %2 = fadd float %1, 0x40123771E0000000
   ret float %2
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI15_0:
+; CHECK-P9-NEXT: .quad   0x400123851eb771eb
+; CHECK-P9-NEXT: .quad   0x8000000000000000
+; CHECK-P9-NEXT: .quad   0x400123851eb991eb
+; CHECK-P9-NEXT: .quad   0x8000000000000000
+; CHECK-P9-NEXT: .quad   0x400123851eb851eb
+; CHECK-P9-NEXT: .quad   0x8000000000000000
 define fp128 @three_constants_f128(fp128 %a, fp128 %c) {
 ; CHECK-LABEL: three_constants_f128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs35, .LCPI15_0@PCREL(0), 1
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    plxv vs35, .LCPI15_1@PCREL(0), 1
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    plxv vs35, .LCPI15_2@PCREL(0), 1
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_f128:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-NEXT:    lxvx vs35, 0, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_1@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC15@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC15@toc@l(r3)
+; CHECK-P9-NEXT:    lxv vs35, 32(r3)
 ; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
-; CHECK-P9-NEXT:    lxvx vs35, 0, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_2@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_2@toc@l
+; CHECK-P9-NEXT:    lxv vs35, 16(r3)
 ; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-P9-NEXT:    lxvx vs35, 0, r3
 ; CHECK-P9-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: three_constants_f128:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r29, -24
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -64(r1)
+; CHECK-P8-NEXT:    lis r5, 16385
+; CHECK-P8-NEXT:    ori r5, r5, 9093
+; CHECK-P8-NEXT:    sldi r29, r5, 32
+; CHECK-P8-NEXT:    li r5, 1
+; CHECK-P8-NEXT:    oris r6, r29, 7864
+; CHECK-P8-NEXT:    sldi r30, r5, 63
+; CHECK-P8-NEXT:    ori r5, r6, 20971
+; CHECK-P8-NEXT:    mr r6, r30
+; CHECK-P8-NEXT:    bl __addkf3
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    oris r5, r29, 7865
+; CHECK-P8-NEXT:    mr r6, r30
+; CHECK-P8-NEXT:    ori r5, r5, 37355
+; CHECK-P8-NEXT:    bl __addkf3
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    oris r5, r29, 7863
+; CHECK-P8-NEXT:    mr r6, r30
+; CHECK-P8-NEXT:    ori r5, r5, 29163
+; CHECK-P8-NEXT:    bl __addkf3
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    addi r1, r1, 64
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB
   %1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB
   %2 = fadd fp128 %1, 0xL8000000000000000400123851EB771EB
   ret fp128 %2
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: p2align        3
+; CHECK-P9-LABEL: .LCPI16_0:
+; CHECK-P9-NEXT: .quad   0x40123851eb851eb8
+; CHECK-P9-NEXT: .quad   0x4012385199851eb8
+; CHECK-P9-NEXT: .quad   0x4012385100851eb8
 define ppc_fp128 @three_constants_ppcf128(ppc_fp128 %a, ppc_fp128 %c) {
 ; CHECK-LABEL: three_constants_ppcf128:
 ; CHECK:         .localentry three_constants_ppcf128, 1
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32

 ; CHECK-NEXT:    addi r1, r1, 32
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_ppcf128:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mflr r0
-; CHECK-P9-NEXT:    std r0, 16(r1)
-; CHECK-P9-NEXT:    stdu r1, -32(r1)
-; CHECK-P9-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P9-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-P9-NEXT:    .cfi_offset lr, 16
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
+; CHECK-P9-NEXT:    .cfi_offset r30, -16
+; CHECK-P9-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT:    std r0, 16(r1)
+; CHECK-P9-NEXT:    stdu r1, -48(r1)
+; CHECK-P9-NEXT:    addis r3, r2, .LC16@toc@ha
 ; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_0@toc@l(r3)
+; CHECK-P9-NEXT:    ld r30, .LC16@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f3, 0(r30)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_1@toc@ha
+; CHECK-P9-NEXT:    lfd f3, 8(r30)
 ; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_1@toc@l(r3)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_2@toc@ha
+; CHECK-P9-NEXT:    lfd f3, 16(r30)
 ; CHECK-P9-NEXT:    xxlxor f4, f4, f4
-; CHECK-P9-NEXT:    lfd f3, .LCPI16_2@toc@l(r3)
 ; CHECK-P9-NEXT:    bl __gcc_qadd
 ; CHECK-P9-NEXT:    nop
-; CHECK-P9-NEXT:    addi r1, r1, 32
+; CHECK-P9-NEXT:    addi r1, r1, 48
 ; CHECK-P9-NEXT:    ld r0, 16(r1)
+; CHECK-P9-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P9-NEXT:    mtlr r0
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: three_constants_ppcf128:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -48(r1)
+; CHECK-P8-NEXT:    addis r3, r2, .LC14@toc@ha
+; CHECK-P8-NEXT:    xxlxor f4, f4, f4
+; CHECK-P8-NEXT:    ld r30, .LC14@toc@l(r3)
+; CHECK-P8-NEXT:    lfdx f3, 0, r30
+; CHECK-P8-NEXT:    bl __gcc_qadd
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    xxlxor f4, f4, f4
+; CHECK-P8-NEXT:    lfd f3, 8(r30)
+; CHECK-P8-NEXT:    bl __gcc_qadd
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    xxlxor f4, f4, f4
+; CHECK-P8-NEXT:    lfd f3, 16(r30)
+; CHECK-P8-NEXT:    bl __gcc_qadd
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    addi r1, r1, 48
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd ppc_fp128 %a, 0xM40123851EB851EB80000000000000000
   %1 = fadd ppc_fp128 %0, 0xM4012385199851EB80000000000000000
   %2 = fadd ppc_fp128 %1, 0xM4012385100851EB80000000000000000
   ret ppc_fp128 %2
 }
 
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI17_0:
+; CHECK-P9-NEXT: .quad   0x40123851eb851eb8
+; CHECK-P9-NEXT: .quad   0x4023f5c28f5c28f6
+; CHECK-P9-NEXT: .quad   0x40123851eb851eb8
+; CHECK-P9-NEXT: .quad   0x4023c28f5c28f5c3
 define <2 x double> @three_constants_vector(<2 x double> %a, <2 x double> %c) {
 ; CHECK-LABEL: three_constants_vector:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs0, .LCPI17_0@PCREL(0), 1
 ; CHECK-NEXT:    plxv vs2, .LCPI17_1@PCREL(0), 1
 ; CHECK-NEXT:    xvadddp vs1, vs34, vs0
 ; CHECK-NEXT:    xvadddp vs1, vs1, vs2
 ; CHECK-NEXT:    xvadddp vs34, vs1, vs0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: three_constants_vector:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI17_0@toc@l
-; CHECK-P9-NEXT:    lxvx vs0, 0, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI17_1@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI17_1@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC17@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC17@toc@l(r3)
+; CHECK-P9-NEXT:    lxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    lxvx vs2, 0, r3
 ; CHECK-P9-NEXT:    xvadddp vs1, vs34, vs0
 ; CHECK-P9-NEXT:    xvadddp vs1, vs1, vs2
 ; CHECK-P9-NEXT:    xvadddp vs34, vs1, vs0
 ; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: three_constants_vector:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LC15@toc@ha
+; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    ld r3, .LC15@toc@l(r3)
+; CHECK-P8-NEXT:    lxvd2x vs0, r3, r4
+; CHECK-P8-NEXT:    lxvd2x vs2, 0, r3
+; CHECK-P8-NEXT:    xvadddp vs1, vs34, vs0
+; CHECK-P8-NEXT:    xvadddp vs1, vs1, vs2
+; CHECK-P8-NEXT:    xvadddp vs34, vs1, vs0
+; CHECK-P8-NEXT:    blr
 entry:
   %0 = fadd <2 x double> %a, <double 4.555000e+00, double 9.880000e+00>
   %1 = fadd <2 x double> %0, <double 4.555000e+00, double 9.980000e+00>
   %2 = fadd <2 x double> %1, <double 4.555000e+00, double 9.880000e+00>
   ret <2 x double> %2
 }
+
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        4
+; CHECK-P9-LABEL: .LCPI18_0:
+; CHECK-P9-NEXT: .quad   0x402871a9fbe76c8b
+; CHECK-P9-NEXT: .quad   0x402871a9fbe76c8b
+; CHECK-P9-NEXT: .quad   0x407563b2fec56d5d
+; CHECK-P9-NEXT: .quad   0x412446e7f9db22d1
+; CHECK-P9-LABEL: .LCPI18_1:
+; CHECK-P9-NEXT: .quad   0x40a2939884e831ad
+; CHECK-P9-LABEL: .LCPI18_2:
+; CHECK-P9-NEXT: .long   0x4457499a
+; CHECK-P9-NEXT: .long   0x4479f852
+define void @constant_pool_mixed_type(<2 x double>* %ArrV, double* %ArrD, i16* %ArrS, float* %ArrF) {
+; CHECK-P9-LABEL: constant_pool_mixed_type:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lis r7, 12
+; CHECK-P9-NEXT:    ori r7, r7, 44
+; CHECK-P9-NEXT:    sldi r7, r7, 32
+; CHECK-P9-NEXT:    oris r7, r7, 8
+; CHECK-P9-NEXT:    ori r7, r7, 98
+; CHECK-P9-NEXT:    std r7, 0(r5)
+; CHECK-P9-NEXT:    lis r7, 271
+; CHECK-P9-NEXT:    ori r7, r7, 888
+; CHECK-P9-NEXT:    stw r7, 8(r5)
+; CHECK-P9-NEXT:    li r7, 99
+; CHECK-P9-NEXT:    sth r7, 12(r5)
+; CHECK-P9-NEXT:    addis r5, r2, .LC18@toc@ha
+; CHECK-P9-NEXT:    lfs f0, 0(r6)
+; CHECK-P9-NEXT:    ld r5, .LC18@toc@l(r5)
+; CHECK-P9-NEXT:    lfs f1, 4(r5)
+; CHECK-P9-NEXT:    xsaddsp f0, f0, f1
+; CHECK-P9-NEXT:    lfs f1, 0(r5)
+; CHECK-P9-NEXT:    addis r5, r2, .LC19@toc@ha
+; CHECK-P9-NEXT:    ld r5, .LC19@toc@l(r5)
+; CHECK-P9-NEXT:    stfs f0, 0(r6)
+; CHECK-P9-NEXT:    lfs f0, 4(r6)
+; CHECK-P9-NEXT:    xsaddsp f0, f0, f1
+; CHECK-P9-NEXT:    stfs f0, 4(r6)
+; CHECK-P9-NEXT:    lxv vs0, 16(r5)
+; CHECK-P9-NEXT:    stxv vs0, 0(r3)
+; CHECK-P9-NEXT:    lxvx vs0, 0, r5
+; CHECK-P9-NEXT:    stxv vs0, 16(r3)
+; CHECK-P9-NEXT:    addis r3, r2, .LC20@toc@ha
+; CHECK-P9-NEXT:    lfd f0, 40(r4)
+; CHECK-P9-NEXT:    ld r3, .LC20@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r3)
+; CHECK-P9-NEXT:    xsadddp f0, f0, f1
+; CHECK-P9-NEXT:    stfd f0, 40(r4)
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: constant_pool_mixed_type:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    lis r7, 12
+; CHECK-P8-NEXT:    addis r8, r2, .LC16@toc@ha
+; CHECK-P8-NEXT:    lis r9, 271
+; CHECK-P8-NEXT:    li r10, 99
+; CHECK-P8-NEXT:    ori r7, r7, 44
+; CHECK-P8-NEXT:    ld r8, .LC16@toc@l(r8)
+; CHECK-P8-NEXT:    ori r9, r9, 888
+; CHECK-P8-NEXT:    sth r10, 12(r5)
+; CHECK-P8-NEXT:    sldi r7, r7, 32
+; CHECK-P8-NEXT:    stw r9, 8(r5)
+; CHECK-P8-NEXT:    oris r7, r7, 8
+; CHECK-P8-NEXT:    ori r7, r7, 98
+; CHECK-P8-NEXT:    lfsx f2, 0, r8
+; CHECK-P8-NEXT:    std r7, 0(r5)
+; CHECK-P8-NEXT:    addis r7, r2, .LC17@toc@ha
+; CHECK-P8-NEXT:    lfs f0, 4(r8)
+; CHECK-P8-NEXT:    lfsx f1, 0, r6
+; CHECK-P8-NEXT:    ld r7, .LC17@toc@l(r7)
+; CHECK-P8-NEXT:    li r8, 16
+; CHECK-P8-NEXT:    lfs f3, 4(r6)
+; CHECK-P8-NEXT:    xsaddsp f0, f1, f0
+; CHECK-P8-NEXT:    xsaddsp f1, f3, f2
+; CHECK-P8-NEXT:    lxvd2x vs2, r7, r8
+; CHECK-P8-NEXT:    lxvd2x vs3, 0, r7
+; CHECK-P8-NEXT:    addis r7, r2, .LC18@toc@ha
+; CHECK-P8-NEXT:    ld r7, .LC18@toc@l(r7)
+; CHECK-P8-NEXT:    stfsx f0, 0, r6
+; CHECK-P8-NEXT:    stfs f1, 4(r6)
+; CHECK-P8-NEXT:    stxvd2x vs2, 0, r3
+; CHECK-P8-NEXT:    lfdx f1, 0, r7
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r8
+; CHECK-P8-NEXT:    lfd f0, 40(r4)
+; CHECK-P8-NEXT:    xsadddp f0, f0, f1
+; CHECK-P8-NEXT:    stfd f0, 40(r4)
+; CHECK-P8-NEXT:    blr
+entry:
+; Ensure that these are still widened to 8b + 4b + 2b
+  store i16 12, i16* %ArrS, align 2
+  %arrayidx1 = getelementptr inbounds i16, i16* %ArrS, i64 1
+  store i16 44, i16* %arrayidx1, align 2
+  %arrayidx2 = getelementptr inbounds i16, i16* %ArrS, i64 2
+  store i16 8, i16* %arrayidx2, align 2
+  %arrayidx3 = getelementptr inbounds i16, i16* %ArrS, i64 3
+  store i16 98, i16* %arrayidx3, align 2
+  %arrayidx4 = getelementptr inbounds i16, i16* %ArrS, i64 4
+  store i16 271, i16* %arrayidx4, align 2
+  %arrayidx5 = getelementptr inbounds i16, i16* %ArrS, i64 5
+  store i16 888, i16* %arrayidx5, align 2
+  %arrayidx6 = getelementptr inbounds i16, i16* %ArrS, i64 6
+  store i16 99, i16* %arrayidx6, align 2
+; These are not vectorized, check 4b alignment
+  %0 = load float, float* %ArrF, align 4
+  %add = fadd fast float %0, 0x408F3F0A40000000
+  store float %add, float* %ArrF, align 4
+  %arrayidx8 = getelementptr inbounds float, float* %ArrF, i64 1
+  %1 = load float, float* %arrayidx8, align 4
+  %add9 = fadd fast float %1, 0x408AE93340000000
+  store float %add9, float* %arrayidx8, align 4
+; These are vectorized, check 16b alignment
+  store <2 x double> <double 0x407563B2FEC56D5D, double 0x412446E7F9DB22D1>, <2 x double>* %ArrV, align 16
+  %arrayidx12 = getelementptr inbounds <2 x double>, <2 x double>* %ArrV, i64 1
+  store <2 x double> <double 1.222200e+01, double 1.222200e+01>, <2 x double>* %arrayidx12, align 16
+; Check 8b alignment
+  %arrayidx13 = getelementptr inbounds double, double* %ArrD, i64 5
+  %2 = load double, double* %arrayidx13, align 8
+  %add14 = fadd fast double %2, 0x40A2939884E831AD
+  store double %add14, double* %arrayidx13, align 8
+  ret void
+}
+
+; CHECK-P9: .section        .data.rel.ro,"aw",@progbits
+; CHECK-P9: .p2align        3
+; CHECK-P9-LABEL: .LCPI19_0:
+; CHECK-P9-NEXT: .long   0x42b5cccd
+; CHECK-P9-NEXT: .space  4
+; CHECK-P9-LABEL: .LCPI19_1:
+; CHECK-P9-NEXT: .quad   0x4012333333333333
+define void @constant_pool_padding() {
+; CHECK-LABEL: constant_pool_padding:
+; CHECK:         .localentry constant_pool_padding, 1
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -32(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    plfd f1, .LCPI19_0@PCREL(0), 1
+; CHECK-NEXT:    xxspltidp vs2, 1119210701
+; CHECK-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
+; CHECK-NEXT:    bl bar@notoc
+; CHECK-NEXT:    addi r1, r1, 32
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+;
+; CHECK-P9-LABEL: constant_pool_padding:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    mflr r0
+; CHECK-P9-NEXT:    std r0, 16(r1)
+; CHECK-P9-NEXT:    stdu r1, -32(r1)
+; CHECK-P9-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P9-NEXT:    .cfi_offset lr, 16
+; CHECK-P9-NEXT:    addis r3, r2, .LC21@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC21@toc@l(r3)
+; CHECK-P9-NEXT:    lfd f1, 0(r3)
+; CHECK-P9-NEXT:    addis r3, r2, .LC22@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC22@toc@l(r3)
+; CHECK-P9-NEXT:    lfs f2, 0(r3)
+; CHECK-P9-NEXT:    bl bar
+; CHECK-P9-NEXT:    nop
+; CHECK-P9-NEXT:    addi r1, r1, 32
+; CHECK-P9-NEXT:    ld r0, 16(r1)
+; CHECK-P9-NEXT:    mtlr r0
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P8-LABEL: constant_pool_padding:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -32(r1)
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    addis r3, r2, .LC19@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC20@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC19@toc@l(r3)
+; CHECK-P8-NEXT:    ld r4, .LC20@toc@l(r4)
+; CHECK-P8-NEXT:    lfdx f1, 0, r3
+; CHECK-P8-NEXT:    lfsx f2, 0, r4
+; CHECK-P8-NEXT:    bl bar
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    addi r1, r1, 32
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
+entry:
+  call void @bar(double 4.550000e+00, float 0x4056B999A0000000)
+  ret void
+}
+declare void @bar(double, float)
+
+; CHECK-P9: .section        .toc,"aw",@progbits
+; CHECK-P9-LABEL: .LC0:
+; CHECK-P9-NEXT: .tc .LCPI0_0[TC],.LCPI0_0
+; CHECK-P9-LABEL: .LC1:
+; CHECK-P9-NEXT: .tc .LCPI1_0[TC],.LCPI1_0
+; CHECK-P9-LABEL: .LC2:
+; CHECK-P9-NEXT: .tc .LCPI2_0[TC],.LCPI2_0
+; CHECK-P9-LABEL: .LC3:
+; CHECK-P9-NEXT: .tc .LCPI3_0[TC],.LCPI3_0
+; CHECK-P9-LABEL: .LC4:
+; CHECK-P9-NEXT: .tc .LCPI4_0[TC],.LCPI4_0
+; CHECK-P9-LABEL: .LC5:
+; CHECK-P9-NEXT: .tc .LCPI5_0[TC],.LCPI5_0
+; CHECK-P9-LABEL: .LC6:
+; CHECK-P9-NEXT: .tc .LCPI6_0[TC],.LCPI6_0
+; CHECK-P9-LABEL: .LC7:
+; CHECK-P9-NEXT: .tc .LCPI7_0[TC],.LCPI7_0
+; CHECK-P9-LABEL: .LC8:
+; CHECK-P9-NEXT: .tc .LCPI8_0[TC],.LCPI8_0
+; CHECK-P9-LABEL: .LC9:
+; CHECK-P9-NEXT: .tc .LCPI9_0[TC],.LCPI9_0
+; CHECK-P9-LABEL: .LC10:
+; CHECK-P9-NEXT: .tc .LCPI10_0[TC],.LCPI10_0
+; CHECK-P9-LABEL: .LC11:
+; CHECK-P9-NEXT: .tc .LCPI11_0[TC],.LCPI11_0
+; CHECK-P9-LABEL: .LC12:
+; CHECK-P9-NEXT: .tc .LCPI12_0[TC],.LCPI12_0
+; CHECK-P9-LABEL: .LC13:
+; CHECK-P9-NEXT: .tc .LCPI13_0[TC],.LCPI13_0
+; CHECK-P9-LABEL: .LC14:
+; CHECK-P9-NEXT: .tc .LCPI14_0[TC],.LCPI14_0
+; CHECK-P9-LABEL: .LC15:
+; CHECK-P9-NEXT: .tc .LCPI15_0[TC],.LCPI15_0
+; CHECK-P9-LABEL: .LC16:
+; CHECK-P9-NEXT: .tc .LCPI16_0[TC],.LCPI16_0
+; CHECK-P9-LABEL: .LC17:
+; CHECK-P9-NEXT: .tc .LCPI17_0[TC],.LCPI17_0
+; CHECK-P9-LABEL: .LC18:
+; CHECK-P9-NEXT: .tc .LCPI18_2[TC],.LCPI18_2
+; CHECK-P9-LABEL: .LC19:
+; CHECK-P9-NEXT: .tc .LCPI18_0[TC],.LCPI18_0
+; CHECK-P9-LABEL: .LC20:
+; CHECK-P9-NEXT: .tc .LCPI18_1[TC],.LCPI18_1
+; CHECK-P9-LABEL: .LC21:
+; CHECK-P9-NEXT: .tc .LCPI19_1[TC],.LCPI19_1
+; CHECK-P9-LABEL: .LC22:
+; CHECK-P9-NEXT: .tc .LCPI19_0[TC],.LCPI19_0

llvm/test/CodeGen/PowerPC/extract-and-store.ll

entry:
   %arrayidx2 = getelementptr inbounds float, float* %b, i64 1
   store float %vecext1, float* %arrayidx2, align 4
   ret void
 }
 
 define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_stores_exceed_vec_size:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xxsldwi vs1, vs34, vs34, 1
 ; CHECK-NEXT:    li r4, 20
-; CHECK-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lvx v3, 0, r3
 ; CHECK-NEXT:    li r3, 16
 ; CHECK-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-NEXT:    xxswapd vs0, vs35
 ; CHECK-NEXT:    stxvd2x vs0, 0, r5
 ; CHECK-NEXT:    stfiwx f1, r5, r3
 ; CHECK-NEXT:    stxsiwx vs34, r5, r4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_stores_exceed_vec_size:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxspltw vs0, vs34, 0
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs34, vs34, 1
 ; CHECK-BE-NEXT:    li r3, 16
 ; CHECK-BE-NEXT:    li r4, 20
 ; CHECK-BE-NEXT:    stxsiwx vs34, r5, r3
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs34, vs0, 2
 ; CHECK-BE-NEXT:    stfiwx f1, r5, r4
 ; CHECK-BE-NEXT:    stxvw4x vs0, 0, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx vs35, 0, r3
 ; CHECK-P9-NEXT:    li r3, 16
 ; CHECK-P9-NEXT:    stfiwx f0, r5, r3
 ; CHECK-P9-NEXT:    li r3, 20
 ; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs35, 0(r5)
 ; CHECK-P9-NEXT:    blr

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

entry:
   ret fp128 %0
 }
 
 ; Function Attrs: nounwind
 define fp128 @sum_float128(i32 signext %count, ...) {
 ; CHECK-LABEL: sum_float128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std r4, 40(r1)
-; CHECK-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
+; CHECK-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    std r5, 48(r1)
-; CHECK-NEXT:    addi r4, r4, .LCPI17_0@toc@l
+; CHECK-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-NEXT:    std r6, 56(r1)
 ; CHECK-NEXT:    std r7, 64(r1)
 ; CHECK-NEXT:    std r8, 72(r1)
-; CHECK-NEXT:    lxvx v2, 0, r4
 ; CHECK-NEXT:    std r9, 80(r1)
+; CHECK-NEXT:    lxvx v2, 0, r4
 ; CHECK-NEXT:    std r10, 88(r1)
 ; CHECK-NEXT:    bltlr cr0
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    addi r3, r1, 40
 ; CHECK-NEXT:    addi r4, r1, 72
 ; CHECK-NEXT:    lxvx v3, 0, r3
 ; CHECK-NEXT:    std r4, -8(r1)
 ; CHECK-NEXT:    xsaddqp v2, v3, v2
 ; CHECK-NEXT:    lxv v3, 16(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: sum_float128:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    std r4, 56(r1)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    std r5, 64(r1)
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI17_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-BE-NEXT:    std r6, 72(r1)
 ; CHECK-BE-NEXT:    std r7, 80(r1)
 ; CHECK-BE-NEXT:    std r8, 88(r1)
-; CHECK-BE-NEXT:    lxvx v2, 0, r4
 ; CHECK-BE-NEXT:    std r9, 96(r1)
+; CHECK-BE-NEXT:    lxvx v2, 0, r4
 ; CHECK-BE-NEXT:    std r10, 104(r1)
 ; CHECK-BE-NEXT:    bltlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %if.end
 ; CHECK-BE-NEXT:    addi r3, r1, 56
 ; CHECK-BE-NEXT:    addi r4, r1, 88
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    std r4, -8(r1)
 ; CHECK-BE-NEXT:    xsaddqp v2, v3, v2

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant() {
 ; CHECK-LABEL: loadConstant:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lxvx v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: loadConstant:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r3, 1
 ; CHECK-P8-NEXT:    ori r3, r3, 5
 ; CHECK-P8-NEXT:    sldi r4, r3, 46
 ; CHECK-P8-NEXT:    li r3, 0
 ; CHECK-P8-NEXT:    blr
   entry:
     ret fp128 0xL00000000000000004001400000000000
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant2(fp128 %a, fp128 %b) {
 ; CHECK-LABEL: loadConstant2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
-; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-NEXT:    lxvx v3, 0, r3
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: loadConstant2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    mflr r0
 ; CHECK-P8-NEXT:    std r0, 16(r1)

llvm/test/CodeGen/PowerPC/float-logic-ops.ll

entry:
   %and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647>
   %conv1 = bitcast <4 x i32> %and to <4 x float>
   ret <4 x float> %conv1
 }
 
 define <4 x float> @absv4f32_invalid(<4 x float> %a) {
 ; CHECK-LABEL: absv4f32_invalid:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lvx v3, 0, r3
 ; CHECK-NEXT:    xxland vs34, vs34, vs35
 ; CHECK-NEXT:    blr
 entry:
   %conv = bitcast <4 x float> %a to <4 x i32>
   %and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647>
   %conv1 = bitcast <4 x i32> %and to <4 x float>
   ret <4 x float> %conv1

llvm/test/CodeGen/PowerPC/fma-combine.ll

entry:
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define float @fma_combine_no_ice() {
 ; CHECK-FAST-LABEL: fma_combine_no_ice:
 ; CHECK-FAST:       # %bb.0:
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-FAST-NEXT:    addis 4, 2, .LCPI4_1@toc@ha
-; CHECK-FAST-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
+; CHECK-FAST-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-FAST-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-FAST-NEXT:    lfs 0, 8(3)
 ; CHECK-FAST-NEXT:    lfsx 2, 0, 3
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-FAST-NEXT:    lfs 3, .LCPI4_1@toc@l(4)
-; CHECK-FAST-NEXT:    lfs 1, .LCPI4_2@toc@l(3)
+; CHECK-FAST-NEXT:    lfs 3, 4(3)
+; CHECK-FAST-NEXT:    lfsx 1, 0, 3
 ; CHECK-FAST-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-FAST-NEXT:    xsmaddasp 1, 2, 3
 ; CHECK-FAST-NEXT:    xsnmsubasp 1, 3, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice:
 ; CHECK-FAST-NOVSX:       # %bb.0:
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
-; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_1@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmadds 0, 1, 2, 0
-; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_2@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    fmadds 2, 1, 0, 2
-; CHECK-FAST-NOVSX-NEXT:    fnmsubs 1, 0, 1, 2
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 0, 0(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 1, 4(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 2, 8(3)
+; CHECK-FAST-NOVSX-NEXT:    fmadds 1, 0, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    lfs 2, 0(3)
+; CHECK-FAST-NOVSX-NEXT:    fmadds 2, 0, 1, 2
+; CHECK-FAST-NOVSX-NEXT:    fnmsubs 1, 1, 0, 2
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_no_ice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI4_1@toc@ha
-; CHECK-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    lfs 0, 8(3)
 ; CHECK-NEXT:    lfsx 2, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-NEXT:    lfs 3, .LCPI4_1@toc@l(4)
-; CHECK-NEXT:    lfs 1, .LCPI4_2@toc@l(3)
+; CHECK-NEXT:    lfs 3, 4(3)
+; CHECK-NEXT:    lfsx 1, 0, 3
 ; CHECK-NEXT:    fmr 4, 3
 ; CHECK-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-NEXT:    xsnmaddasp 4, 2, 0
 ; CHECK-NEXT:    xsmaddasp 1, 2, 3
 ; CHECK-NEXT:    xsmaddasp 1, 4, 2
 ; CHECK-NEXT:    blr
   %tmp = load float, float* undef, align 4
   %tmp2 = load float, float* undef, align 4
; CHECK-NEXT:    blr
   %tmp12 = fadd reassoc float %tmp11, %tmp10
   ret float %tmp12
 }
 
 ; This would crash while trying getNegatedExpression().
 define double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST:       # %bb.0:
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-FAST-NEXT:    addis 4, 2, .LCPI5_0@toc@ha
-; CHECK-FAST-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
-; CHECK-FAST-NEXT:    lfs 4, .LCPI5_0@toc@l(4)
+; CHECK-FAST-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-FAST-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-FAST-NEXT:    lfs 3, 4(3)
+; CHECK-FAST-NEXT:    lfsx 4, 0, 3
 ; CHECK-FAST-NEXT:    xssubdp 0, 1, 3
 ; CHECK-FAST-NEXT:    xsmaddadp 3, 1, 4
 ; CHECK-FAST-NEXT:    xsmaddadp 0, 3, 2
 ; CHECK-FAST-NEXT:    fmr 1, 0
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST-NOVSX:       # %bb.0:
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    addis 4, 2, .LCPI5_1@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI5_0@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    lfs 3, .LCPI5_1@toc@l(4)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 0, 4(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 3, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 3, 1, 3, 0
 ; CHECK-FAST-NOVSX-NEXT:    fsub 0, 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 1, 3, 2, 0
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: getNegatedExpression_crash:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI5_0@toc@ha
-; CHECK-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
-; CHECK-NEXT:    lfs 4, .LCPI5_0@toc@l(4)
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    lfs 3, 4(3)
+; CHECK-NEXT:    lfsx 4, 0, 3
 ; CHECK-NEXT:    xssubdp 0, 1, 3
 ; CHECK-NEXT:    xsmaddadp 3, 1, 4
 ; CHECK-NEXT:    xsmaddadp 0, 3, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
   %neg = fneg reassoc double %x
   %fma = call reassoc nsz double @llvm.fma.f64(double %neg, double 42.0, double -1.0)
   %add = fadd reassoc nsz double %x, 1.0
   %fma1 = call reassoc nsz double @llvm.fma.f64(double %fma, double %y, double %add)
   ret double %fma1
 }
 
 define double @fma_flag_propagation(double %a) {
 ; CHECK-FAST-LABEL: fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xxlxor 1, 1, 1
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_flag_propagation:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 1, .LCPI6_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_flag_propagation:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor 1, 1, 1
 ; CHECK-NEXT:    blr
 entry:
   %0 = fneg double %a
   %1 = call reassoc nnan double @llvm.fma.f64(double %0, double 1.0, double %a)
   ret double %1
 }
 
 define double @neg_fma_flag_propagation(double %a) {
 ; CHECK-FAST-LABEL: neg_fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xxlxor 1, 1, 1
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: neg_fma_flag_propagation:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 1, .LCPI7_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: neg_fma_flag_propagation:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor 1, 1, 1
 ; CHECK-NEXT:    blr
 entry:
   %0 = call reassoc nnan double @llvm.fma.f64(double %a, double -1.0, double %a)
   ret double %0
 }
 
 define <2 x double> @vec_neg_fma_flag_propagation(<2 x double> %a) {
 ; CHECK-FAST-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; CHECK-FAST-NEXT:    addi 3, 3, .LCPI8_0@toc@l
+; CHECK-FAST-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-FAST-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-FAST-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-FAST-NEXT:    xxswapd 0, 0
 ; CHECK-FAST-NEXT:    xvmaddadp 34, 34, 0
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 1, .LCPI8_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmr 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: vec_neg_fma_flag_propagation:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI8_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 0, 0
 ; CHECK-NEXT:    xvmaddadp 34, 34, 0
 ; CHECK-NEXT:    blr
 entry:
   %0 = call reassoc nnan <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> <double -1.0, double -1.0>, <2 x double> %a)
   ret <2 x double> %0
 }
 
 define double @fma_combine_const(double %a, double %b) {
 ; CHECK-FAST-LABEL: fma_combine_const:
 ; CHECK-FAST:       # %bb.0: # %entry
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; CHECK-FAST-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
+; CHECK-FAST-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-FAST-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-FAST-NEXT:    lfdx 0, 0, 3
 ; CHECK-FAST-NEXT:    xsmaddadp 2, 1, 0
 ; CHECK-FAST-NEXT:    fmr 1, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_const:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    ld 3, .LC5@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfd 0, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 1, 1, 0, 2
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_const:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; CHECK-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; CHECK-NEXT:    lfd 3, .LCPI9_1@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-NEXT:    lfd 0, 8(3)
+; CHECK-NEXT:    lfdx 3, 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 1, 0
 ; CHECK-NEXT:    fmr 1, 2
 ; CHECK-NEXT:    xsmaddadp 1, 0, 3
 ; CHECK-NEXT:    blr
 entry:
   %0 = fmul double %a, 1.1
   %1 = call contract double @llvm.fma.f64(double %0, double 2.1, double %b)
   ret double %1
 }
 
 declare double @llvm.fma.f64(double, double, double) nounwind readnone
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone

llvm/test/CodeGen/PowerPC/fma-mutate.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
 
 declare double @llvm.sqrt.f64(double)
 
 ; Test several VSX FMA mutation opportunities.
 
 ; This is reasonable transformation since it eliminates extra register copy.
 define double @foo3_fmf(double %a) nounwind {
 ; CHECK-LABEL: foo3_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xstsqrtdp 0, 1
 ; CHECK-NEXT:    bc 12, 2, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    xsrsqrtedp 0, 1
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    lfs 3, .LCPI0_0@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    lfs 4, .LCPI0_1@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    lfs 3, 4(3)
+; CHECK-NEXT:    lfs 4, 0(3)
 ; CHECK-NEXT:    xsmuldp 2, 1, 0
 ; CHECK-NEXT:    xsmaddmdp 2, 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-NEXT:    xsmuldp 0, 1, 4
 ; CHECK-NEXT:    xsmuldp 1, 0, 3

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
 ; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc1:'
 
 define float @fmul_fma_reassoc1(float %x) {
 ; FMF-LABEL: fmul_fma_reassoc1:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
-; FMF-NEXT:    lfs 0, .LCPI6_0@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LC0@toc@ha
+; FMF-NEXT:    ld 3, .LC0@toc@l(3)
+; FMF-NEXT:    lfsx 0, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_reassoc1:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
-; GLOBAL-NEXT:    lfs 0, .LCPI6_0@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LC0@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC0@toc@l(3)
+; GLOBAL-NEXT:    lfsx 0, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
   %mul = fmul float %x, 42.0
   %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc2:'
 ; FMFDEBUG:         fmul reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc2:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc2:'
 ; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc2:'
 
 define float @fmul_fma_reassoc2(float %x) {
 ; FMF-LABEL: fmul_fma_reassoc2:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; FMF-NEXT:    lfs 0, .LCPI7_0@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LC1@toc@ha
+; FMF-NEXT:    ld 3, .LC1@toc@l(3)
+; FMF-NEXT:    lfsx 0, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_reassoc2:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; GLOBAL-NEXT:    lfs 0, .LCPI7_0@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LC1@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC1@toc@l(3)
+; GLOBAL-NEXT:    lfsx 0, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, 42.0
   %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; The FMA is now fully 'fast'. This implies that reassociation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast1:'
 ; FMFDEBUG:         fmul reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast1:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast1:'
 ; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast1:'
 
 define float @fmul_fma_fast1(float %x) {
 ; FMF-LABEL: fmul_fma_fast1:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; FMF-NEXT:    lfs 0, .LCPI8_0@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LC2@toc@ha
+; FMF-NEXT:    ld 3, .LC2@toc@l(3)
+; FMF-NEXT:    lfsx 0, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_fast1:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    addis 3, 2, .LCPI8_0@toc@ha
-; GLOBAL-NEXT:    lfs 0, .LCPI8_0@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LC2@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC2@toc@l(3)
+; GLOBAL-NEXT:    lfsx 0, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
   %mul = fmul float %x, 42.0
   %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast2:'
 ; FMFDEBUG:         fmul reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast2:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_fast2:'
 ; GLOBALDEBUG:         fmul reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fma_fast2:'
 
 define float @fmul_fma_fast2(float %x) {
 ; FMF-LABEL: fmul_fma_fast2:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; FMF-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LC3@toc@ha
+; FMF-NEXT:    ld 3, .LC3@toc@l(3)
+; FMF-NEXT:    lfsx 0, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fma_fast2:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
-; GLOBAL-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LC3@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC3@toc@l(3)
+; GLOBAL-NEXT:    lfsx 0, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, 42.0
   %fma = call reassoc float @llvm.fma.f32(float %x, float 7.0, float %mul)
   ret float %fma
 }
 
 ; Reduced precision for sqrt is allowed - should use estimate and NR iterations.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
 ; FMFDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
 ; GLOBALDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'
 
 define float @sqrt_afn_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_afn_ieee:
 ; FMF:       # %bb.0:
+; FMF-NEXT:    addis 3, 2, .LC4@toc@ha
 ; FMF-NEXT:    xsabsdp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
+; FMF-NEXT:    ld 3, .LC4@toc@l(3)
+; FMF-NEXT:    lfsx 2, 0, 3
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB10_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; FMF-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI10_0@toc@l(3)
-; FMF-NEXT:    lfs 3, .LCPI10_1@toc@l(4)
+; FMF-NEXT:    lfs 2, 4(3)
+; FMF-NEXT:    lfs 3, 8(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:    xsmulsp 1, 1, 2
 ; FMF-NEXT:    xsaddsp 0, 0, 3
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB10_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_ieee:
 ; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    addis 3, 2, .LC4@toc@ha
 ; GLOBAL-NEXT:    xsabsdp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI10_2@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI10_2@toc@l(3)
+; GLOBAL-NEXT:    ld 3, .LC4@toc@l(3)
+; GLOBAL-NEXT:    lfsx 2, 0, 3
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB10_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; GLOBAL-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI10_0@toc@l(3)
-; GLOBAL-NEXT:    lfs 3, .LCPI10_1@toc@l(4)
+; GLOBAL-NEXT:    lfs 2, 8(3)
+; GLOBAL-NEXT:    lfs 3, 4(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB10_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call afn ninf float @llvm.sqrt.f32(float %x)

 define float @sqrt_afn_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_afn_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    fcmpu 0, 1, 0
 ; FMF-NEXT:    beq 0, .LBB12_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
-; FMF-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI12_0@toc@l(3)
-; FMF-NEXT:    lfs 3, .LCPI12_1@toc@l(4)
+; FMF-NEXT:    addis 3, 2, .LC5@toc@ha
+; FMF-NEXT:    ld 3, .LC5@toc@l(3)
+; FMF-NEXT:    lfs 2, 4(3)
+; FMF-NEXT:    lfsx 3, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
-; FMF-NEXT:    xsmulsp 1, 1, 2
-; FMF-NEXT:    xsaddsp 0, 0, 3
+; FMF-NEXT:    xsmulsp 1, 1, 3
+; FMF-NEXT:    xsaddsp 0, 0, 2
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB12_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_preserve_sign:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    fcmpu 0, 1, 0
 ; GLOBAL-NEXT:    beq 0, .LBB12_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
-; GLOBAL-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI12_0@toc@l(3)
-; GLOBAL-NEXT:    lfs 3, .LCPI12_1@toc@l(4)
+; GLOBAL-NEXT:    addis 3, 2, .LC5@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC5@toc@l(3)
+; GLOBAL-NEXT:    lfs 2, 4(3)
+; GLOBAL-NEXT:    lfsx 3, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB12_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call afn ninf float @llvm.sqrt.f32(float %x)

 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
 ; GLOBALDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
+; FMF-NEXT:    addis 3, 2, .LC6@toc@ha
 ; FMF-NEXT:    xsabsdp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI14_2@toc@l(3)
+; FMF-NEXT:    ld 3, .LC6@toc@l(3)
+; FMF-NEXT:    lfsx 2, 0, 3
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB14_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; FMF-NEXT:    addis 4, 2, .LCPI14_1@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI14_0@toc@l(3)
-; FMF-NEXT:    lfs 3, .LCPI14_1@toc@l(4)
+; FMF-NEXT:    lfs 2, 8(3)
+; FMF-NEXT:    lfs 3, 4(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB14_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_ieee:
 ; GLOBAL:       # %bb.0:
+; GLOBAL-NEXT:    addis 3, 2, .LC6@toc@ha
 ; GLOBAL-NEXT:    xsabsdp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI14_2@toc@l(3)
+; GLOBAL-NEXT:    ld 3, .LC6@toc@l(3)
+; GLOBAL-NEXT:    lfsx 2, 0, 3
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB14_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; GLOBAL-NEXT:    addis 4, 2, .LCPI14_1@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI14_0@toc@l(3)
-; GLOBAL-NEXT:    lfs 3, .LCPI14_1@toc@l(4)
+; GLOBAL-NEXT:    lfs 2, 8(3)
+; GLOBAL-NEXT:    lfs 3, 4(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB14_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call reassoc afn ninf float @llvm.sqrt.f32(float %x)

 define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_fast_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    fcmpu 0, 1, 0
 ; FMF-NEXT:    beq 0, .LBB15_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; FMF-NEXT:    addis 4, 2, .LCPI15_1@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI15_0@toc@l(3)
-; FMF-NEXT:    lfs 3, .LCPI15_1@toc@l(4)
+; FMF-NEXT:    addis 3, 2, .LC7@toc@ha
+; FMF-NEXT:    ld 3, .LC7@toc@l(3)
+; FMF-NEXT:    lfs 2, 4(3)
+; FMF-NEXT:    lfsx 3, 0, 3
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB15_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_preserve_sign:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    fcmpu 0, 1, 0
 ; GLOBAL-NEXT:    beq 0, .LBB15_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; GLOBAL-NEXT:    addis 4, 2, .LCPI15_1@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI15_0@toc@l(3)
-; GLOBAL-NEXT:    lfs 3, .LCPI15_1@toc@l(4)
+; GLOBAL-NEXT:    addis 3, 2, .LC7@toc@ha
+; GLOBAL-NEXT:    ld 3, .LC7@toc@l(3)
+; GLOBAL-NEXT:    lfs 2, 4(3)
+; GLOBAL-NEXT:    lfsx 3, 0, 3
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB15_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call reassoc ninf afn float @llvm.sqrt.f32(float %x)

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

 ; P8-LABEL: ppcq_to_u32:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -128(r1)
 ; P8-NEXT:    .cfi_def_cfa_offset 128
 ; P8-NEXT:    .cfi_offset lr, 16
 ; P8-NEXT:    .cfi_offset r30, -16
-; P8-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
+; P8-NEXT:    addis r3, r2, .LC0@toc@ha
 ; P8-NEXT:    xxlxor f3, f3, f3
 ; P8-NEXT:    std r30, 112(r1) # 8-byte Folded Spill
-; P8-NEXT:    lfs f0, .LCPI13_0@toc@l(r3)
+; P8-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P8-NEXT:    fcmpo cr0, f2, f3
-; P8-NEXT:    lis r3, -32768
 ; P8-NEXT:    xxlxor f3, f3, f3
+; P8-NEXT:    lfsx f0, 0, r3
+; P8-NEXT:    lis r3, -32768
 ; P8-NEXT:    fcmpo cr1, f1, f0
 ; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, lt
 ; P8-NEXT:    crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
 ; P8-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r30, 0, r3, 4*cr5+lt
 ; P8-NEXT:    bc 12, 4*cr5+lt, .LBB13_2
 ; P8-NEXT:  # %bb.1: # %entry
 ; P8-NEXT:    fmr f3, f0

 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    mflr r0
 ; P9-NEXT:    .cfi_def_cfa_offset 48
 ; P9-NEXT:    .cfi_offset lr, 16
 ; P9-NEXT:    .cfi_offset r30, -16
 ; P9-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; P9-NEXT:    std r0, 16(r1)
 ; P9-NEXT:    stdu r1, -48(r1)
-; P9-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
+; P9-NEXT:    addis r3, r2, .LC0@toc@ha
 ; P9-NEXT:    xxlxor f3, f3, f3
-; P9-NEXT:    lfs f0, .LCPI13_0@toc@l(r3)
+; P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P9-NEXT:    fcmpo cr1, f2, f3
+; P9-NEXT:    xxlxor f3, f3, f3
+; P9-NEXT:    lfs f0, 0(r3)
 ; P9-NEXT:    lis r3, -32768
 ; P9-NEXT:    fcmpo cr0, f1, f0
-; P9-NEXT:    xxlxor f3, f3, f3
 ; P9-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; P9-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P9-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r30, 0, r3, 4*cr5+lt
 ; P9-NEXT:    bc 12, 4*cr5+lt, .LBB13_2
 ; P9-NEXT:  # %bb.1: # %entry
 ; P9-NEXT:    fmr f3, f0
 ; P9-NEXT:  .LBB13_2: # %entry

 ; NOVSX-NEXT:    mfocrf r12, 32
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stw r12, 8(r1)
 ; NOVSX-NEXT:    stdu r1, -48(r1)
 ; NOVSX-NEXT:    .cfi_def_cfa_offset 48
 ; NOVSX-NEXT:    .cfi_offset lr, 16
 ; NOVSX-NEXT:    .cfi_offset cr2, 8
-; NOVSX-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; NOVSX-NEXT:    addis r4, r2, .LCPI13_1@toc@ha
-; NOVSX-NEXT:    lfs f0, .LCPI13_0@toc@l(r3)
-; NOVSX-NEXT:    lfs f4, .LCPI13_1@toc@l(r4)
+; NOVSX-NEXT:    addis r3, r2, .LC0@toc@ha
+; NOVSX-NEXT:    ld r3, .LC0@toc@l(r3)
+; NOVSX-NEXT:    lfs f0, 0(r3)
+; NOVSX-NEXT:    lfs f4, 4(r3)
 ; NOVSX-NEXT:    fcmpo cr0, f1, f0
 ; NOVSX-NEXT:    fcmpo cr1, f2, f4
 ; NOVSX-NEXT:    fmr f3, f4
 ; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, lt, eq
 ; NOVSX-NEXT:    cror 4*cr2+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    bc 12, 4*cr2+lt, .LBB13_2
 ; NOVSX-NEXT:  # %bb.1: # %entry

 ; P9-NEXT:    xxlxor f2, f2, f2
 ; P9-NEXT:    xscvsxddp f1, f0
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: i1_to_ppcq:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
+; NOVSX-NEXT:    addis r3, r2, .LC1@toc@ha
 ; NOVSX-NEXT:    lfiwax f0, 0, r4
-; NOVSX-NEXT:    lfs f2, .LCPI16_0@toc@l(r3)
+; NOVSX-NEXT:    ld r3, .LC1@toc@l(r3)
 ; NOVSX-NEXT:    fcfid f1, f0
+; NOVSX-NEXT:    lfs f2, 0(r3)
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @u1_to_ppcq(i1 zeroext %m) #0 {
 ; P8-LABEL: u1_to_ppcq:

 ; P9-NEXT:    xxlxor f2, f2, f2
 ; P9-NEXT:    xscvsxddp f1, f0
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: u1_to_ppcq:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
+; NOVSX-NEXT:    addis r3, r2, .LC2@toc@ha
 ; NOVSX-NEXT:    lfiwax f0, 0, r4
-; NOVSX-NEXT:    lfs f2, .LCPI17_0@toc@l(r3)
+; NOVSX-NEXT:    ld r3, .LC2@toc@l(r3)
 ; NOVSX-NEXT:    fcfid f1, f0
+; NOVSX-NEXT:    lfs f2, 0(r3)
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret ppc_fp128 %conv
 }
 
 define fp128 @i32_to_q(i32 signext %m) #0 {
 ; P8-LABEL: i32_to_q:

llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll

 define float @fooul(float %X) #0 {
 ; FPCVT-LABEL: fooul:
 ; FPCVT:       # %bb.0: # %entry
 ; FPCVT-NEXT:    friz 1, 1
 ; FPCVT-NEXT:    blr
 ;
 ; PPC64-LABEL: fooul:
 ; PPC64:       # %bb.0: # %entry
-; PPC64-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; PPC64-NEXT:    addis 3, 2, .LC0@toc@ha
 ; PPC64-NEXT:    li 4, 1
-; PPC64-NEXT:    lfs 0, .LCPI2_0@toc@l(3)
+; PPC64-NEXT:    ld 3, .LC0@toc@l(3)
 ; PPC64-NEXT:    sldi 4, 4, 63
+; PPC64-NEXT:    lfs 0, 0(3)
 ; PPC64-NEXT:    fsubs 2, 1, 0
 ; PPC64-NEXT:    fcmpu 0, 1, 0
 ; PPC64-NEXT:    fctidz 2, 2
 ; PPC64-NEXT:    stfd 2, -8(1)
 ; PPC64-NEXT:    fctidz 2, 1
 ; PPC64-NEXT:    stfd 2, -16(1)
 ; PPC64-NEXT:    ld 3, -8(1)
 ; PPC64-NEXT:    ld 5, -16(1)

 define double @fooudl(double %X) #0 {
 ; FPCVT-LABEL: fooudl:
 ; FPCVT:       # %bb.0: # %entry
 ; FPCVT-NEXT:    friz 1, 1
 ; FPCVT-NEXT:    blr
 ;
 ; PPC64-LABEL: fooudl:
 ; PPC64:       # %bb.0: # %entry
-; PPC64-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; PPC64-NEXT:    addis 3, 2, .LC1@toc@ha
 ; PPC64-NEXT:    li 4, 1
-; PPC64-NEXT:    lfs 0, .LCPI3_0@toc@l(3)
+; PPC64-NEXT:    ld 3, .LC1@toc@l(3)
 ; PPC64-NEXT:    sldi 4, 4, 63
+; PPC64-NEXT:    lfs 0, 0(3)
 ; PPC64-NEXT:    fsub 2, 1, 0
 ; PPC64-NEXT:    fcmpu 0, 1, 0
 ; PPC64-NEXT:    fctidz 2, 2
 ; PPC64-NEXT:    stfd 2, -8(1)
 ; PPC64-NEXT:    fctidz 2, 1
 ; PPC64-NEXT:    stfd 2, -16(1)
 ; PPC64-NEXT:    ld 3, -8(1)
 ; PPC64-NEXT:    ld 5, -16(1)
 ; PPC64-NEXT:    xor 3, 3, 4
 ; PPC64-NEXT:    li 4, 1107
 ; PPC64-NEXT:    sldi 4, 4, 52
 ; PPC64-NEXT:    bc 12, 0, .LBB3_1
 ; PPC64-NEXT:    b .LBB3_2
 ; PPC64-NEXT:  .LBB3_1: # %entry
 ; PPC64-NEXT:    addi 3, 5, 0
 ; PPC64-NEXT:  .LBB3_2: # %entry
 ; PPC64-NEXT:    rldicl 5, 3, 32, 32
 ; PPC64-NEXT:    clrldi 3, 3, 32
 ; PPC64-NEXT:    or 4, 5, 4
-; PPC64-NEXT:    addis 5, 2, .LCPI3_1@toc@ha
+; PPC64-NEXT:    addis 5, 2, .LC2@toc@ha
+; PPC64-NEXT:    ld 5, .LC2@toc@l(5)
 ; PPC64-NEXT:    std 4, -24(1)
 ; PPC64-NEXT:    li 4, 1075
 ; PPC64-NEXT:    sldi 4, 4, 52
 ; PPC64-NEXT:    or 3, 3, 4
-; PPC64-NEXT:    lfd 0, .LCPI3_1@toc@l(5)
+; PPC64-NEXT:    lfd 0, 0(5)
 ; PPC64-NEXT:    std 3, -32(1)
 ; PPC64-NEXT:    lfd 1, -24(1)
 ; PPC64-NEXT:    lfd 2, -32(1)
 ; PPC64-NEXT:    fsub 0, 1, 0
 ; PPC64-NEXT:    fadd 1, 2, 0
 ; PPC64-NEXT:    blr
 ;
 ; PWR9-LABEL: fooudl:

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    xxlxor f0, f0, f0
 ; P8-NEXT:    fcmpu cr0, f1, f0
 ; P8-NEXT:    beq cr0, .LBB20_2
 ; P8-NEXT:  # %bb.1:
-; P8-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; P8-NEXT:    lfs f0, .LCPI20_0@toc@l(r3)
+; P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; P8-NEXT:    ld r3, .LC0@toc@l(r3)
+; P8-NEXT:    lfsx f0, 0, r3
 ; P8-NEXT:  .LBB20_2:
 ; P8-NEXT:    fmr f1, f0
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: PR40273:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdphp f0, f1
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    xscvhpdp f0, f0
 ; CHECK-NEXT:    fcmpu cr0, f0, f1
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    lfs f1, .LCPI20_0@toc@l(r3)
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-NEXT:    lfs f1, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: PR40273:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    std r0, 16(r1)
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    clrldi r3, r3, 48

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

; CHECK-P9-BE-NEXT:    blr
   %v2 = load <2 x i64>, <2 x i64>* %vp2
   %v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <2 x i32> <i32 3, i32 2>
   ret <2 x i64> %v3
 }
 
 define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
 ; CHECK-P8-LABEL: load_swap10:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap10:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap10:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap10:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x i32> %v3
 }
 
 define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {
 ; CHECK-P8-LABEL: load_swap11:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-P8-NEXT:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P8-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap11:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap11:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap11:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P9-BE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x i32> %v3
 }
 
 define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){
 ; CHECK-P8-LABEL: load_swap20:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap20:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvh8x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap20:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI4_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap20:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x i16> %v3
 }
 
 define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){
 ; CHECK-P8-LABEL: load_swap21:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-P8-NEXT:    addis r3, r2, .LC3@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P8-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap21:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvh8x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap21:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC3@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap21:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC3@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P9-BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   ret <8 x i16> %v3
 }
 
 define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){
 ; CHECK-P8-LABEL: load_swap30:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC4@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap30:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvb16x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap30:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r4, r2, .LC4@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap30:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-P9-BE-NEXT:    xxbrq v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <16 x i8>, <16 x i8>* %vp1
   %v2 = load <16 x i8>, <16 x i8>* %vp2
   %v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <16 x i8> %v3
 }
 
 define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){
 ; CHECK-P8-LABEL: load_swap31:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
+; CHECK-P8-NEXT:    addis r3, r2, .LC5@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-P8-NEXT:    ld r3, .LC5@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap31:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvb16x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap31:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC5@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap31:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv vs0, 0(r4)
 ; CHECK-P9-BE-NEXT:    xxbrq v2, vs0
; CHECK-P9-BE-NEXT:    blr
   %v2 = load <2 x double>, <2 x double>* %vp2
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> <i32 3, i32 2>
   ret <2 x double> %v3
 }
 
 define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
 ; CHECK-P8-LABEL: load_swap50:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI9_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC6@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI9_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap50:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap50:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI9_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r4, r2, .LC6@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI9_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap50:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %v3
 }
 
 define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {
 ; CHECK-P8-LABEL: load_swap51:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
+; CHECK-P8-NEXT:    addis r3, r2, .LC7@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P8-NEXT:    ld r3, .LC7@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: load_swap51:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    lxvw4x v2, 0, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: load_swap51:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC7@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P8-BE-NEXT:    ld r3, .LC7@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap51:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC5@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P9-BE-NEXT:    ld r3, .LC5@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x float> %v3
 }
; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <2 x i64> %v1, <2 x i64> %v2, <2 x i32> <i32 3, i32 2>
   store <2 x i64> %v3, <2 x i64>* %vp
   ret void
 }
 
 define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
 ; CHECK-P8-LABEL: swap_store10:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI13_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC8@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store10:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store10:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI13_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC8@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store10:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI13_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC6@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC6@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
 ; CHECK-P8-LABEL: swap_store11:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC9@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC9@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store11:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvw4x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store11:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC9@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store11:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC7@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC7@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
 ; CHECK-P8-LABEL: swap_store20:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC10@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC10@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store20:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvh8x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store20:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC10@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC10@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store20:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC8@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC8@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
 ; CHECK-P8-LABEL: swap_store21:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC11@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC11@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store21:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvh8x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store21:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC11@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store21:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC9@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC9@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
 ; CHECK-P8-LABEL: swap_store30:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI17_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC12@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC12@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store30:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvb16x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store30:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI17_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC12@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC12@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store30:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    xxbrq vs0, v2
 ; CHECK-P9-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   store <16 x i8> %v3, <16 x i8>* %vp
   ret void
 }
 
 define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
 ; CHECK-P8-LABEL: swap_store31:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI18_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC13@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC13@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store31:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvb16x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store31:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC13@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC13@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store31:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    xxbrq vs0, v3
; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> <i32 3, i32 2>
   store <2 x double> %v3, <2 x double>* %vp
   ret void
 }
 
 define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
 ; CHECK-P8-LABEL: swap_store50:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI21_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC14@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC14@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store50:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store50:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI21_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC14@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC14@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store50:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI21_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC10@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC10@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }
 
 define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
 ; CHECK-P8-LABEL: swap_store51:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI22_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC15@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC15@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    stvx v2, 0, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: swap_store51:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    stxvw4x v3, 0, r7
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-BE-LABEL: swap_store51:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
-; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI22_0@toc@l
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LC15@toc@ha
+; CHECK-P8-BE-NEXT:    ld r3, .LC15@toc@l(r3)
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store51:
 ; CHECK-P9-BE:       # %bb.0:
-; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
-; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI22_0@toc@l
+; CHECK-P9-BE-NEXT:    addis r3, r2, .LC11@toc@ha
+; CHECK-P9-BE-NEXT:    ld r3, .LC11@toc@l(r3)
 ; CHECK-P9-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }

llvm/test/CodeGen/PowerPC/mcm-12.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
-; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
+; CHECK: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; CHECK: .quad 0x3f4fd4920b498cf0
 ; CHECK-LABEL: test_double_const:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; CHECK: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
+; CHECK: lfd {{[0-9]+}}, 0([[REG2]]) 
+; CHECK: [[VAR]]:
+; CHECK: .tc [[LCPI]][TC],[[LCPI]]
 
-; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; CHECK-VSX: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; CHECK-VSX: .quad 0x3f4fd4920b498cf0
 ; CHECK-VSX-LABEL: test_double_const:
-; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}}) 
+; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; CHECK-VSX: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
+; CHECK-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] 
+; CHECK-VSX: [[VAR]]:
+; CHECK-VSX: .tc [[LCPI]][TC],[[LCPI]]
 
-; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
+; CHECK-P9: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; CHECK-P9: .quad 0x3f4fd4920b498cf0
 ; CHECK-P9-LABEL: test_double_const:
-; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; CHECK-P9: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
+; CHECK-P9: lfd {{[0-9]+}}, 0([[REG2]])
+; CHECK-P9: [[VAR]]:
+; CHECK-P9: .tc [[LCPI]][TC],[[LCPI]]

llvm/test/CodeGen/PowerPC/mcm-4.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
-; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-LABEL: test_double_const:
-; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
+; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; MEDIUM: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: [[VAR]]:
+; MEDIUM: .tc [[LCPI]][TC],[[LCPI]]
 
-; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM-VSX: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-VSX-LABEL: test_double_const:
-; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; MEDIUM-VSX: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
+; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
+; MEDIUM-VSX: [[VAR]]:
+; MEDIUM-VSX: .tc [[LCPI]][TC],[[LCPI]]
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 0x3f4fd4920b498cf0
 ; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE-VSX: .quad 0x3f4fd4920b498cf0
 ; LARGE-VSX-LABEL: test_double_const:
 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
 
-; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM-P9: [[LCPI:[a-z0-9A-Z_.]+]]:
 ; MEDIUM-P9: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-P9-LABEL: test_double_const:
-; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
+; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
+; MEDIUM-P9: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])
+; MEDIUM-P9: [[VAR]]:
+; MEDIUM-P9: .tc [[LCPI]][TC],[[LCPI]]
 
 ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE-P9: .quad 0x3f4fd4920b498cf0
 ; LARGE-P9-LABEL: test_double_const:
 ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])

llvm/test/CodeGen/PowerPC/mcm-obj-2.ll

 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a constant.
 ;
 ; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
-; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
+; CHECK:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]

llvm/test/CodeGen/PowerPC/mcm-obj.ll

 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a constant.
 ;
 ; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
 ;
 ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
 ; accessing a constant.
 ;
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
 
 @ti = common global i32 0, align 4

llvm/test/CodeGen/PowerPC/nofpexcept.ll

define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, i32* %addr1, i64* %addr2) {
   ; CHECK:   [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
   ; CHECK:   MTFSB1 31, implicit-def $rm
   ; CHECK:   MTFSB0 30, implicit-def $rm
   ; CHECK:   %15:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
   ; CHECK:   MTFSFb 1, [[MFFS]], implicit-def $rm
   ; CHECK:   %16:vsfrc = nofpexcept XSCVDPSXWS killed %15, implicit $rm
   ; CHECK:   [[MFVSRWZ2:%[0-9]+]]:gprc = MFVSRWZ killed %16
   ; CHECK:   STW killed [[MFVSRWZ2]], 0, [[COPY1]] :: (volatile store 4 into %ir.addr1)
-  ; CHECK:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
-  ; CHECK:   [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load 4 from constant-pool)
+  ; CHECK:   [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, target-flags(ppc-got) %const.0
+  ; CHECK:   [[LDtocL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocL target-flags(ppc-got) %const.0, killed [[ADDIStocHA8_]] :: (load 8 from got)
+  ; CHECK:   [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 0, killed [[LDtocL]] :: (load 4 from constant-pool)
   ; CHECK:   [[COPY9:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
   ; CHECK:   [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY9]]
   ; CHECK:   [[COPY10:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
   ; CHECK:   [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
   ; CHECK:   [[FCMPOD1:%[0-9]+]]:crrc = FCMPOD [[COPY3]], [[XXLXORdpz]]
   ; CHECK:   [[COPY11:%[0-9]+]]:crbitrc = COPY [[FCMPOD1]].sub_lt
   ; CHECK:   [[CRAND:%[0-9]+]]:crbitrc = CRAND killed [[COPY10]], killed [[COPY11]]
   ; CHECK:   [[COPY12:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, i32* %addr1, i64* %addr2) {
   ; CHECK:   $f4 = COPY [[XXLXORdpz]]
   ; CHECK:   BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
   ; CHECK:   ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
   ; CHECK:   [[COPY14:%[0-9]+]]:f8rc = COPY $f1
   ; CHECK:   [[COPY15:%[0-9]+]]:f8rc = COPY $f2
   ; CHECK:   [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm
   ; CHECK:   MTFSB1 31, implicit-def $rm
   ; CHECK:   MTFSB0 30, implicit-def $rm
-  ; CHECK:   %37:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm
+  ; CHECK:   %38:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm
   ; CHECK:   MTFSFb 1, [[MFFS1]], implicit-def $rm
-  ; CHECK:   %38:vsfrc = nofpexcept XSCVDPSXWS killed %37, implicit $rm
-  ; CHECK:   [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %38
+  ; CHECK:   %39:vsfrc = nofpexcept XSCVDPSXWS killed %38, implicit $rm
+  ; CHECK:   [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %39
   ; CHECK:   [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ3]], killed [[ISEL]]
   ; CHECK:   STW killed [[XOR]], 0, [[COPY1]] :: (volatile store 4 into %ir.addr1)
   ; CHECK:   BLR8 implicit $lr8, implicit $rm
 entry:
   %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.ignore") #0
   store volatile i32 %conv1, i32* %addr1, align 4
   %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %m, metadata !"fpexcept.ignore") #0
   store volatile i32 %conv2, i32* %addr1, align 4

llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll

 define dso_local <2 x double> @testDoubleToDoubleFail() local_unnamed_addr {
 ; CHECK-LABEL: testDoubleToDoubleFail:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI0_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testDoubleToDoubleFail:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret <2 x double> <double 3.423300e+02, double 3.423300e+02>
 }
 
 define dso_local <2 x double> @testFloatDenormToDouble() local_unnamed_addr {
 ; CHECK-LABEL: testFloatDenormToDouble:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI1_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testFloatDenormToDouble:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret <2 x double> <double 0x380B38FB80000000, double 0x380B38FB80000000>
 }
 
 define dso_local <2 x double> @testDoubleToDoubleNaNFail() local_unnamed_addr {
 ; CHECK-LABEL: testDoubleToDoubleNaNFail:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plxv vs34, .LCPI2_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testDoubleToDoubleNaNFail:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-NOPCREL-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-NOPCREL-NEXT:    lxvx vs34, 0, r3
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret <2 x double> <double 0xFFFFFFFFFFFFFFF0, double 0xFFFFFFFFFFFFFFF0>
 }
 
 define dso_local double @testDoubleNonRepresentableScalar() local_unnamed_addr {
 ; CHECK-LABEL: testDoubleNonRepresentableScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfd f1, .LCPI3_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testDoubleNonRepresentableScalar:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfd f1, .LCPI3_0@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC3@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    lfd f1, 0(r3)
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret double 3.423300e+02
 }
 
 define dso_local float @testFloatDenormScalar() local_unnamed_addr {
 ; CHECK-LABEL: testFloatDenormScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfs f1, .LCPI4_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testFloatDenormScalar:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfs f1, .LCPI4_0@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC4@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    lfs f1, 0(r3)
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret float 0x380B38FB80000000
 }
 
 define dso_local double @testFloatDenormToDoubleScalar() local_unnamed_addr {
 ; CHECK-LABEL: testFloatDenormToDoubleScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfs f1, .LCPI5_0@PCREL(0), 1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOPCREL-LABEL: testFloatDenormToDoubleScalar:
 ; CHECK-NOPCREL:       # %bb.0: # %entry
-; CHECK-NOPCREL-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-NOPCREL-NEXT:    lfs f1, .LCPI5_0@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    addis r3, r2, .LC5@toc@ha
+; CHECK-NOPCREL-NEXT:    ld r3, .LC5@toc@l(r3)
+; CHECK-NOPCREL-NEXT:    lfs f1, 0(r3)
 ; CHECK-NOPCREL-NEXT:    blr
-
 entry:
   ret double 0x380B38FB80000000
 }

llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll

 ; CHECK-LE-LABEL: test_vrlq_cost_mult8:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    plxv v3, .LCPI1_0@PCREL(0), 1
 ; CHECK-LE-NEXT:    vrlq v2, v3, v2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vrlq_cost_mult8:
 ; CHECK-BE:       # %bb.0:
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vrlq v2, v3, v2
 ; CHECK-BE-NEXT:    blr
   %shl.i = shl <1 x i128> <i128 16>, %x
   %sub.i = sub <1 x i128> <i128 128>, %x
   %lshr.i = lshr <1 x i128> <i128 16>, %sub.i
   %tmp = or <1 x i128> %shl.i, %lshr.i
   ret <1 x i128> %tmp
 }
 
 define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) {
 ; CHECK-LE-LABEL: test_vrlq_cost_non_mult8:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    plxv v3, .LCPI2_0@PCREL(0), 1
 ; CHECK-LE-NEXT:    vrlq v2, v3, v2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vrlq_cost_non_mult8:
 ; CHECK-BE:       # %bb.0:
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vrlq v2, v3, v2
 ; CHECK-BE-NEXT:    blr
   %shl.i = shl <1 x i128> <i128 4>, %x
   %sub.i = sub <1 x i128> <i128 128>, %x
   %lshr.i = lshr <1 x i128> <i128 4>, %sub.i
   %tmp = or <1 x i128> %shl.i, %lshr.i
   ret <1 x i128> %tmp

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    plxv v5, .LCPI4_0@PCREL(0), 1
 ; CHECK-LE-NEXT:    vperm v3, v4, v3, v5
 ; CHECK-LE-NEXT:    vrlqnm v2, v2, v3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vrlqnm:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v5, 0, r3
 ; CHECK-BE-NEXT:    vperm v3, v3, v4, v5
 ; CHECK-BE-NEXT:    vrlqnm v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast <1 x i128> %b to <16 x i8>
   %1 = bitcast <1 x i128> %c to <16 x i8>
   %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll

 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 2
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC1@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 

 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_0_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_1_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_2_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 13
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_3_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_4_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC6@toc@ha
+; CHECK-NEXT:    ld 3, .LC6@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_5_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 10
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC6@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC6@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_6_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 9
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC7@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC7@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_7_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC8@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC8@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_8_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC7@toc@ha
+; CHECK-NEXT:    ld 3, .LC7@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_9_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC8@toc@ha
+; CHECK-NEXT:    ld 3, .LC8@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 9
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_10_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC9@toc@ha
+; CHECK-NEXT:    ld 3, .LC9@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_11_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC9@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC9@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_12_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC10@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC10@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_13_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC10@toc@ha
+; CHECK-NEXT:    ld 3, .LC10@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 13
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_14_7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-NEXT:    ld 3, .LC11@toc@l(3)
 ; CHECK-NEXT:    lxvx 35, 0, 3
 ; CHECK-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 14
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_15_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
+; CHECK-BE-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-BE-NEXT:    ld 3, .LC11@toc@l(3)
 ; CHECK-BE-NEXT:    lxvx 35, 0, 3
 ; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

 ;
 ; PC64LE9-LABEL: test_fpext_ppc_fp128_f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxlxor 2, 2, 2
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fpext_ppc_fp128_f32:
 ; PC64:       # %bb.0: # %entry
-; PC64-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
-; PC64-NEXT:    lfs 2, .LCPI26_0@toc@l(3)
+; PC64-NEXT:    addis 3, 2, .LC0@toc@ha
+; PC64-NEXT:    ld 3, .LC0@toc@l(3)
+; PC64-NEXT:    lfs 2, 0(3)
 ; PC64-NEXT:    blr
 entry:
   %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128(
                     float %first,
                     metadata !"fpexcept.strict") #1
   ret ppc_fp128 %fpext
 }
 
 define ppc_fp128 @test_fpext_ppc_fp128_f64(double %first) #0 {
 ; PC64LE-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    xxlxor 2, 2, 2
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxlxor 2, 2, 2
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: test_fpext_ppc_fp128_f64:
 ; PC64:       # %bb.0: # %entry
-; PC64-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; PC64-NEXT:    lfs 2, .LCPI27_0@toc@l(3)
+; PC64-NEXT:    addis 3, 2, .LC1@toc@ha
+; PC64-NEXT:    ld 3, .LC1@toc@l(3)
+; PC64-NEXT:    lfs 2, 0(3)
 ; PC64-NEXT:    blr
 entry:
   %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f64.ppcf128(
                     double %first,
                     metadata !"fpexcept.strict") #1
   ret ppc_fp128 %fpext
 }
 

 
 define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
 ; PC64LE-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -48(1)
-; PC64LE-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
+; PC64LE-NEXT:    addis 3, 2, .LC0@toc@ha
 ; PC64LE-NEXT:    xxlxor 3, 3, 3
-; PC64LE-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
+; PC64LE-NEXT:    ld 3, .LC0@toc@l(3)
 ; PC64LE-NEXT:    fcmpo 0, 2, 3
-; PC64LE-NEXT:    lis 3, -32768
 ; PC64LE-NEXT:    xxlxor 3, 3, 3
+; PC64LE-NEXT:    lfsx 0, 0, 3
+; PC64LE-NEXT:    lis 3, -32768
 ; PC64LE-NEXT:    fcmpo 1, 1, 0
 ; PC64LE-NEXT:    crand 20, 6, 0
 ; PC64LE-NEXT:    crandc 21, 4, 6
 ; PC64LE-NEXT:    cror 20, 21, 20
 ; PC64LE-NEXT:    isel 30, 0, 3, 20
 ; PC64LE-NEXT:    bc 12, 20, .LBB31_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
 ; PC64LE-NEXT:    fmr 3, 0

 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 30, -16(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -48(1)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
+; PC64LE9-NEXT:    addis 3, 2, .LC0@toc@ha
 ; PC64LE9-NEXT:    xxlxor 3, 3, 3
-; PC64LE9-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
+; PC64LE9-NEXT:    ld 3, .LC0@toc@l(3)
 ; PC64LE9-NEXT:    fcmpo 1, 2, 3
+; PC64LE9-NEXT:    xxlxor 3, 3, 3
+; PC64LE9-NEXT:    lfs 0, 0(3)
 ; PC64LE9-NEXT:    lis 3, -32768
 ; PC64LE9-NEXT:    fcmpo 0, 1, 0
-; PC64LE9-NEXT:    xxlxor 3, 3, 3
 ; PC64LE9-NEXT:    crand 20, 2, 4
 ; PC64LE9-NEXT:    crandc 21, 0, 2
 ; PC64LE9-NEXT:    cror 20, 21, 20
 ; PC64LE9-NEXT:    isel 30, 0, 3, 20
 ; PC64LE9-NEXT:    bc 12, 20, .LBB31_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
 ; PC64LE9-NEXT:    fmr 3, 0
 ; PC64LE9-NEXT:  .LBB31_2: # %entry

 ;
 ; PC64-LABEL: test_fptoui_ppc_i32_ppc_fp128:
 ; PC64:       # %bb.0: # %entry
 ; PC64-NEXT:    mflr 0
 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    mfcr 12
 ; PC64-NEXT:    stw 12, 8(1)
 ; PC64-NEXT:    stdu 1, -128(1)
-; PC64-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; PC64-NEXT:    lfs 0, .LCPI31_0@toc@l(3)
-; PC64-NEXT:    addis 3, 2, .LCPI31_1@toc@ha
-; PC64-NEXT:    lfs 4, .LCPI31_1@toc@l(3)
+; PC64-NEXT:    addis 3, 2, .LC2@toc@ha
+; PC64-NEXT:    ld 3, .LC2@toc@l(3)
+; PC64-NEXT:    lfs 0, 0(3)
+; PC64-NEXT:    lfs 4, 4(3)
 ; PC64-NEXT:    fcmpo 0, 1, 0
 ; PC64-NEXT:    crandc 21, 0, 2
 ; PC64-NEXT:    fcmpo 1, 2, 4
 ; PC64-NEXT:    crand 20, 2, 4
 ; PC64-NEXT:    cror 8, 21, 20
 ; PC64-NEXT:    fmr 3, 4
 ; PC64-NEXT:    bc 12, 8, .LBB31_2
 ; PC64-NEXT:  # %bb.1: # %entry

 ; PC64-NEXT:    std 29, 120(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 29, 3
 ; PC64-NEXT:    li 3, 0
 ; PC64-NEXT:    stfd 31, 168(1) # 8-byte Folded Spill
 ; PC64-NEXT:    std 30, 128(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 30, 4
 ; PC64-NEXT:    lfs 31, 0(29)
 ; PC64-NEXT:    std 3, 8(4)
-; PC64-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
+; PC64-NEXT:    addis 3, 2, .LC3@toc@ha
+; PC64-NEXT:    ld 3, .LC3@toc@l(3)
 ; PC64-NEXT:    stfd 30, 160(1) # 8-byte Folded Spill
-; PC64-NEXT:    lfs 30, .LCPI32_0@toc@l(3)
 ; PC64-NEXT:    fmr 1, 31
 ; PC64-NEXT:    fmr 3, 31
+; PC64-NEXT:    lfs 30, 0(3)
 ; PC64-NEXT:    stfd 28, 144(1) # 8-byte Folded Spill
 ; PC64-NEXT:    fmr 2, 30
 ; PC64-NEXT:    fmr 4, 30
 ; PC64-NEXT:    stfd 29, 152(1) # 8-byte Folded Spill
 ; PC64-NEXT:    stfd 31, 0(4)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    fmr 3, 1

 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprwa 0, 3
 ; PC64LE9-NEXT:    xxlxor 2, 2, 2
 ; PC64LE9-NEXT:    xscvsxddp 1, 0
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: i32_to_ppcq:
 ; PC64:       # %bb.0: # %entry
+; PC64-NEXT:    addis 4, 2, .LC4@toc@ha
 ; PC64-NEXT:    std 3, -8(1)
-; PC64-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
+; PC64-NEXT:    ld 4, .LC4@toc@l(4)
 ; PC64-NEXT:    lfd 0, -8(1)
-; PC64-NEXT:    lfs 2, .LCPI33_0@toc@l(3)
+; PC64-NEXT:    lfs 2, 0(4)
 ; PC64-NEXT:    fcfid 1, 0
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @i64_to_ppcq(i64 %m) #0 {

 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    xxlxor 2, 2, 2
 ; PC64LE9-NEXT:    xscvuxddp 1, 0
 ; PC64LE9-NEXT:    blr
 ;
 ; PC64-LABEL: u32_to_ppcq:
 ; PC64:       # %bb.0: # %entry
-; PC64-NEXT:    lis 4, 17200
 ; PC64-NEXT:    stw 3, -4(1)
-; PC64-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
-; PC64-NEXT:    stw 4, -8(1)
-; PC64-NEXT:    lfs 0, .LCPI35_0@toc@l(3)
-; PC64-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; PC64-NEXT:    lfd 1, -8(1)
-; PC64-NEXT:    lfs 2, .LCPI35_1@toc@l(3)
-; PC64-NEXT:    fsub 1, 1, 0
+; PC64-NEXT:    lis 3, 17200
+; PC64-NEXT:    addis 4, 2, .LC5@toc@ha
+; PC64-NEXT:    stw 3, -8(1)
+; PC64-NEXT:    ld 3, .LC5@toc@l(4)
+; PC64-NEXT:    lfd 0, -8(1)
+; PC64-NEXT:    lfs 1, 4(3)
+; PC64-NEXT:    lfs 2, 0(3)
+; PC64-NEXT:    fsub 1, 0, 1
 ; PC64-NEXT:    blr
 entry:
   %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
   ret ppc_fp128 %conv
 }
 
 define ppc_fp128 @u64_to_ppcq(i64 %m) #0 {
 ; PC64LE-LABEL: u64_to_ppcq:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    mr 30, 3
 ; PC64LE-NEXT:    bl __floatditf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
+; PC64LE-NEXT:    addis 3, 2, .LC1@toc@ha
 ; PC64LE-NEXT:    xxlxor 4, 4, 4
 ; PC64LE-NEXT:    fmr 30, 1
+; PC64LE-NEXT:    ld 3, .LC1@toc@l(3)
 ; PC64LE-NEXT:    fmr 31, 2
-; PC64LE-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
+; PC64LE-NEXT:    lfsx 3, 0, 3
 ; PC64LE-NEXT:    bl __gcc_qadd
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    cmpdi 30, 0
 ; PC64LE-NEXT:    blt 0, .LBB36_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
 ; PC64LE-NEXT:    fmr 1, 30
 ; PC64LE-NEXT:  .LBB36_2: # %entry
 ; PC64LE-NEXT:    blt 0, .LBB36_4

 ; PC64LE9-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    mr 30, 3
 ; PC64LE9-NEXT:    bl __floatditf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
+; PC64LE9-NEXT:    addis 3, 2, .LC1@toc@ha
 ; PC64LE9-NEXT:    xxlxor 4, 4, 4
 ; PC64LE9-NEXT:    fmr 30, 1
+; PC64LE9-NEXT:    ld 3, .LC1@toc@l(3)
 ; PC64LE9-NEXT:    fmr 31, 2
-; PC64LE9-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
+; PC64LE9-NEXT:    lfs 3, 0(3)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    cmpdi 30, 0
 ; PC64LE9-NEXT:    blt 0, .LBB36_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
 ; PC64LE9-NEXT:    fmr 1, 30
 ; PC64LE9-NEXT:  .LBB36_2: # %entry
 ; PC64LE9-NEXT:    blt 0, .LBB36_4

 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    stdu 1, -144(1)
 ; PC64-NEXT:    std 30, 112(1) # 8-byte Folded Spill
 ; PC64-NEXT:    stfd 30, 128(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 30, 3
 ; PC64-NEXT:    stfd 31, 136(1) # 8-byte Folded Spill
 ; PC64-NEXT:    bl __floatditf
 ; PC64-NEXT:    nop
-; PC64-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
+; PC64-NEXT:    addis 3, 2, .LC6@toc@ha
 ; PC64-NEXT:    fmr 31, 2
-; PC64-NEXT:    lfs 3, .LCPI36_0@toc@l(3)
-; PC64-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
+; PC64-NEXT:    ld 3, .LC6@toc@l(3)
 ; PC64-NEXT:    fmr 30, 1
-; PC64-NEXT:    lfs 4, .LCPI36_1@toc@l(3)
+; PC64-NEXT:    lfs 3, 4(3)
+; PC64-NEXT:    lfs 4, 0(3)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    cmpdi 30, 0
 ; PC64-NEXT:    blt 0, .LBB36_2
 ; PC64-NEXT:  # %bb.1: # %entry
 ; PC64-NEXT:    fmr 1, 30
 ; PC64-NEXT:  .LBB36_2: # %entry
 ; PC64-NEXT:    blt 0, .LBB36_4

 ; PC64LE-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    mr 30, 4
 ; PC64LE-NEXT:    bl __floattitf
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
+; PC64LE-NEXT:    addis 3, 2, .LC2@toc@ha
 ; PC64LE-NEXT:    xxlxor 4, 4, 4
 ; PC64LE-NEXT:    fmr 30, 1
+; PC64LE-NEXT:    ld 3, .LC2@toc@l(3)
 ; PC64LE-NEXT:    fmr 31, 2
-; PC64LE-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
+; PC64LE-NEXT:    lfdx 3, 0, 3
 ; PC64LE-NEXT:    bl __gcc_qadd
 ; PC64LE-NEXT:    nop
 ; PC64LE-NEXT:    cmpdi 30, 0
 ; PC64LE-NEXT:    blt 0, .LBB38_2
 ; PC64LE-NEXT:  # %bb.1: # %entry
 ; PC64LE-NEXT:    fmr 1, 30
 ; PC64LE-NEXT:  .LBB38_2: # %entry
 ; PC64LE-NEXT:    blt 0, .LBB38_4

 ; PC64LE9-NEXT:    std 30, -32(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 30, -16(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    stfd 31, -8(1) # 8-byte Folded Spill
 ; PC64LE9-NEXT:    std 0, 16(1)
 ; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    mr 30, 4
 ; PC64LE9-NEXT:    bl __floattitf
 ; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
+; PC64LE9-NEXT:    addis 3, 2, .LC2@toc@ha
 ; PC64LE9-NEXT:    xxlxor 4, 4, 4
 ; PC64LE9-NEXT:    fmr 30, 1
-; PC64LE9-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
+; PC64LE9-NEXT:    ld 3, .LC2@toc@l(3)
 ; PC64LE9-NEXT:    fmr 31, 2
+; PC64LE9-NEXT:    lfd 3, 0(3)
 ; PC64LE9-NEXT:    bl __gcc_qadd
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    cmpdi 30, 0
 ; PC64LE9-NEXT:    blt 0, .LBB38_2
 ; PC64LE9-NEXT:  # %bb.1: # %entry
 ; PC64LE9-NEXT:    fmr 1, 30
 ; PC64LE9-NEXT:  .LBB38_2: # %entry
 ; PC64LE9-NEXT:    blt 0, .LBB38_4

 ; PC64-NEXT:    std 0, 16(1)
 ; PC64-NEXT:    stdu 1, -144(1)
 ; PC64-NEXT:    std 30, 112(1) # 8-byte Folded Spill
 ; PC64-NEXT:    stfd 30, 128(1) # 8-byte Folded Spill
 ; PC64-NEXT:    mr 30, 3
 ; PC64-NEXT:    stfd 31, 136(1) # 8-byte Folded Spill
 ; PC64-NEXT:    bl __floattitf
 ; PC64-NEXT:    nop
-; PC64-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
+; PC64-NEXT:    addis 3, 2, .LC7@toc@ha
+; PC64-NEXT:    addis 4, 2, .LC8@toc@ha
 ; PC64-NEXT:    fmr 31, 2
-; PC64-NEXT:    lfd 3, .LCPI38_0@toc@l(3)
-; PC64-NEXT:    addis 3, 2, .LCPI38_1@toc@ha
+; PC64-NEXT:    ld 3, .LC7@toc@l(3)
+; PC64-NEXT:    ld 4, .LC8@toc@l(4)
 ; PC64-NEXT:    fmr 30, 1
-; PC64-NEXT:    lfs 4, .LCPI38_1@toc@l(3)
+; PC64-NEXT:    lfd 3, 0(3)
+; PC64-NEXT:    lfs 4, 0(4)
 ; PC64-NEXT:    bl __gcc_qadd
 ; PC64-NEXT:    nop
 ; PC64-NEXT:    cmpdi 30, 0
 ; PC64-NEXT:    blt 0, .LBB38_2
 ; PC64-NEXT:  # %bb.1: # %entry
 ; PC64-NEXT:    fmr 1, 30
 ; PC64-NEXT:  .LBB38_2: # %entry
 ; PC64-NEXT:    blt 0, .LBB38_4

llvm/test/CodeGen/PowerPC/ppcf128-endian.ll

 define void @caller_const() {
 ; CHECK-LABEL: caller_const:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -32(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
-; CHECK-NEXT:    lfs 1, .LCPI2_0@toc@l(3)
-; CHECK-NEXT:    lfs 2, .LCPI2_1@toc@l(4)
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    lfs 1, 0(3)
+; CHECK-NEXT:    lfs 2, 4(3)
 ; CHECK-NEXT:    bl test
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)

llvm/test/CodeGen/PowerPC/pr25080.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
 
 define <8 x i16> @pr25080(<8 x i32> %a) {
 ; LE-LABEL: pr25080:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; LE-NEXT:    addis 3, 2, .LC0@toc@ha
 ; LE-NEXT:    xxlxor 37, 37, 37
-; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; LE-NEXT:    ld 3, .LC0@toc@l(3)
 ; LE-NEXT:    lvx 4, 0, 3
 ; LE-NEXT:    xxland 34, 34, 36
 ; LE-NEXT:    xxland 35, 35, 36
 ; LE-NEXT:    vcmpequw 2, 2, 5
 ; LE-NEXT:    vcmpequw 3, 3, 5
 ; LE-NEXT:    xxswapd 0, 34
 ; LE-NEXT:    mfvsrwz 3, 34
 ; LE-NEXT:    xxsldwi 1, 34, 34, 1

 ; LE-NEXT:    xxsldwi 0, 35, 35, 3
 ; LE-NEXT:    mtvsrd 33, 3
 ; LE-NEXT:    mffprwz 3, 1
 ; LE-NEXT:    mtvsrd 38, 4
 ; LE-NEXT:    mtvsrd 35, 3
 ; LE-NEXT:    mffprwz 3, 0
 ; LE-NEXT:    vmrghh 2, 0, 2
 ; LE-NEXT:    mtvsrd 32, 3
-; LE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; LE-NEXT:    addis 3, 2, .LC1@toc@ha
 ; LE-NEXT:    vmrghh 4, 1, 4
-; LE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; LE-NEXT:    ld 3, .LC1@toc@l(3)
 ; LE-NEXT:    vmrghh 3, 3, 6
 ; LE-NEXT:    vmrghh 5, 0, 5
 ; LE-NEXT:    vmrglw 2, 4, 2
 ; LE-NEXT:    vspltish 4, 15
 ; LE-NEXT:    vmrglw 3, 5, 3
 ; LE-NEXT:    xxmrgld 34, 35, 34
 ; LE-NEXT:    lvx 3, 0, 3
 ; LE-NEXT:    xxlor 34, 34, 35
 ; LE-NEXT:    vslh 2, 2, 4
 ; LE-NEXT:    vsrah 2, 2, 4
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: pr25080:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; BE-NEXT:    addis 3, 2, .LC0@toc@ha
 ; BE-NEXT:    xxlxor 36, 36, 36
-; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; BE-NEXT:    ld 3, .LC0@toc@l(3)
 ; BE-NEXT:    lxvw4x 0, 0, 3
 ; BE-NEXT:    xxland 35, 35, 0
 ; BE-NEXT:    xxland 34, 34, 0
 ; BE-NEXT:    vcmpequw 3, 3, 4
 ; BE-NEXT:    vcmpequw 2, 2, 4
 ; BE-NEXT:    xxswapd 0, 35
 ; BE-NEXT:    mfvsrwz 3, 35
 ; BE-NEXT:    xxsldwi 1, 35, 35, 1

 ; BE-NEXT:    sldi 4, 4, 48
 ; BE-NEXT:    mtvsrd 32, 4
 ; BE-NEXT:    mffprwz 4, 1
 ; BE-NEXT:    sldi 3, 3, 48
 ; BE-NEXT:    mtvsrd 33, 3
 ; BE-NEXT:    sldi 3, 4, 48
 ; BE-NEXT:    vmrghh 2, 2, 4
 ; BE-NEXT:    mtvsrd 36, 3
-; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; BE-NEXT:    addis 3, 2, .LC1@toc@ha
 ; BE-NEXT:    vmrghh 0, 1, 0
-; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; BE-NEXT:    ld 3, .LC1@toc@l(3)
 ; BE-NEXT:    vmrghh 4, 4, 5
 ; BE-NEXT:    lxvw4x 0, 0, 3
 ; BE-NEXT:    vmrghw 2, 2, 3
 ; BE-NEXT:    vmrghw 3, 4, 0
 ; BE-NEXT:    xxmrghd 34, 35, 34
 ; BE-NEXT:    vspltish 3, 15
 ; BE-NEXT:    xxlor 34, 34, 0
 ; BE-NEXT:    vslh 2, 2, 3

llvm/test/CodeGen/PowerPC/pr43976.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
 @a = dso_local local_unnamed_addr global double 0.000000e+00, align 8
 
 define dso_local signext i32 @b() local_unnamed_addr #0 {
 ; CHECK-LABEL: b:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -144(r1)
-; CHECK-NEXT:    addis r3, r2, a@toc@ha
-; CHECK-NEXT:    li r4, 1
-; CHECK-NEXT:    lfd f0, a@toc@l(r3)
-; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    sldi r4, r4, 63
-; CHECK-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    addis r4, r2, a@toc@ha
+; CHECK-NEXT:    li r5, 1
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-NEXT:    lfd f0, a@toc@l(r4)
+; CHECK-NEXT:    sldi r5, r5, 63
+; CHECK-NEXT:    lfs f1, 4(r3)
 ; CHECK-NEXT:    fsub f2, f0, f1
 ; CHECK-NEXT:    fctidz f2, f2
 ; CHECK-NEXT:    stfd f2, 128(r1)
 ; CHECK-NEXT:    fctidz f2, f0
 ; CHECK-NEXT:    stfd f2, 120(r1)
-; CHECK-NEXT:    ld r3, 128(r1)
-; CHECK-NEXT:    ld r5, 120(r1)
+; CHECK-NEXT:    ld r4, 128(r1)
+; CHECK-NEXT:    ld r6, 120(r1)
 ; CHECK-NEXT:    fcmpu cr0, f0, f1
-; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    lfs f1, 0(r3)
+; CHECK-NEXT:    xor r4, r4, r5
 ; CHECK-NEXT:    bc 12, lt, .LBB0_1
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %entry
-; CHECK-NEXT:    addi r3, r5, 0
+; CHECK-NEXT:    addi r4, r6, 0
 ; CHECK-NEXT:  .LBB0_2: # %entry
-; CHECK-NEXT:    std r3, 112(r1)
-; CHECK-NEXT:    addis r3, r2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    std r4, 112(r1)
 ; CHECK-NEXT:    lfd f0, 112(r1)
-; CHECK-NEXT:    lfs f1, .LCPI0_1@toc@l(r3)
 ; CHECK-NEXT:    fcfid f0, f0
 ; CHECK-NEXT:    fmul f0, f0, f1
 ; CHECK-NEXT:    fctiwz f0, f0
 ; CHECK-NEXT:    stfd f0, 136(r1)
 ; CHECK-NEXT:    lwa r3, 140(r1)
 ; CHECK-NEXT:    bl g
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 144

llvm/test/CodeGen/PowerPC/pr45628.ll

entry:
   %shr = lshr <1 x i128> %num, <i128 100>
   %or = or <1 x i128> %shl, %shr
   ret <1 x i128> %or
 }
 
 define <1 x i128> @NO_rotl(<1 x i128> %num) {
 ; P9-VSX-LABEL: NO_rotl:
 ; P9-VSX:       # %bb.0: # %entry
-; P9-VSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
-; P9-VSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
+; P9-VSX-NEXT:    addis r3, r2, .LC0@toc@ha
+; P9-VSX-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P9-VSX-NEXT:    lxvx v3, 0, r3
-; P9-VSX-NEXT:    addis r3, r2, .LCPI8_1@toc@ha
-; P9-VSX-NEXT:    addi r3, r3, .LCPI8_1@toc@l
 ; P9-VSX-NEXT:    vslo v4, v2, v3
 ; P9-VSX-NEXT:    vspltb v3, v3, 15
 ; P9-VSX-NEXT:    vsl v3, v4, v3
-; P9-VSX-NEXT:    lxvx v4, 0, r3
+; P9-VSX-NEXT:    lxv v4, 16(r3)
 ; P9-VSX-NEXT:    vsro v2, v2, v4
 ; P9-VSX-NEXT:    vspltb v4, v4, 15
 ; P9-VSX-NEXT:    vsr v2, v2, v4
 ; P9-VSX-NEXT:    xxlor v2, v3, v2
 ; P9-VSX-NEXT:    blr
 ;
 ; P9-NOVSX-LABEL: NO_rotl:
 ; P9-NOVSX:       # %bb.0: # %entry
-; P9-NOVSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
-; P9-NOVSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
+; P9-NOVSX-NEXT:    addis r3, r2, .LC0@toc@ha
+; P9-NOVSX-NEXT:    li r4, 16
+; P9-NOVSX-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P9-NOVSX-NEXT:    lvx v3, 0, r3
-; P9-NOVSX-NEXT:    addis r3, r2, .LCPI8_1@toc@ha
-; P9-NOVSX-NEXT:    addi r3, r3, .LCPI8_1@toc@l
 ; P9-NOVSX-NEXT:    vslo v4, v2, v3
 ; P9-NOVSX-NEXT:    vspltb v3, v3, 15
 ; P9-NOVSX-NEXT:    vsl v3, v4, v3
-; P9-NOVSX-NEXT:    lvx v4, 0, r3
+; P9-NOVSX-NEXT:    lvx v4, r3, r4
 ; P9-NOVSX-NEXT:    vsro v2, v2, v4
 ; P9-NOVSX-NEXT:    vspltb v4, v4, 15
 ; P9-NOVSX-NEXT:    vsr v2, v2, v4
 ; P9-NOVSX-NEXT:    vor v2, v3, v2
 ; P9-NOVSX-NEXT:    blr
 ;
 ; P8-VSX-LABEL: NO_rotl:
 ; P8-VSX:       # %bb.0: # %entry

 ; P8-VSX-NEXT:    mtfprd f3, r4
 ; P8-VSX-NEXT:    xxmrghd v2, vs2, vs1
 ; P8-VSX-NEXT:    xxmrghd v3, vs0, vs3
 ; P8-VSX-NEXT:    xxlor v2, v2, v3
 ; P8-VSX-NEXT:    blr
 ;
 ; P8-NOVSX-LABEL: NO_rotl:
 ; P8-NOVSX:       # %bb.0: # %entry
-; P8-NOVSX-NEXT:    addis r3, r2, .LCPI8_0@toc@ha
-; P8-NOVSX-NEXT:    addis r4, r2, .LCPI8_1@toc@ha
-; P8-NOVSX-NEXT:    addi r3, r3, .LCPI8_0@toc@l
+; P8-NOVSX-NEXT:    addis r3, r2, .LC0@toc@ha
+; P8-NOVSX-NEXT:    li r4, 16
+; P8-NOVSX-NEXT:    ld r3, .LC0@toc@l(r3)
 ; P8-NOVSX-NEXT:    lvx v3, 0, r3
-; P8-NOVSX-NEXT:    addi r3, r4, .LCPI8_1@toc@l
-; P8-NOVSX-NEXT:    lvx v4, 0, r3
+; P8-NOVSX-NEXT:    lvx v4, r3, r4
 ; P8-NOVSX-NEXT:    vslo v5, v2, v3
 ; P8-NOVSX-NEXT:    vspltb v3, v3, 15
 ; P8-NOVSX-NEXT:    vsro v2, v2, v4
 ; P8-NOVSX-NEXT:    vspltb v4, v4, 15
 ; P8-NOVSX-NEXT:    vsl v3, v5, v3
 ; P8-NOVSX-NEXT:    vsr v2, v2, v4
 ; P8-NOVSX-NEXT:    vor v2, v3, v2
 ; P8-NOVSX-NEXT:    blr

llvm/test/CodeGen/PowerPC/pr45709.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_6
 ; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:  .LBB0_1: # %.preheader
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    b .LBB0_3
 ; CHECK-NEXT:  .LBB0_3:
-; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lvx v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    vxor v3, v3, v3
 ; CHECK-NEXT:    addi r3, r1, -48
 ; CHECK-NEXT:    stvx v3, 0, r3
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    stvx v2, 0, r3
 ; CHECK-NEXT:    lwz r3, -48(r1)

llvm/test/CodeGen/PowerPC/pr47660.ll

 ; CHECK-LE-NEXT:    xsmuldp f0, f0, f1
 ; CHECK-LE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-LE-NEXT:    mffprwz r3, f0
 ; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: _Z1f1c:
 ; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    clrldi r3, r3, 56
+; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    std r3, -16(r1)
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    lfd f0, -16(r1)
-; CHECK-BE-NEXT:    lfs f1, .LCPI0_0@toc@l(r3)
+; CHECK-BE-NEXT:    lfs f1, 0(r4)
 ; CHECK-BE-NEXT:    fcfid f0, f0
 ; CHECK-BE-NEXT:    fmul f0, f0, f1
 ; CHECK-BE-NEXT:    fctiwz f0, f0
 ; CHECK-BE-NEXT:    stfd f0, -8(r1)
 ; CHECK-BE-NEXT:    lwz r3, -4(r1)
 ; CHECK-BE-NEXT:    clrldi r3, r3, 32
 ; CHECK-BE-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/pr47891.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 %struct.poly2 = type { [11 x i64] }
 
 ; Function Attrs: nofree norecurse nounwind
 define dso_local void @poly2_lshift1(%struct.poly2* nocapture %p) local_unnamed_addr #0 {
 ; CHECK-LABEL: poly2_lshift1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r4, 72
-; CHECK-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addis r6, r2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    ld r7, 64(r3)
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r6, 64(r3)
+; CHECK-NEXT:    li r7, 16
 ; CHECK-NEXT:    ld r8, 16(r3)
 ; CHECK-NEXT:    ld r10, 24(r3)
 ; CHECK-NEXT:    ld r11, 32(r3)
 ; CHECK-NEXT:    lxvd2x vs0, r3, r4
-; CHECK-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; CHECK-NEXT:    addi r6, r6, .LCPI0_1@toc@l
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-NEXT:    ld r12, 56(r3)
-; CHECK-NEXT:    lxvd2x vs1, 0, r5
-; CHECK-NEXT:    mtfprd f2, r7
-; CHECK-NEXT:    ld r5, 0(r3)
+; CHECK-NEXT:    mtfprd f1, r6
 ; CHECK-NEXT:    xxswapd v2, vs0
-; CHECK-NEXT:    lxvd2x vs0, 0, r6
-; CHECK-NEXT:    ld r6, 8(r3)
+; CHECK-NEXT:    lxvd2x vs0, 0, r5
+; CHECK-NEXT:    lxvd2x vs2, r5, r7
+; CHECK-NEXT:    ld r5, 0(r3)
+; CHECK-NEXT:    ld r7, 8(r3)
 ; CHECK-NEXT:    rotldi r9, r5, 1
 ; CHECK-NEXT:    sldi r5, r5, 1
-; CHECK-NEXT:    xxswapd v3, vs1
+; CHECK-NEXT:    xxpermdi v3, v2, vs1, 2
+; CHECK-NEXT:    xxswapd v4, vs0
+; CHECK-NEXT:    rldimi r9, r7, 1, 0
+; CHECK-NEXT:    rotldi r7, r7, 1
 ; CHECK-NEXT:    std r5, 0(r3)
-; CHECK-NEXT:    rotldi r5, r10, 1
-; CHECK-NEXT:    rldimi r9, r6, 1, 0
-; CHECK-NEXT:    rotldi r6, r6, 1
-; CHECK-NEXT:    xxpermdi v4, v2, vs2, 2
-; CHECK-NEXT:    xxswapd v5, vs0
-; CHECK-NEXT:    rldimi r6, r8, 1, 0
+; CHECK-NEXT:    xxswapd v5, vs2
+; CHECK-NEXT:    rldimi r7, r8, 1, 0
 ; CHECK-NEXT:    rotldi r8, r8, 1
 ; CHECK-NEXT:    std r9, 8(r3)
 ; CHECK-NEXT:    ld r9, 40(r3)
+; CHECK-NEXT:    rotldi r5, r10, 1
 ; CHECK-NEXT:    rldimi r8, r10, 1, 0
+; CHECK-NEXT:    std r7, 16(r3)
+; CHECK-NEXT:    vsrd v3, v3, v4
 ; CHECK-NEXT:    rldimi r5, r11, 1, 0
-; CHECK-NEXT:    std r6, 16(r3)
 ; CHECK-NEXT:    rotldi r10, r11, 1
 ; CHECK-NEXT:    ld r11, 48(r3)
-; CHECK-NEXT:    std r5, 32(r3)
-; CHECK-NEXT:    rotldi r6, r12, 1
-; CHECK-NEXT:    vsrd v3, v4, v3
-; CHECK-NEXT:    rldimi r10, r9, 1, 0
-; CHECK-NEXT:    rotldi r9, r9, 1
 ; CHECK-NEXT:    std r8, 24(r3)
 ; CHECK-NEXT:    vsld v2, v2, v5
+; CHECK-NEXT:    rldimi r10, r9, 1, 0
+; CHECK-NEXT:    rotldi r9, r9, 1
+; CHECK-NEXT:    std r5, 32(r3)
 ; CHECK-NEXT:    rotldi r5, r11, 1
-; CHECK-NEXT:    rldimi r9, r11, 1, 0
+; CHECK-NEXT:    rotldi r7, r12, 1
 ; CHECK-NEXT:    std r10, 40(r3)
+; CHECK-NEXT:    xxlor vs0, v2, v3
+; CHECK-NEXT:    rldimi r9, r11, 1, 0
 ; CHECK-NEXT:    rldimi r5, r12, 1, 0
-; CHECK-NEXT:    rldimi r6, r7, 1, 0
+; CHECK-NEXT:    rldimi r7, r6, 1, 0
 ; CHECK-NEXT:    std r9, 48(r3)
-; CHECK-NEXT:    xxlor vs0, v2, v3
 ; CHECK-NEXT:    std r5, 56(r3)
-; CHECK-NEXT:    std r6, 64(r3)
 ; CHECK-NEXT:    xxswapd vs0, vs0
+; CHECK-NEXT:    std r7, 64(r3)
 ; CHECK-NEXT:    stxvd2x vs0, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds %struct.poly2, %struct.poly2* %p, i64 0, i32 0, i64 0
   %0 = load i64, i64* %arrayidx, align 8
   %shl = shl i64 %0, 1
   store i64 %shl, i64* %arrayidx, align 8
   %arrayidx.1 = getelementptr inbounds %struct.poly2, %struct.poly2* %p, i64 0, i32 0, i64 1

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     < %s | FileCheck %s
 
 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     < %s | FileCheck %s --check-prefix=P9BE
 
 ; Function Attrs: norecurse nounwind readonly
 define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
 ; CHECK-LABEL: test_pre_inc_disable_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxsd v5, 0(r5)
-; CHECK-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xxlxor v3, v3, v3
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; CHECK-NEXT:    lxvx v2, 0, r5
-; CHECK-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    addi r5, r5, .LCPI0_1@toc@l
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    lxv v2, 16(r5)
 ; CHECK-NEXT:    lxvx v4, 0, r5
 ; CHECK-NEXT:    li r5, 4
-; CHECK-NEXT:    vperm v0, v3, v5, v2
 ; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    vperm v0, v3, v5, v2
 ; CHECK-NEXT:    vperm v1, v3, v5, v4
 ; CHECK-NEXT:    xvnegsp v5, v0
 ; CHECK-NEXT:    xvnegsp v0, v1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lxsd v1, 0(r3)
 ; CHECK-NEXT:    add r7, r3, r4

 ; CHECK-NEXT:    bdnz .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %for.cond.cleanup
 ; CHECK-NEXT:    extsw r3, r6
 ; CHECK-NEXT:    blr
 ;
 ; P9BE-LABEL: test_pre_inc_disable_1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r5)
-; P9BE-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
+; P9BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; P9BE-NEXT:    xxlxor v3, v3, v3
 ; P9BE-NEXT:    li r6, 0
-; P9BE-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxvx v2, 0, r5
-; P9BE-NEXT:    addis r5, r2, .LCPI0_1@toc@ha
+; P9BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; P9BE-NEXT:    xxlor v5, vs0, vs0
-; P9BE-NEXT:    addi r5, r5, .LCPI0_1@toc@l
-; P9BE-NEXT:    lxvx v4, 0, r5
+; P9BE-NEXT:    lxvx v2, 0, r5
+; P9BE-NEXT:    lxv v4, 16(r5)
 ; P9BE-NEXT:    li r5, 4
-; P9BE-NEXT:    vperm v0, v3, v5, v2
 ; P9BE-NEXT:    mtctr r5
 ; P9BE-NEXT:    li r5, 0
+; P9BE-NEXT:    vperm v0, v3, v5, v2
 ; P9BE-NEXT:    vperm v1, v3, v5, v4
 ; P9BE-NEXT:    xvnegsp v5, v0
 ; P9BE-NEXT:    xvnegsp v0, v1
 ; P9BE-NEXT:    .p2align 4
 ; P9BE-NEXT:  .LBB0_1: # %for.cond1.preheader
 ; P9BE-NEXT:    #
 ; P9BE-NEXT:    lfd f0, 0(r3)
 ; P9BE-NEXT:    add r7, r3, r4
for.cond.cleanup:                                 ; preds = %for.cond1.preheader
   ret i32 %op.extra.1
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
 ; CHECK-LABEL: test_pre_inc_disable_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxsd v2, 0(r3)
-; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-NEXT:    addis r3, r2, .LC1@toc@ha
 ; CHECK-NEXT:    lxsd v1, 0(r4)
 ; CHECK-NEXT:    xxlxor v3, v3, v3
-; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-NEXT:    lxvx v4, 0, r3
-; CHECK-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI1_1@toc@l
-; CHECK-NEXT:    lxvx v0, 0, r3
+; CHECK-NEXT:    lxv v0, 16(r3)
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v5, v3, v2, v4
 ; CHECK-NEXT:    vperm v2, v3, v2, v0
 ; CHECK-NEXT:    vperm v0, v3, v1, v0
 ; CHECK-NEXT:    vperm v3, v3, v1, v4
 ; CHECK-NEXT:    vabsduw v2, v2, v0
 ; CHECK-NEXT:    vabsduw v3, v5, v3
 ; CHECK-NEXT:    vadduwm v2, v3, v2
 ; CHECK-NEXT:    xxswapd v3, v2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; P9BE-LABEL: test_pre_inc_disable_2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfd f0, 0(r3)
-; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; P9BE-NEXT:    addis r3, r2, .LC1@toc@ha
 ; P9BE-NEXT:    xxlxor v3, v3, v3
-; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxvx v4, 0, r3
-; P9BE-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; P9BE-NEXT:    addi r3, r3, .LCPI1_1@toc@l
+; P9BE-NEXT:    ld r3, .LC1@toc@l(r3)
 ; P9BE-NEXT:    xxlor v2, vs0, vs0
 ; P9BE-NEXT:    lfd f0, 0(r4)
+; P9BE-NEXT:    lxv v4, 16(r3)
 ; P9BE-NEXT:    lxvx v0, 0, r3
-; P9BE-NEXT:    xxlor v1, vs0, vs0
 ; P9BE-NEXT:    li r3, 0
+; P9BE-NEXT:    xxlor v1, vs0, vs0
 ; P9BE-NEXT:    vperm v5, v3, v2, v4
 ; P9BE-NEXT:    vperm v2, v3, v2, v0
 ; P9BE-NEXT:    vperm v0, v3, v1, v0
 ; P9BE-NEXT:    vperm v3, v3, v1, v4
 ; P9BE-NEXT:    vabsduw v2, v2, v0
 ; P9BE-NEXT:    vabsduw v3, v5, v3
 ; P9BE-NEXT:    vadduwm v2, v3, v2
 ; P9BE-NEXT:    xxswapd v3, v2

 ;  return i_sum;
 ;}
 
 define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
 ; CHECK-LABEL: test32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r5, r3, r4
 ; CHECK-NEXT:    lxsiwzx v2, r3, r4
-; CHECK-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-NEXT:    addis r3, r2, .LC2@toc@ha
 ; CHECK-NEXT:    xxlxor v3, v3, v3
-; CHECK-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 4
 ; CHECK-NEXT:    lxsiwzx v5, r5, r3
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-NEXT:    vperm v3, v5, v3, v4
 ; CHECK-NEXT:    vspltisw v4, 8
 ; CHECK-NEXT:    vnegw v3, v3
 ; CHECK-NEXT:    vadduwm v4, v4, v4
 ; CHECK-NEXT:    vslw v3, v3, v4
 ; CHECK-NEXT:    vsubuwm v2, v3, v2
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    stxvx vs0, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; P9BE-LABEL: test32:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add r5, r3, r4
 ; P9BE-NEXT:    lfiwzx f0, r3, r4
-; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P9BE-NEXT:    addis r3, r2, .LC2@toc@ha
 ; P9BE-NEXT:    xxlxor v3, v3, v3
+; P9BE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; P9BE-NEXT:    xxsldwi v2, f0, f0, 1
-; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; P9BE-NEXT:    lxvx v4, 0, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    lfiwzx f0, r5, r3
 ; P9BE-NEXT:    vperm v2, v3, v2, v4
 ; P9BE-NEXT:    xxsldwi v5, f0, f0, 1
 ; P9BE-NEXT:    vperm v3, v3, v5, v4
 ; P9BE-NEXT:    vspltisw v4, 8
 ; P9BE-NEXT:    vnegw v3, v3

 
 define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sldi r4, r4, 1
 ; CHECK-NEXT:    li r7, 16
 ; CHECK-NEXT:    add r6, r3, r4
 ; CHECK-NEXT:    lxsihzx v4, r3, r4
-; CHECK-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-NEXT:    addis r3, r2, .LC3@toc@ha
 ; CHECK-NEXT:    lxsihzx v2, r6, r7
 ; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-NEXT:    mtvsrd v3, r6
 ; CHECK-NEXT:    vsplth v4, v4, 3
 ; CHECK-NEXT:    vsplth v2, v2, 3
 ; CHECK-NEXT:    vmrghh v4, v3, v4
 ; CHECK-NEXT:    vmrghh v2, v3, v2
 ; CHECK-NEXT:    vsplth v3, v3, 3
 ; CHECK-NEXT:    vmrglw v3, v4, v3
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-NEXT:    cmpw r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test16:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 1
 ; P9BE-NEXT:    li r7, 16
 ; P9BE-NEXT:    add r6, r3, r4
 ; P9BE-NEXT:    lxsihzx v4, r3, r4
-; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; P9BE-NEXT:    addis r3, r2, .LC3@toc@ha
 ; P9BE-NEXT:    lxsihzx v2, r6, r7
 ; P9BE-NEXT:    li r6, 0
-; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; P9BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; P9BE-NEXT:    sldi r6, r6, 48
 ; P9BE-NEXT:    vsplth v4, v4, 3
 ; P9BE-NEXT:    mtvsrd v3, r6
 ; P9BE-NEXT:    vsplth v2, v2, 3
 ; P9BE-NEXT:    vmrghh v4, v3, v4
 ; P9BE-NEXT:    vmrghh v2, v3, v2
 ; P9BE-NEXT:    vsplth v3, v3, 0
 ; P9BE-NEXT:    vmrghw v3, v3, v4

 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    add r6, r3, r4
 ; CHECK-NEXT:    lxsibzx v2, r3, r4
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    mtvsrd v3, r3
 ; CHECK-NEXT:    li r3, 8
 ; CHECK-NEXT:    lxsibzx v5, r6, r3
+; CHECK-NEXT:    addis r3, r2, .LC4@toc@ha
 ; CHECK-NEXT:    vspltb v4, v3, 7
-; CHECK-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-NEXT:    vspltb v2, v2, 7
-; CHECK-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-NEXT:    vmrghb v2, v3, v2
 ; CHECK-NEXT:    vspltb v5, v5, 7
 ; CHECK-NEXT:    vmrglh v2, v2, v4
 ; CHECK-NEXT:    vmrghb v3, v3, v5
 ; CHECK-NEXT:    vmrglw v2, v2, v4
 ; CHECK-NEXT:    vmrglh v3, v3, v4
 ; CHECK-NEXT:    vmrglw v3, v4, v3
 ; CHECK-NEXT:    lxvx v4, 0, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NEXT:    xxspltw v3, v2, 2
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-NEXT:    cmpw r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test8:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add r6, r3, r4
 ; P9BE-NEXT:    li r7, 8
 ; P9BE-NEXT:    lxsibzx v4, r3, r4
-; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; P9BE-NEXT:    addis r3, r2, .LC4@toc@ha
 ; P9BE-NEXT:    lxsibzx v2, r6, r7
 ; P9BE-NEXT:    li r6, 0
-; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; P9BE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; P9BE-NEXT:    sldi r6, r6, 56
 ; P9BE-NEXT:    vspltb v4, v4, 7
 ; P9BE-NEXT:    mtvsrd v3, r6
 ; P9BE-NEXT:    vspltb v2, v2, 7
 ; P9BE-NEXT:    vmrghb v4, v3, v4
 ; P9BE-NEXT:    vmrghb v2, v3, v2
 ; P9BE-NEXT:    vspltb v3, v3, 0
 ; P9BE-NEXT:    vmrghh v4, v4, v3

llvm/test/CodeGen/PowerPC/recipest.ll

 declare fp128 @llvm.sqrt.f128(fp128)
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
 
 define double @foo_fmf(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrte 0, 2
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
-; CHECK-P7-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI0_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P7-NEXT:    lfs 4, 4(3)
+; CHECK-P7-NEXT:    lfs 5, 0(3)
 ; CHECK-P7-NEXT:    fmul 3, 2, 0
 ; CHECK-P7-NEXT:    fmadd 3, 3, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 3
 ; CHECK-P7-NEXT:    fmul 2, 2, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-P8-NEXT:    lfs 5, .LCPI0_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 6, 4
+; CHECK-P8-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P8-NEXT:    lfs 4, 4(3)
+; CHECK-P8-NEXT:    lfsx 5, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 3, 2, 0
+; CHECK-P8-NEXT:    fmr 6, 4
 ; CHECK-P8-NEXT:    xsmaddadp 6, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 6
 ; CHECK-P8-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P8-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo_fmf:
 ; CHECK-P9:       # %bb.0:
+; CHECK-P9-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 2
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P9-NEXT:    lfs 4, 4(3)
 ; CHECK-P9-NEXT:    xsmuldp 3, 2, 0
 ; CHECK-P9-NEXT:    fmr 5, 4
 ; CHECK-P9-NEXT:    xsmaddadp 5, 3, 0
-; CHECK-P9-NEXT:    lfs 3, .LCPI0_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 0(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
; CHECK-P9-NEXT:    blr
   %r = fdiv arcp reassoc double %a, %x
   ret double %r
 }
 
 define double @foof_fmf(double %a, float %b) nounwind {
 ; CHECK-P7-LABEL: foof_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 2
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI3_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 4(3)
+; CHECK-P7-NEXT:    lfs 4, 0(3)
 ; CHECK-P7-NEXT:    fmuls 2, 2, 0
 ; CHECK-P7-NEXT:    fmadds 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmuls 0, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foof_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
-; CHECK-P8-NEXT:    lfs 4, .LCPI3_1@toc@l(4)
+; CHECK-P8-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-P8-NEXT:    lfs 3, 4(3)
+; CHECK-P8-NEXT:    lfsx 4, 0, 3
 ; CHECK-P8-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P8-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foof_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 4(3)
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI3_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, 0(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
   %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
   %y = fpext float %x to double
   %r = fdiv reassoc arcp double %a, %y
   ret double %r
; CHECK-P9-NEXT:    blr
   %r = fdiv double %a, %y
   ret double %r
 }
 
 define float @food_fmf(float %a, double %b) nounwind {
 ; CHECK-P7-LABEL: food_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrte 0, 2
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI5_1@toc@ha
-; CHECK-P7-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI5_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-P7-NEXT:    lfs 4, 4(3)
+; CHECK-P7-NEXT:    lfs 5, 0(3)
 ; CHECK-P7-NEXT:    fmul 3, 2, 0
 ; CHECK-P7-NEXT:    fmadd 3, 3, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 3
 ; CHECK-P7-NEXT:    fmul 2, 2, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    frsp 0, 0
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: food_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-P8-NEXT:    lfs 5, .LCPI5_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 6, 4
+; CHECK-P8-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-P8-NEXT:    lfs 4, 4(3)
+; CHECK-P8-NEXT:    lfsx 5, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 3, 2, 0
+; CHECK-P8-NEXT:    fmr 6, 4
 ; CHECK-P8-NEXT:    xsmaddadp 6, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 6
 ; CHECK-P8-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P8-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsrsp 0, 0
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: food_fmf:
 ; CHECK-P9:       # %bb.0:
+; CHECK-P9-NEXT:    addis 3, 2, .LC2@toc@ha
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 2
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-P9-NEXT:    lfs 4, 4(3)
 ; CHECK-P9-NEXT:    xsmuldp 3, 2, 0
 ; CHECK-P9-NEXT:    fmr 5, 4
 ; CHECK-P9-NEXT:    xsmaddadp 5, 3, 0
-; CHECK-P9-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 0(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsrsp 0, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
; CHECK-P9-NEXT:    blr
   %r = fdiv float %a, %y
   ret float %r
 }
 
 define float @goo_fmf(float %a, float %b) nounwind {
 ; CHECK-P7-LABEL: goo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 2
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI7_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI7_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 4(3)
+; CHECK-P7-NEXT:    lfs 4, 0(3)
 ; CHECK-P7-NEXT:    fmuls 2, 2, 0
 ; CHECK-P7-NEXT:    fmadds 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmuls 0, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: goo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI7_1@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
-; CHECK-P8-NEXT:    lfs 4, .LCPI7_1@toc@l(4)
+; CHECK-P8-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-P8-NEXT:    lfs 3, 4(3)
+; CHECK-P8-NEXT:    lfsx 4, 0, 3
 ; CHECK-P8-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P8-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: goo_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 4(3)
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI7_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, 0(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
   %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
   %r = fdiv reassoc arcp float %a, %x
   ret float %r
 }
; CHECK-P9-NEXT:    blr
   %r = fdiv reassoc arcp float %a, %x
   ret float %r
 }
 
 define float @rsqrt_fmul_fmf(float %a, float %b, float %c) {
 ; CHECK-P7-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    frsqrtes 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
-; CHECK-P7-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 5, .LCPI10_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-P7-NEXT:    lfs 4, 4(3)
+; CHECK-P7-NEXT:    lfs 5, 0(3)
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    fmadds 1, 1, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 5
 ; CHECK-P7-NEXT:    fmuls 0, 0, 1
 ; CHECK-P7-NEXT:    fres 1, 2
 ; CHECK-P7-NEXT:    fmuls 4, 0, 1
 ; CHECK-P7-NEXT:    fnmsubs 0, 2, 4, 0
 ; CHECK-P7-NEXT:    fmadds 0, 1, 0, 4
 ; CHECK-P7-NEXT:    fmuls 1, 3, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI10_1@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P8-NEXT:    lfs 5, .LCPI10_1@toc@l(4)
+; CHECK-P8-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-P8-NEXT:    lfs 4, 4(3)
+; CHECK-P8-NEXT:    lfsx 5, 0, 3
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 5
 ; CHECK-P8-NEXT:    xsresp 1, 2
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P8-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P8-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 1
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI10_1@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
+; CHECK-P9-NEXT:    lfs 4, 4(3)
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
-; CHECK-P9-NEXT:    lfs 1, .LCPI10_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 1, 0(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 1
 ; CHECK-P9-NEXT:    xsresp 1, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P9-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P9-NEXT:    blr
; CHECK-P9-NEXT:    blr
   %z = fdiv float %c, %y
   ret float %z
 }
 
 define <4 x float> @hoo_fmf(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 4, -1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
+; CHECK-P7-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-P7-NEXT:    li 4, 16
 ; CHECK-P7-NEXT:    vrsqrtefp 5, 3
-; CHECK-P7-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; CHECK-P7-NEXT:    lvx 0, 0, 3
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI12_1@toc@ha
-; CHECK-P7-NEXT:    addi 3, 3, .LCPI12_1@toc@l
+; CHECK-P7-NEXT:    ld 3, .LC5@toc@l(3)
+; CHECK-P7-NEXT:    lvx 0, 3, 4
 ; CHECK-P7-NEXT:    lvx 1, 0, 3
 ; CHECK-P7-NEXT:    vslw 4, 4, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 3, 5, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 3, 5, 0
 ; CHECK-P7-NEXT:    vmaddfp 5, 5, 1, 4
 ; CHECK-P7-NEXT:    vmaddfp 3, 5, 3, 4
 ; CHECK-P7-NEXT:    vmaddfp 2, 2, 3, 4
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 35
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI12_1@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; CHECK-P8-NEXT:    xvmulsp 1, 35, 0
-; CHECK-P8-NEXT:    lvx 3, 0, 3
-; CHECK-P8-NEXT:    addi 3, 4, .LCPI12_1@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-P8-NEXT:    li 4, 16
+; CHECK-P8-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-P8-NEXT:    lvx 4, 0, 3
+; CHECK-P8-NEXT:    xvmulsp 1, 35, 0
+; CHECK-P8-NEXT:    lvx 3, 3, 4
 ; CHECK-P8-NEXT:    xvmaddasp 35, 1, 0
 ; CHECK-P8-NEXT:    xvmulsp 0, 0, 36
 ; CHECK-P8-NEXT:    xvmulsp 0, 0, 35
 ; CHECK-P8-NEXT:    xvmulsp 34, 34, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvrsqrtesp 0, 35
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI12_0@toc@l
-; CHECK-P9-NEXT:    lxvx 2, 0, 3
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI12_1@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI12_1@toc@l
+; CHECK-P9-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-P9-NEXT:    xvmulsp 1, 35, 0
+; CHECK-P9-NEXT:    lxv 2, 16(3)
 ; CHECK-P9-NEXT:    xvmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lxvx 1, 0, 3
 ; CHECK-P9-NEXT:    xvmulsp 0, 0, 1
 ; CHECK-P9-NEXT:    xvmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xvmulsp 34, 34, 0
 ; CHECK-P9-NEXT:    blr
   %x = call reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
   %r = fdiv reassoc arcp <4 x float> %a, %x
; CHECK-P9-NEXT:    blr
   %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
   %r = fdiv <4 x float> %a, %x
   ret <4 x float> %r
 }
 
 define double @foo2_fmf(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo2_fmf:
 ; CHECK-P7:       # %bb.0:
+; CHECK-P7-NEXT:    addis 3, 2, .LC6@toc@ha
 ; CHECK-P7-NEXT:    fre 0, 2
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI14_0@toc@l(3)
+; CHECK-P7-NEXT:    ld 3, .LC6@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 0(3)
 ; CHECK-P7-NEXT:    fmadd 3, 2, 0, 3
 ; CHECK-P7-NEXT:    fnmsub 0, 0, 3, 0
 ; CHECK-P7-NEXT:    fmul 3, 1, 0
 ; CHECK-P7-NEXT:    fnmsub 1, 2, 3, 1
 ; CHECK-P7-NEXT:    fmadd 1, 0, 1, 3
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo2_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    addis 3, 2, .LC6@toc@ha
 ; CHECK-P8-NEXT:    xsredp 3, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; CHECK-P8-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
+; CHECK-P8-NEXT:    ld 3, .LC6@toc@l(3)
+; CHECK-P8-NEXT:    lfsx 0, 0, 3
 ; CHECK-P8-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P8-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P8-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P8-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P8-NEXT:    fmr 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo2_fmf:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC6@toc@ha
 ; CHECK-P9-NEXT:    xsredp 3, 2
-; CHECK-P9-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
+; CHECK-P9-NEXT:    ld 3, .LC6@toc@l(3)
+; CHECK-P9-NEXT:    lfs 0, 0(3)
 ; CHECK-P9-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
   %r = fdiv reassoc arcp nsz ninf double %a, %b

 
 define double @foo3_fmf(double %a) nounwind {
 ; CHECK-P7-LABEL: foo3_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    ftsqrt 0, 1
 ; CHECK-P7-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI20_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI20_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC7@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC7@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 4(3)
+; CHECK-P7-NEXT:    lfs 4, 0(3)
 ; CHECK-P7-NEXT:    fmul 2, 1, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    fmadd 0, 1, 0, 3
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB20_2:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo3_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xstsqrtdp 0, 1
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI20_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 5, 3
+; CHECK-P8-NEXT:    addis 3, 2, .LC7@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC7@toc@l(3)
+; CHECK-P8-NEXT:    lfs 3, 4(3)
+; CHECK-P8-NEXT:    lfsx 4, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 2, 1, 0
+; CHECK-P8-NEXT:    fmr 5, 3
 ; CHECK-P8-NEXT:    xsmaddadp 5, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 4
 ; CHECK-P8-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB20_2:
 ; CHECK-P8-NEXT:    xssqrtdp 1, 1
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo3_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xstsqrtdp 0, 1
 ; CHECK-P9-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P9-NEXT:  # %bb.1:
+; CHECK-P9-NEXT:    addis 3, 2, .LC7@toc@ha
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 1
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC7@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 4(3)
 ; CHECK-P9-NEXT:    xsmuldp 2, 1, 0
 ; CHECK-P9-NEXT:    fmr 4, 3
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI20_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, 0(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB20_2:
 ; CHECK-P9-NEXT:    xssqrtdp 1, 1
 ; CHECK-P9-NEXT:    blr
   %r = call reassoc ninf afn double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_fmf_crbits_off(double %a) #2 {
 ; CHECK-P7-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P7:       # %bb.0:
+; CHECK-P7-NEXT:    addis 3, 2, .LC8@toc@ha
 ; CHECK-P7-NEXT:    fabs 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
-; CHECK-P7-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
+; CHECK-P7-NEXT:    ld 3, .LC8@toc@l(3)
+; CHECK-P7-NEXT:    lfd 2, 0(3)
 ; CHECK-P7-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P7-NEXT:    blt 0, .LBB21_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI21_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 4, .LCPI21_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC9@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC9@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 4(3)
+; CHECK-P7-NEXT:    lfs 4, 0(3)
 ; CHECK-P7-NEXT:    fmul 2, 1, 0
 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 3
 ; CHECK-P7-NEXT:    fmul 0, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    fmadd 0, 1, 0, 3
 ; CHECK-P7-NEXT:    fmul 1, 1, 4
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB21_2:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    addis 3, 2, .LC8@toc@ha
 ; CHECK-P8-NEXT:    xsabsdp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
-; CHECK-P8-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
+; CHECK-P8-NEXT:    ld 3, .LC8@toc@l(3)
+; CHECK-P8-NEXT:    lfdx 2, 0, 3
 ; CHECK-P8-NEXT:    xscmpudp 0, 0, 2
 ; CHECK-P8-NEXT:    blt 0, .LBB21_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI21_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 5, 3
+; CHECK-P8-NEXT:    addis 3, 2, .LC9@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC9@toc@l(3)
+; CHECK-P8-NEXT:    lfs 3, 4(3)
+; CHECK-P8-NEXT:    lfsx 4, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 2, 1, 0
+; CHECK-P8-NEXT:    fmr 5, 3
 ; CHECK-P8-NEXT:    xsmaddadp 5, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 4
 ; CHECK-P8-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB21_2:
 ; CHECK-P8-NEXT:    xssqrtdp 1, 1
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC8@toc@ha
 ; CHECK-P9-NEXT:    xsabsdp 0, 1
-; CHECK-P9-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
+; CHECK-P9-NEXT:    ld 3, .LC8@toc@l(3)
+; CHECK-P9-NEXT:    lfd 2, 0(3)
 ; CHECK-P9-NEXT:    xscmpudp 0, 0, 2
 ; CHECK-P9-NEXT:    blt 0, .LBB21_2
 ; CHECK-P9-NEXT:  # %bb.1:
+; CHECK-P9-NEXT:    addis 3, 2, .LC9@toc@ha
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 1
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC9@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, 4(3)
 ; CHECK-P9-NEXT:    xsmuldp 2, 1, 0
 ; CHECK-P9-NEXT:    fmr 4, 3
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI21_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, 0(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB21_2:

 ; CHECK-P9-NEXT:    blr
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define float @goo3_fmf(float %a) nounwind {
 ; CHECK-P7-LABEL: goo3_fmf:
 ; CHECK-P7:       # %bb.0:
+; CHECK-P7-NEXT:    addis 3, 2, .LC10@toc@ha
 ; CHECK-P7-NEXT:    fabs 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
-; CHECK-P7-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
+; CHECK-P7-NEXT:    ld 3, .LC10@toc@l(3)
+; CHECK-P7-NEXT:    lfs 2, 0(3)
 ; CHECK-P7-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P7-NEXT:    blt 0, .LBB23_2
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrtes 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI23_1@toc@ha
-; CHECK-P7-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 3, .LCPI23_1@toc@l(4)
+; CHECK-P7-NEXT:    lfs 2, 12(3)
+; CHECK-P7-NEXT:    lfs 3, 8(3)
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    fmadds 0, 1, 0, 2
 ; CHECK-P7-NEXT:    fmuls 1, 1, 3
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB23_2:
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_3@toc@ha
-; CHECK-P7-NEXT:    lfs 1, .LCPI23_3@toc@l(3)
+; CHECK-P7-NEXT:    lfs 1, 4(3)
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: goo3_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    addis 3, 2, .LC10@toc@ha
 ; CHECK-P8-NEXT:    xsabsdp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
-; CHECK-P8-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
+; CHECK-P8-NEXT:    ld 3, .LC10@toc@l(3)
+; CHECK-P8-NEXT:    lfsx 2, 0, 3
 ; CHECK-P8-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P8-NEXT:    xxlxor 0, 0, 0
 ; CHECK-P8-NEXT:    blt 0, .LBB23_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI23_1@toc@ha
-; CHECK-P8-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P8-NEXT:    lfs 3, .LCPI23_1@toc@l(4)
+; CHECK-P8-NEXT:    lfs 2, 8(3)
+; CHECK-P8-NEXT:    lfs 3, 4(3)
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddasp 2, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P8-NEXT:  .LBB23_2:
 ; CHECK-P8-NEXT:    fmr 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: goo3_fmf:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC10@toc@ha
 ; CHECK-P9-NEXT:    xsabsdp 0, 1
-; CHECK-P9-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
+; CHECK-P9-NEXT:    ld 3, .LC10@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, 0(3)
 ; CHECK-P9-NEXT:    fcmpu 0, 0, 2
 ; CHECK-P9-NEXT:    xxlxor 0, 0, 0
 ; CHECK-P9-NEXT:    blt 0, .LBB23_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 1
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P9-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
+; CHECK-P9-NEXT:    lfs 2, 8(3)
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddasp 2, 1, 0
-; CHECK-P9-NEXT:    lfs 0, .LCPI23_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 0, 4(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:  .LBB23_2:
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
   %r = call reassoc ninf afn float @llvm.sqrt.f32(float %a)
   ret float %r
 }
; CHECK-P9-NEXT:    blr
   %r = call float @llvm.sqrt.f32(float %a)
   ret float %r
 }
 
 define <4 x float> @hoo3_fmf(<4 x float> %a) #1 {
 ; CHECK-P7-LABEL: hoo3_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 3, -1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
+; CHECK-P7-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-P7-NEXT:    li 4, 16
 ; CHECK-P7-NEXT:    vrsqrtefp 4, 2
-; CHECK-P7-NEXT:    addi 3, 3, .LCPI25_0@toc@l
-; CHECK-P7-NEXT:    lvx 0, 0, 3
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI25_1@toc@ha
-; CHECK-P7-NEXT:    addi 3, 3, .LCPI25_1@toc@l
+; CHECK-P7-NEXT:    ld 3, .LC11@toc@l(3)
+; CHECK-P7-NEXT:    lvx 0, 3, 4
 ; CHECK-P7-NEXT:    lvx 1, 0, 3
 ; CHECK-P7-NEXT:    vslw 3, 3, 3
 ; CHECK-P7-NEXT:    vmaddfp 5, 2, 4, 3
 ; CHECK-P7-NEXT:    vmaddfp 4, 5, 4, 0
 ; CHECK-P7-NEXT:    vmaddfp 5, 5, 1, 3
 ; CHECK-P7-NEXT:    vxor 0, 0, 0
 ; CHECK-P7-NEXT:    vmaddfp 3, 5, 4, 3
 ; CHECK-P7-NEXT:    vcmpeqfp 2, 2, 0
 ; CHECK-P7-NEXT:    vsel 2, 3, 0, 2
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo3_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtsp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB25_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 34
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI25_1@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI25_0@toc@l
-; CHECK-P8-NEXT:    xvmulsp 1, 34, 0
-; CHECK-P8-NEXT:    lvx 2, 0, 3
-; CHECK-P8-NEXT:    addi 3, 4, .LCPI25_1@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-P8-NEXT:    li 4, 16
+; CHECK-P8-NEXT:    ld 3, .LC11@toc@l(3)
 ; CHECK-P8-NEXT:    lvx 3, 0, 3
+; CHECK-P8-NEXT:    xvmulsp 1, 34, 0
+; CHECK-P8-NEXT:    lvx 2, 3, 4
 ; CHECK-P8-NEXT:    xvmaddasp 34, 1, 0
 ; CHECK-P8-NEXT:    xvmulsp 0, 1, 35
 ; CHECK-P8-NEXT:    xvmulsp 34, 0, 34
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB25_2:
 ; CHECK-P8-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo3_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvtsqrtsp 0, 34
 ; CHECK-P9-NEXT:    bc 12, 2, .LBB25_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xvrsqrtesp 0, 34
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI25_0@toc@l
-; CHECK-P9-NEXT:    lxvx 2, 0, 3
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI25_1@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI25_1@toc@l
+; CHECK-P9-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC11@toc@l(3)
 ; CHECK-P9-NEXT:    xvmulsp 1, 34, 0
+; CHECK-P9-NEXT:    lxv 2, 16(3)
 ; CHECK-P9-NEXT:    xvmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lxvx 0, 0, 3
 ; CHECK-P9-NEXT:    xvmulsp 0, 1, 0
 ; CHECK-P9-NEXT:    xvmulsp 34, 0, 2
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB25_2:
 ; CHECK-P9-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P9-NEXT:    blr
; CHECK-P9-NEXT:    blr
   %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <2 x double> @hoo4_fmf(<2 x double> %a) #1 {
 ; CHECK-P7-LABEL: hoo4_fmf:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    ftsqrt 0, 1
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; CHECK-P7-NEXT:    addis 4, 2, .LCPI27_1@toc@ha
-; CHECK-P7-NEXT:    lfs 3, .LCPI27_0@toc@l(3)
-; CHECK-P7-NEXT:    lfs 0, .LCPI27_1@toc@l(4)
+; CHECK-P7-NEXT:    addis 3, 2, .LC12@toc@ha
+; CHECK-P7-NEXT:    ld 3, .LC12@toc@l(3)
+; CHECK-P7-NEXT:    lfs 3, 4(3)
+; CHECK-P7-NEXT:    lfs 0, 0(3)
 ; CHECK-P7-NEXT:    bc 12, 2, .LBB27_3
 ; CHECK-P7-NEXT:  # %bb.1:
 ; CHECK-P7-NEXT:    frsqrte 4, 1
 ; CHECK-P7-NEXT:    fmul 5, 1, 4
 ; CHECK-P7-NEXT:    fmadd 5, 5, 4, 3
 ; CHECK-P7-NEXT:    fmul 4, 4, 0
 ; CHECK-P7-NEXT:    fmul 4, 4, 5
 ; CHECK-P7-NEXT:    fmul 1, 1, 4

 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo4_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xvtsqrtdp 0, 34
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB27_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtedp 0, 34
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x 1, 0, 3
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI27_1@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC12@toc@ha
+; CHECK-P8-NEXT:    li 4, 16
+; CHECK-P8-NEXT:    ld 3, .LC12@toc@l(3)
+; CHECK-P8-NEXT:    lxvd2x 1, 3, 4
 ; CHECK-P8-NEXT:    lxvd2x 3, 0, 3
-; CHECK-P8-NEXT:    xxswapd 1, 1
 ; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
+; CHECK-P8-NEXT:    xxswapd 1, 1
 ; CHECK-P8-NEXT:    xxswapd 3, 3
 ; CHECK-P8-NEXT:    xxlor 4, 1, 1
 ; CHECK-P8-NEXT:    xvmaddadp 4, 2, 0
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 3
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
 ; CHECK-P8-NEXT:    xvmaddadp 1, 2, 0
 ; CHECK-P8-NEXT:    xvmuldp 0, 2, 3
 ; CHECK-P8-NEXT:    xvmuldp 34, 0, 1
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB27_2:
 ; CHECK-P8-NEXT:    xvsqrtdp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo4_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvtsqrtdp 0, 34
 ; CHECK-P9-NEXT:    bc 12, 2, .LBB27_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xvrsqrtedp 0, 34
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI27_0@toc@l
-; CHECK-P9-NEXT:    lxvx 2, 0, 3
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI27_1@toc@l
+; CHECK-P9-NEXT:    addis 3, 2, .LC12@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC12@toc@l(3)
 ; CHECK-P9-NEXT:    xvmuldp 1, 34, 0
+; CHECK-P9-NEXT:    lxv 2, 16(3)
 ; CHECK-P9-NEXT:    xxlor 3, 2, 2
 ; CHECK-P9-NEXT:    xvmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    lxvx 1, 0, 3
 ; CHECK-P9-NEXT:    xvmuldp 0, 0, 1
 ; CHECK-P9-NEXT:    xvmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xvmuldp 3, 34, 0
 ; CHECK-P9-NEXT:    xvmaddadp 2, 3, 0
 ; CHECK-P9-NEXT:    xvmuldp 0, 3, 1

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
 
 ; Check if this causes infinite loop when estimation disabled
 define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
 ; CHECK-LABEL: repeated_fp_divisor_noest:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    xxspltw 0, 0, 0
 ; CHECK-NEXT:    xvdivsp 0, 35, 0
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    xvmulsp 1, 34, 35
 ; CHECK-NEXT:    xvmulsp 34, 1, 0
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
   %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 
 define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
 ; CHECK-LABEL: repeated_fp_divisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI1_1@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    xxspltw 0, 0, 0
 ; CHECK-NEXT:    xvresp 1, 0
 ; CHECK-NEXT:    xvnmsubasp 35, 0, 1
 ; CHECK-NEXT:    xvmulsp 0, 34, 36
 ; CHECK-NEXT:    xvmaddasp 1, 1, 35
 ; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
   %mul = fdiv reassoc arcp nsz ninf <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   %c = icmp ugt i64 %x, %noty
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI24_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI24_1@toc@l
 ; CHECK-NEXT:    vminub 2, 2, 3
-; CHECK-NEXT:    lvx 3, 0, 3
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    vaddubm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %r = add <16 x i8> %s, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI25_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI25_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vaddubs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, %a
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI26_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vaddubs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
   %c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
   %r = select <16 x i1> %c, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %a
   ret <16 x i8> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI27_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI27_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI27_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI27_1@toc@l
 ; CHECK-NEXT:    vminuh 2, 2, 3
-; CHECK-NEXT:    lvx 3, 0, 3
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    vadduhm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %r = add <8 x i16> %s, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI28_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI28_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduhs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, %a
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI29_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduhs 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
   %c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
   %r = select <8 x i1> %c, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %a
   ret <8 x i16> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI30_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI30_0@toc@l
-; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI30_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI30_1@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC6@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC6@toc@l(3)
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    vminuw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = add <4 x i32> %s, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI31_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI31_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC7@toc@ha
+; CHECK-NEXT:    ld 3, .LC7@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduws 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, %a
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI32_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC8@toc@ha
+; CHECK-NEXT:    ld 3, .LC8@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduws 2, 2, 3
 ; CHECK-NEXT:    blr
   %a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
   %c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
   %r = select <4 x i1> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a
   ret <4 x i32> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI33_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI33_0@toc@l
-; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI33_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI33_1@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC9@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC9@toc@l(3)
+; CHECK-NEXT:    lxvd2x 0, 3, 4
 ; CHECK-NEXT:    xxswapd 35, 0
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    vminud 2, 2, 3
 ; CHECK-NEXT:    xxswapd 35, 0
 ; CHECK-NEXT:    vaddudm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
   %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
   %r = add <2 x i64> %s, <i64 42, i64 42>
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI34_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC10@toc@ha
+; CHECK-NEXT:    ld 3, .LC10@toc@l(3)
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 35, 0
 ; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vaddudm 3, 2, 3
 ; CHECK-NEXT:    vcmpgtud 2, 2, 3
 ; CHECK-NEXT:    xxsel 34, 35, 0, 34
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, %a
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r
 }
 
 define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
 ; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI35_1@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC11@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC11@toc@l(3)
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI35_0@toc@l
-; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    lxvd2x 1, 3, 4
 ; CHECK-NEXT:    xxswapd 35, 0
-; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    xxswapd 36, 1
+; CHECK-NEXT:    xxleqv 0, 0, 0
 ; CHECK-NEXT:    vcmpgtud 3, 2, 3
 ; CHECK-NEXT:    vaddudm 2, 2, 4
 ; CHECK-NEXT:    xxsel 34, 34, 0, 35
 ; CHECK-NEXT:    blr
   %a = add <2 x i64> %x, <i64 42, i64 42>
   %c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
   %r = select <2 x i1> %c, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %a
   ret <2 x i64> %r

llvm/test/CodeGen/PowerPC/scalar_cmp.ll

entry:
   %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 ; Test RHS is 1.000000e+00
 define double @onecmp1(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp1:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; FAST-P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; FAST-P8-NEXT:    ld r3, .LC0@toc@l(r3)
+; FAST-P8-NEXT:    lfsx f0, 0, r3
 ; FAST-P8-NEXT:    xssubdp f0, f1, f0
 ; FAST-P8-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp1:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; FAST-P9-NEXT:    addis r3, r2, .LC0@toc@ha
+; FAST-P9-NEXT:    ld r3, .LC0@toc@l(r3)
+; FAST-P9-NEXT:    lfs f0, 0(r3)
 ; FAST-P9-NEXT:    xssubdp f0, f1, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp1:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; NO-FAST-P8-NEXT:    ld r3, .LC0@toc@l(r3)
+; NO-FAST-P8-NEXT:    lfsx f0, 0, r3
 ; NO-FAST-P8-NEXT:    fcmpu cr0, f1, f0
 ; NO-FAST-P8-NEXT:    cror 4*cr5+lt, lt, un
 ; NO-FAST-P8-NEXT:    bc 12, 4*cr5+lt, .LBB24_2
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f3, f2
 ; NO-FAST-P8-NEXT:  .LBB24_2: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp1:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    addis r3, r2, .LC0@toc@ha
+; NO-FAST-P9-NEXT:    ld r3, .LC0@toc@l(r3)
+; NO-FAST-P9-NEXT:    lfs f0, 0(r3)
 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f0
 ; NO-FAST-P9-NEXT:    cror 4*cr5+lt, lt, un
 ; NO-FAST-P9-NEXT:    bc 12, 4*cr5+lt, .LBB24_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f2
 ; NO-FAST-P9-NEXT:  .LBB24_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp ult double %a, 1.000000e+00
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 }
 
 define double @onecmp2(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp2:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; FAST-P8-NEXT:    addis r3, r2, .LC1@toc@ha
+; FAST-P8-NEXT:    ld r3, .LC1@toc@l(r3)
+; FAST-P8-NEXT:    lfsx f0, 0, r3
 ; FAST-P8-NEXT:    xssubdp f0, f0, f1
 ; FAST-P8-NEXT:    fsel f1, f0, f3, f2
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp2:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; FAST-P9-NEXT:    addis r3, r2, .LC1@toc@ha
+; FAST-P9-NEXT:    ld r3, .LC1@toc@l(r3)
+; FAST-P9-NEXT:    lfs f0, 0(r3)
 ; FAST-P9-NEXT:    xssubdp f0, f0, f1
 ; FAST-P9-NEXT:    fsel f1, f0, f3, f2
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp2:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    addis r3, r2, .LC1@toc@ha
+; NO-FAST-P8-NEXT:    ld r3, .LC1@toc@l(r3)
+; NO-FAST-P8-NEXT:    lfsx f0, 0, r3
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    bgtlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp2:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    addis r3, r2, .LC1@toc@ha
+; NO-FAST-P9-NEXT:    ld r3, .LC1@toc@l(r3)
+; NO-FAST-P9-NEXT:    lfs f0, 0(r3)
 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P9-NEXT:    bgt cr0, .LBB25_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f2, f3
 ; NO-FAST-P9-NEXT:  .LBB25_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f2
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp ogt double %a, 1.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 }
 
 define double @onecmp3(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp3:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; FAST-P8-NEXT:    addis r3, r2, .LC2@toc@ha
+; FAST-P8-NEXT:    ld r3, .LC2@toc@l(r3)
+; FAST-P8-NEXT:    lfsx f0, 0, r3
 ; FAST-P8-NEXT:    xssubdp f0, f1, f0
 ; FAST-P8-NEXT:    xsnegdp f1, f0
 ; FAST-P8-NEXT:    fsel f0, f0, f2, f3
 ; FAST-P8-NEXT:    fsel f1, f1, f0, f3
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp3:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; FAST-P9-NEXT:    addis r3, r2, .LC2@toc@ha
+; FAST-P9-NEXT:    ld r3, .LC2@toc@l(r3)
+; FAST-P9-NEXT:    lfs f0, 0(r3)
 ; FAST-P9-NEXT:    xssubdp f0, f1, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P9-NEXT:    xsnegdp f0, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f1, f3
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp3:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    addis r3, r2, .LC2@toc@ha
+; NO-FAST-P8-NEXT:    ld r3, .LC2@toc@l(r3)
+; NO-FAST-P8-NEXT:    lfsx f0, 0, r3
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    beqlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp3:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    addis r3, r2, .LC2@toc@ha
+; NO-FAST-P9-NEXT:    ld r3, .LC2@toc@l(r3)
+; NO-FAST-P9-NEXT:    lfs f0, 0(r3)
 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P9-NEXT:    beq cr0, .LBB26_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f2, f3
 ; NO-FAST-P9-NEXT:  .LBB26_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f2
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp oeq double %a, 1.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 }

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lwz r3, 0(r3)
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test1:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; P8LE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
-; P8LE-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; P8LE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lwz r3, 4(r3)
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test2:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; P8LE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; P8LE-NEXT:    addi r3, r3, 4
-; P8LE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; P8LE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4

 ; P9BE-NEXT:    sldi r4, r7, 2
 ; P9BE-NEXT:    lwzx r3, r3, r4
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test3:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; P8LE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; P8LE-NEXT:    sldi r5, r7, 2
-; P8LE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; P8LE-NEXT:    ld r4, .LC2@toc@l(r4)
 ; P8LE-NEXT:    lxsiwzx v3, r3, r5
 ; P8LE-NEXT:    lvx v4, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v3, v4
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r7, 2

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lwz r3, 4(r3)
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test4:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; P8LE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; P8LE-NEXT:    addi r3, r3, 4
-; P8LE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; P8LE-NEXT:    ld r4, .LC3@toc@l(r4)
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4

 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lwz r3, 0(r5)
 ; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test5:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; P8LE-NEXT:    addis r3, r2, .LC4@toc@ha
 ; P8LE-NEXT:    lxsiwzx v4, 0, r5
-; P8LE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; P8LE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; P8LE-NEXT:    lvx v3, 0, r3
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test5:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r5
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1

 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpspn vs0, f0
 ; P9BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f1:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
+; P8LE-NEXT:    addis r4, r2, .LC5@toc@ha
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
-; P8LE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
+; P8LE-NEXT:    ld r4, .LC5@toc@l(r4)
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
 ; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1

llvm/test/CodeGen/PowerPC/select_const.ll

; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 2, i8 3
   %bo = ashr i8 128, %sel
   ret i8 %bo
 }
 
 define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fadd_constant:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC0@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
+; ISEL-NEXT:    ld 4, .LC0@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fadd_constant:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC0@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC0@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB42_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB42_2
 ; NO_ISEL-NEXT:  .LBB42_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fadd double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fsub_constant:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC1@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
+; ISEL-NEXT:    ld 4, .LC1@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fsub_constant:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC1@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC1@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB43_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB43_2
 ; NO_ISEL-NEXT:  .LBB43_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double %sel, 5.1
   ret double %bo
 }
 
 define double @fsub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fsub_constant_sel_constants:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC2@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
+; ISEL-NEXT:    ld 4, .LC2@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fsub_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC2@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC2@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB44_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB44_2
 ; NO_ISEL-NEXT:  .LBB44_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double 5.1, %sel
   ret double %bo
 }
 
 define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fmul_constant:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC3@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
+; ISEL-NEXT:    ld 4, .LC3@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fmul_constant:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC3@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC3@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB45_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB45_2
 ; NO_ISEL-NEXT:  .LBB45_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fmul double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fdiv_constant:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC4@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
+; ISEL-NEXT:    ld 4, .LC4@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC4@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC4@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB46_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB46_2
 ; NO_ISEL-NEXT:  .LBB46_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double %sel, 5.1
   ret double %bo
 }
 
 define double @fdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fdiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC5@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
+; ISEL-NEXT:    ld 4, .LC5@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
 ; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fdiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC5@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
+; NO_ISEL-NEXT:    ld 4, .LC5@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB47_2
 ; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB47_2
 ; NO_ISEL-NEXT:  .LBB47_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double 5.1, %sel
   ret double %bo
 }
 
 define double @sel_constants_frem_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_frem_constant:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    andi. 3, 3, 1
 ; ALL-NEXT:    bc 12, 1, .LBB48_2
 ; ALL-NEXT:  # %bb.1:
-; ALL-NEXT:    addis 3, 2, .LCPI48_0@toc@ha
-; ALL-NEXT:    lfd 1, .LCPI48_0@toc@l(3)
+; ALL-NEXT:    addis 3, 2, .LC6@toc@ha
+; ALL-NEXT:    ld 3, .LC6@toc@l(3)
+; ALL-NEXT:    lfdx 1, 0, 3
 ; ALL-NEXT:    blr
 ; ALL-NEXT:  .LBB48_2:
-; ALL-NEXT:    addis 3, 2, .LCPI48_1@toc@ha
-; ALL-NEXT:    lfs 1, .LCPI48_1@toc@l(3)
+; ALL-NEXT:    addis 3, 2, .LC7@toc@ha
+; ALL-NEXT:    ld 3, .LC7@toc@l(3)
+; ALL-NEXT:    lfsx 1, 0, 3
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double %sel, 5.1
   ret double %bo
 }
 
 define double @frem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: frem_constant_sel_constants:
 ; ISEL:       # %bb.0:
+; ISEL-NEXT:    addis 4, 2, .LC8@toc@ha
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
-; ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
-; ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
-; ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; ISEL-NEXT:    iselgt 3, 3, 4
+; ISEL-NEXT:    ld 4, .LC8@toc@l(4)
+; ISEL-NEXT:    addi 3, 4, 8
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: frem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
+; NO_ISEL-NEXT:    addis 4, 2, .LC8@toc@ha
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
-; NO_ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
-; NO_ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
-; NO_ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; NO_ISEL-NEXT:    bc 12, 1, .LBB49_2
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    ld 4, .LC8@toc@l(4)
+; NO_ISEL-NEXT:    addi 3, 4, 8
+; NO_ISEL-NEXT:    bc 12, 1, .LBB49_1
 ; NO_ISEL-NEXT:    b .LBB49_2
+; NO_ISEL-NEXT:  .LBB49_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:  .LBB49_2:
 ; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double 5.1, %sel
   ret double %bo
 }

llvm/test/CodeGen/PowerPC/signbit-shift.ll

; CHECK-NEXT:    blr
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_zext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 35, 35, 35
-; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vsubuwm 2, 3, 2
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = zext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
   ret <4 x i32> %r
; CHECK-NEXT:    blr
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_sext_ifpos_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxleqv 35, 35, 35
-; CHECK-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = sext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
; CHECK-NEXT:    blr
   ret i32 %r
 }
 
 define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: add_lshr_not_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
-; CHECK-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI15_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
; CHECK-NEXT:    blr
   ret i32 %r
 }
 
 define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
 ; CHECK-LABEL: sub_lshr_not_vec_splat:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
-; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsrw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
   %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
; CHECK-NEXT:    blr
   ret i32 %r
 }
 
 define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
 ; CHECK-LABEL: sub_const_op_lshr_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
-; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
   ret <4 x i32> %r
 }
 

llvm/test/CodeGen/PowerPC/toc-float.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
 
 ; As the constant could be represented as float, a float is
 ; loaded from constant pool.
 define double @doubleConstant1() {
 ; CHECK-P9-LABEL: doubleConstant1:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P9-NEXT:    lfs 1, 0(3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: doubleConstant1:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P8-NEXT:    lfsx 1, 0, 3
 ; CHECK-P8-NEXT:    blr
   ret double 1.400000e+01
 }
 
 ; As the constant couldn't be represented as float, a double is
 ; loaded from constant pool.
 define double @doubleConstant2() {
 ; CHECK-P9-LABEL: doubleConstant2:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    lfd 1, .LCPI1_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-P9-NEXT:    lfd 1, 0(3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: doubleConstant2:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    lfd 1, .LCPI1_0@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-P8-NEXT:    lfdx 1, 0, 3
 ; CHECK-P8-NEXT:    blr
   ret double 2.408904e+01
 }
 
 @FArr = hidden local_unnamed_addr global [10 x float] zeroinitializer, align 4
 
 define float @floatConstantArray() local_unnamed_addr  {
 ; CHECK-P9-LABEL: floatConstantArray:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    addis 3, 2, FArr@toc@ha+12
 ; CHECK-P9-NEXT:    lfs 0, FArr@toc@l+12(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    lfs 1, .LCPI2_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-P9-NEXT:    lfs 1, 0(3)
 ; CHECK-P9-NEXT:    xsaddsp 1, 0, 1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: floatConstantArray:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, FArr@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, FArr@toc@l
-; CHECK-P8-NEXT:    lfs 1, .LCPI2_0@toc@l(4)
-; CHECK-P8-NEXT:    lfs 0, 12(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-P8-NEXT:    addis 4, 2, FArr@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-P8-NEXT:    addi 4, 4, FArr@toc@l
+; CHECK-P8-NEXT:    lfs 0, 12(4)
+; CHECK-P8-NEXT:    lfsx 1, 0, 3
 ; CHECK-P8-NEXT:    xsaddsp 1, 0, 1
 ; CHECK-P8-NEXT:    blr
   %1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4
   %2 = fadd float %1, 0x400B333340000000
   ret float %2
 }
 
 define float @floatConstant() {
 ; CHECK-P9-LABEL: floatConstant:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    lfs 1, .LCPI3_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-P9-NEXT:    lfs 1, 0(3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: floatConstant:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    lfs 1, .LCPI3_0@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC3@toc@l(3)
+; CHECK-P8-NEXT:    lfsx 1, 0, 3
 ; CHECK-P8-NEXT:    blr
   ret float 0x400470A3E0000000
 }
 
 ; llvm put the hidden globals into the TOC table.
 ; TODO - do some analysis and decide which globals could be put into TOC.
 @d = hidden local_unnamed_addr global [200 x double] zeroinitializer, align 8
 
 define double @doubleConstantArray()  {
 ; CHECK-P9-LABEL: doubleConstantArray:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    addis 3, 2, d@toc@ha+24
 ; CHECK-P9-NEXT:    lfd 0, d@toc@l+24(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    lfd 1, .LCPI4_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-P9-NEXT:    lfd 1, 0(3)
 ; CHECK-P9-NEXT:    xsadddp 1, 0, 1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: doubleConstantArray:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, d@toc@ha
-; CHECK-P8-NEXT:    addis 4, 2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, d@toc@l
-; CHECK-P8-NEXT:    lfd 1, .LCPI4_0@toc@l(4)
-; CHECK-P8-NEXT:    lfd 0, 24(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-P8-NEXT:    addis 4, 2, d@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-P8-NEXT:    addi 4, 4, d@toc@l
+; CHECK-P8-NEXT:    lfd 0, 24(4)
+; CHECK-P8-NEXT:    lfdx 1, 0, 3
 ; CHECK-P8-NEXT:    xsadddp 1, 0, 1
 ; CHECK-P8-NEXT:    blr
   %1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8
   %2 = fadd double %1, 6.880000e+00
   ret double %2
 }
 
 @arr = hidden local_unnamed_addr global [20000 x double] zeroinitializer, align 8
 
 ; Access an element with an offset that doesn't fit in the displacement field of LFD.
 define double @doubleLargeConstantArray()  {
 ; CHECK-P9-LABEL: doubleLargeConstantArray:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    addis 3, 2, arr@toc@ha
 ; CHECK-P9-NEXT:    li 4, 0
 ; CHECK-P9-NEXT:    addi 3, 3, arr@toc@l
 ; CHECK-P9-NEXT:    ori 4, 4, 32768
 ; CHECK-P9-NEXT:    lfdx 0, 3, 4
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    lfd 1, .LCPI5_0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC5@toc@l(3)
+; CHECK-P9-NEXT:    lfd 1, 0(3)
 ; CHECK-P9-NEXT:    xsadddp 1, 0, 1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: doubleLargeConstantArray:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, arr@toc@ha
-; CHECK-P8-NEXT:    li 4, 0
-; CHECK-P8-NEXT:    addis 5, 2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, arr@toc@l
-; CHECK-P8-NEXT:    ori 4, 4, 32768
-; CHECK-P8-NEXT:    lfdx 0, 3, 4
-; CHECK-P8-NEXT:    lfd 1, .LCPI5_0@toc@l(5)
+; CHECK-P8-NEXT:    addis 3, 2, .LC5@toc@ha
+; CHECK-P8-NEXT:    addis 4, 2, arr@toc@ha
+; CHECK-P8-NEXT:    li 5, 0
+; CHECK-P8-NEXT:    ld 3, .LC5@toc@l(3)
+; CHECK-P8-NEXT:    addi 4, 4, arr@toc@l
+; CHECK-P8-NEXT:    ori 5, 5, 32768
+; CHECK-P8-NEXT:    lfdx 0, 4, 5
+; CHECK-P8-NEXT:    lfdx 1, 0, 3
 ; CHECK-P8-NEXT:    xsadddp 1, 0, 1
 ; CHECK-P8-NEXT:    blr
   %1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8
   %2 = fadd double %1, 6.880000e+00
   ret double %2
 }
 
 @vec_arr = global [10 x <4 x i32>] zeroinitializer, align 16
 
 define <4 x i32> @vectorArray() #0 {
 ; CHECK-P9-LABEL: vectorArray:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis 3, 2, .LC0@toc@ha
-; CHECK-P9-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P9-NEXT:    addis 3, 2, .LC6@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC6@toc@l(3)
 ; CHECK-P9-NEXT:    lxv 34, 32(3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: vectorArray:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LC0@toc@ha
-; CHECK-P8-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LC6@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC6@toc@l(3)
 ; CHECK-P8-NEXT:    addi 3, 3, 32
 ; CHECK-P8-NEXT:    lvx 2, 0, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = load <4 x i32>, <4 x i32>* getelementptr inbounds ([10 x <4 x i32>], [10 x <4 x i32>]* @vec_arr, i64 0, i64 2), align 16
   ret <4 x i32> %0
 }

llvm/test/CodeGen/PowerPC/vavg.ll

entry:
   %add1 = add <16 x i8> %add, %n
   %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %shr
 }
 
 define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-P9-LABEL: test_v8i16_sign_negative:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    vadduhm 2, 2, 3
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-P9-NEXT:    lxvx 35, 0, 3
 ; CHECK-P9-NEXT:    vadduhm 2, 2, 3
 ; CHECK-P9-NEXT:    vspltish 3, 1
 ; CHECK-P9-NEXT:    vsrah 2, 2, 3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v8i16_sign_negative:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P8-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    vadduhm 2, 2, 3
 ; CHECK-P8-NEXT:    vspltish 4, 1
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P8-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-P8-NEXT:    lvx 3, 0, 3
 ; CHECK-P8-NEXT:    vadduhm 2, 2, 3
 ; CHECK-P8-NEXT:    vsrah 2, 2, 4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16_sign_negative:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addis 3, 2, .LCPI6_0@toc@ha
+; CHECK-P7-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-P7-NEXT:    vadduhm 2, 2, 3
 ; CHECK-P7-NEXT:    vspltish 4, 1
-; CHECK-P7-NEXT:    addi 3, 3, .LCPI6_0@toc@l
+; CHECK-P7-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-P7-NEXT:    lvx 3, 0, 3
 ; CHECK-P7-NEXT:    vadduhm 2, 2, 3
 ; CHECK-P7-NEXT:    vsrah 2, 2, 4
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1>
   %add1 = add <8 x i16> %add, %n
   %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: test8:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI0_2@toc@ha
-; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_1@toc@ha
-; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI0_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI0_2@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI0_1@toc@l
+; CHECK-P8-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    lvx v4, 0, r4
+; CHECK-P8-NEXT:    li r4, 32
+; CHECK-P8-NEXT:    xxlxor v3, v3, v3
+; CHECK-P8-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI0_3@toc@ha
-; CHECK-P8-NEXT:    lvx v5, 0, r6
-; CHECK-P8-NEXT:    lvx v1, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI0_3@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r5
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    vperm v2, v4, v3, v2
-; CHECK-P8-NEXT:    vperm v5, v4, v3, v5
-; CHECK-P8-NEXT:    vperm v0, v4, v3, v0
-; CHECK-P8-NEXT:    vperm v3, v4, v3, v1
+; CHECK-P8-NEXT:    lvx v5, r5, r6
+; CHECK-P8-NEXT:    lvx v0, r5, r7
+; CHECK-P8-NEXT:    lvx v1, r5, r4
+; CHECK-P8-NEXT:    vperm v2, v3, v4, v2
+; CHECK-P8-NEXT:    vperm v5, v3, v4, v5
+; CHECK-P8-NEXT:    vperm v0, v3, v4, v0
+; CHECK-P8-NEXT:    vperm v3, v3, v4, v1
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v5
 ; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
 ; CHECK-P8-NEXT:    xvcvuxddp vs3, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r6
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI0_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI0_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI0_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI0_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI0_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI0_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
   %1 = uitofp <8 x i16> %0 to <8 x double>
   store <8 x double> %1, <8 x double>* %Sink, align 16
   ret void
 }
 
 define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: test4:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI1_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC1@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI1_1@toc@l
-; CHECK-P8-NEXT:    lvx v5, 0, r5
+; CHECK-P8-NEXT:    lvx v5, r5, r6
 ; CHECK-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v4, v3, v5
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
   %1 = uitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %Sink, align 16
   ret void
 }
 
 define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: test2:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC2@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC2@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
 ; CHECK-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
   %1 = uitofp <2 x i16> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %Sink, align 16
   ret void
 }
 
 define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: stest8:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI3_2@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC3@toc@ha
+; CHECK-P8-NEXT:    addis r6, r2, .LC4@toc@ha
+; CHECK-P8-NEXT:    li r7, 32
+; CHECK-P8-NEXT:    li r8, 16
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI3_2@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_3@toc@ha
-; CHECK-P8-NEXT:    lvx v4, 0, r6
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI3_4@toc@ha
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_3@toc@l
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI3_4@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r5
+; CHECK-P8-NEXT:    ld r5, .LC3@toc@l(r5)
+; CHECK-P8-NEXT:    ld r6, .LC4@toc@l(r6)
+; CHECK-P8-NEXT:    lvx v2, 0, r5
+; CHECK-P8-NEXT:    lvx v4, r5, r7
+; CHECK-P8-NEXT:    lvx v5, r5, r8
+; CHECK-P8-NEXT:    lvx v0, r5, r4
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r6
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    vperm v4, v3, v3, v4
 ; CHECK-P8-NEXT:    vperm v5, v3, v3, v5
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v0
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v2, v2, v0
-; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0
-; CHECK-P8-NEXT:    xvcvsxddp vs2, v3
+; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v5
+; CHECK-P8-NEXT:    xvcvsxddp vs2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp vs3, v4
-; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
 ; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r8
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest8:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC3@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC3@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
   %1 = sitofp <8 x i16> %0 to <8 x double>
   store <8 x double> %1, <8 x double>* %Sink, align 16
   ret void
 }
 
 define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: stest4:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI4_2@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC5@toc@ha
+; CHECK-P8-NEXT:    addis r6, r2, .LC6@toc@ha
+; CHECK-P8-NEXT:    li r7, 16
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC5@toc@l(r5)
+; CHECK-P8-NEXT:    ld r6, .LC6@toc@l(r6)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI4_2@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v4, 0, r5
+; CHECK-P8-NEXT:    lvx v4, r5, r7
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r6
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r7
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest4:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI4_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI4_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI4_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    ld r4, .LC4@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
   %1 = sitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %Sink, align 16
   ret void
 }
 
 define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
 ; CHECK-P8-LABEL: stest2:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC7@toc@ha
+; CHECK-P8-NEXT:    addis r6, r2, .LC8@toc@ha
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC7@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    ld r5, .LC8@toc@l(r6)
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC5@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
+; CHECK-BE-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-BE-NEXT:    ld r4, .LC5@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
   %1 = sitofp <2 x i16> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %Sink, align 16
   ret void
 }

llvm/test/CodeGen/PowerPC/vec-trunc.ll

entry:
   %1 = trunc <4 x i16> %0 to <4 x i8>
   store <4 x i8> %1, <4 x i8>* %Sink, align 16
   ret void
 }
 
 define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
 ; CHECK-LABEL: test4i8w:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    lvx v3, 0, r4
-; CHECK-NEXT:    addi r5, r5, .LCPI2_0@toc@l
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-NEXT:    lvx v2, 0, r5
 ; CHECK-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
 ; CHECK-NEXT:    stfiwx f0, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4i8w:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-BE-NEXT:    addi r4, r5, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    addi r4, r1, -16
+; CHECK-BE-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
 ; CHECK-BE-NEXT:    lwz r4, -16(r1)
 ; CHECK-BE-NEXT:    stw r4, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
   %1 = trunc <4 x i32> %0 to <4 x i8>
entry:
   %1 = trunc <2 x i32> %0 to <2 x i16>
   store <2 x i16> %1, <2 x i16>* %Sink, align 16
   ret void
 }
 
 define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) {
 ; CHECK-LABEL: test2i16d:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC1@toc@ha
 ; CHECK-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
-; CHECK-NEXT:    addi r4, r5, .LCPI6_0@toc@l
-; CHECK-NEXT:    lvx v3, 0, r4
+; CHECK-NEXT:    ld r4, .LC1@toc@l(r5)
 ; CHECK-NEXT:    xxswapd v2, vs0
+; CHECK-NEXT:    lvx v3, 0, r4
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
 ; CHECK-NEXT:    stfiwx f0, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2i16d:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addis r5, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
-; CHECK-BE-NEXT:    addi r4, r5, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-BE-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-BE-NEXT:    addi r4, r1, -16
+; CHECK-BE-NEXT:    lxvw4x v3, 0, r5
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
 ; CHECK-BE-NEXT:    lwz r4, -16(r1)
 ; CHECK-BE-NEXT:    stw r4, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i64>, <2 x i64>* %SrcPtr, align 16
   %1 = trunc <2 x i64> %0 to <2 x i16>
   store <2 x i16> %1, <2 x i16>* %Sink, align 16
   ret void
 }

llvm/test/CodeGen/PowerPC/vec-trunc2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
 ; CHECK-LABEL: test8x32:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis r11, r2, .LC0@toc@ha
 ; CHECK-NEXT:    rldimi r3, r4, 32, 0
 ; CHECK-NEXT:    rldimi r5, r6, 32, 0
-; CHECK-NEXT:    addis r11, r2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    rldimi r7, r8, 32, 0
 ; CHECK-NEXT:    rldimi r9, r10, 32, 0
-; CHECK-NEXT:    mtfprd f0, r3
-; CHECK-NEXT:    addi r3, r11, .LCPI0_0@toc@l
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r11)
 ; CHECK-NEXT:    mtfprd f1, r5
-; CHECK-NEXT:    lvx v4, 0, r3
 ; CHECK-NEXT:    mtfprd f2, r7
 ; CHECK-NEXT:    mtfprd f3, r9
 ; CHECK-NEXT:    xxmrghd v2, vs1, vs0
+; CHECK-NEXT:    lvx v4, 0, r3
 ; CHECK-NEXT:    xxmrghd v3, vs3, vs2
 ; CHECK-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8x32:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    stw r10, -80(r1)
 ; CHECK-BE-NEXT:    stw r9, -96(r1)
 ; CHECK-BE-NEXT:    stw r8, -112(r1)
 ; CHECK-BE-NEXT:    stw r7, -128(r1)
 ; CHECK-BE-NEXT:    stw r6, -16(r1)
 ; CHECK-BE-NEXT:    stw r5, -32(r1)
 ; CHECK-BE-NEXT:    stw r4, -48(r1)
+; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    stw r3, -64(r1)
 ; CHECK-BE-NEXT:    addi r3, r1, -80
 ; CHECK-BE-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -96
 ; CHECK-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -112
 ; CHECK-BE-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -128
 ; CHECK-BE-NEXT:    lxvw4x v5, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -16
 ; CHECK-BE-NEXT:    lxvw4x v0, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -32
 ; CHECK-BE-NEXT:    lxvw4x v1, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -48
+; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvw4x v6, 0, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -64
 ; CHECK-BE-NEXT:    lxvw4x v7, 0, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    vmrghw v3, v5, v4
 ; CHECK-BE-NEXT:    vmrghw v4, v1, v0
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    lxvw4x v8, 0, r4
 ; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
-; CHECK-BE-NEXT:    lxvw4x v8, 0, r3
 ; CHECK-BE-NEXT:    vmrghw v5, v7, v6
 ; CHECK-BE-NEXT:    xxmrghd v3, v5, v4
 ; CHECK-BE-NEXT:    vperm v2, v3, v2, v8
 ; CHECK-BE-NEXT:    blr
 %v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
 %v11 = insertelement <8 x i32> %v10, i32 %i2, i32 1
 %v12 = insertelement <8 x i32> %v11, i32 %i3, i32 2
 %v13 = insertelement <8 x i32> %v12, i32 %i4, i32 3
 %v14 = insertelement <8 x i32> %v13, i32 %i5, i32 4
 %v15 = insertelement <8 x i32> %v14, i32 %i6, i32 5
 %v16 = insertelement <8 x i32> %v15, i32 %i7, i32 6
 %v17 = insertelement <8 x i32> %v16, i32 %i8, i32 7
 %v2 = trunc <8 x i32> %v17 to <8 x i8>
 ret <8 x i8> %v2
 }
 
 define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
 ; CHECK-LABEL: test4x64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis r7, r2, .LCPI1_0@toc@ha
+; CHECK-NEXT:    addis r7, r2, .LC1@toc@ha
+; CHECK-NEXT:    mtfprd f2, r3
+; CHECK-NEXT:    ld r3, .LC1@toc@l(r7)
 ; CHECK-NEXT:    mtfprd f0, r5
 ; CHECK-NEXT:    mtfprd f1, r6
-; CHECK-NEXT:    mtfprd f2, r3
-; CHECK-NEXT:    addi r3, r7, .LCPI1_0@toc@l
 ; CHECK-NEXT:    mtfprd f3, r4
 ; CHECK-NEXT:    xxmrghd v2, vs1, vs0
 ; CHECK-NEXT:    lvx v4, 0, r3
 ; CHECK-NEXT:    xxmrghd v3, vs3, vs2
 ; CHECK-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4x64:
 ; CHECK-BE:       # %bb.0:
+; CHECK-BE-NEXT:    addis r7, r2, .LC1@toc@ha
+; CHECK-BE-NEXT:    std r3, -32(r1)
 ; CHECK-BE-NEXT:    std r6, -8(r1)
 ; CHECK-BE-NEXT:    std r5, -16(r1)
+; CHECK-BE-NEXT:    addi r5, r1, -16
+; CHECK-BE-NEXT:    ld r3, .LC1@toc@l(r7)
 ; CHECK-BE-NEXT:    std r4, -24(r1)
-; CHECK-BE-NEXT:    std r3, -32(r1)
-; CHECK-BE-NEXT:    addi r3, r1, -32
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    addi r7, r1, -16
-; CHECK-BE-NEXT:    lxvd2x v3, 0, r3
-; CHECK-BE-NEXT:    addi r3, r4, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxvd2x v2, 0, r7
+; CHECK-BE-NEXT:    addi r4, r1, -32
+; CHECK-BE-NEXT:    lxvd2x v2, 0, r5
+; CHECK-BE-NEXT:    lxvd2x v3, 0, r4
 ; CHECK-BE-NEXT:    lxvw4x v4, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-NEXT:    blr
 %v10 = insertelement <4 x i64> undef, i64 %i1, i32 0
 %v11 = insertelement <4 x i64> %v10, i64 %i2, i32 1
 %v12 = insertelement <4 x i64> %v11, i64 %i3, i32 2
 %v13 = insertelement <4 x i64> %v12, i64 %i4, i32 3
 %v2 = trunc <4 x i64> %v13 to <4 x i16>

llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

 ; ALL-NEXT:    blr
   %result = add <2 x i64> %x, %y
   ret <2 x i64> %result
 }
 
 define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
 ; VSX-LABEL: increment_by_one:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; VSX-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; VSX-NEXT:    addis 3, 2, .LC0@toc@ha
+; VSX-NEXT:    ld 3, .LC0@toc@l(3)
 ; VSX-NEXT:    lxvd2x 35, 0, 3
 ; VSX-NEXT:    vaddudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: increment_by_one:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; NOVSX-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; NOVSX-NEXT:    addis 3, 2, .LC0@toc@ha
+; NOVSX-NEXT:    ld 3, .LC0@toc@l(3)
 ; NOVSX-NEXT:    lvx 3, 0, 3
 ; NOVSX-NEXT:    vaddudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = add <2 x i64> %x, <i64 1, i64 1>
   ret <2 x i64> %result
 }
 
 define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {

 ; VSX-LABEL: decrement_by_one:
 ; VSX:       # %bb.0:
 ; VSX-NEXT:    xxleqv 35, 35, 35
 ; VSX-NEXT:    vsubudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: decrement_by_one:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; NOVSX-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; NOVSX-NEXT:    addis 3, 2, .LC1@toc@ha
+; NOVSX-NEXT:    ld 3, .LC1@toc@l(3)
 ; NOVSX-NEXT:    lvx 3, 0, 3
 ; NOVSX-NEXT:    vsubudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = sub <2 x i64> %x, <i64 -1, i64 -1>
   ret <2 x i64> %result
 }
 
 define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {

llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll

 ; ALL-NEXT:    blr
   %result = add <1 x i128> %x, %y
   ret <1 x i128> %result
 }
 
 define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
 ; VSX-LABEL: increment_by_one:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; VSX-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; VSX-NEXT:    addis 3, 2, .LC0@toc@ha
+; VSX-NEXT:    ld 3, .LC0@toc@l(3)
 ; VSX-NEXT:    lxvd2x 35, 0, 3
 ; VSX-NEXT:    vadduqm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: increment_by_one:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; NOVSX-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; NOVSX-NEXT:    addis 3, 2, .LC0@toc@ha
+; NOVSX-NEXT:    ld 3, .LC0@toc@l(3)
 ; NOVSX-NEXT:    lvx 3, 0, 3
 ; NOVSX-NEXT:    vadduqm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = add <1 x i128> %x, <i128 1>
   ret <1 x i128> %result
 }
 
 define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {

 ; ALL-NEXT:    blr
   %result = sub <1 x i128> %x, %y
   ret <1 x i128> %result
 }
 
 define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
 ; VSX-LABEL: decrement_by_one:
 ; VSX:       # %bb.0:
-; VSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; VSX-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; VSX-NEXT:    addis 3, 2, .LC1@toc@ha
+; VSX-NEXT:    ld 3, .LC1@toc@l(3)
 ; VSX-NEXT:    lxvd2x 35, 0, 3
 ; VSX-NEXT:    vsubuqm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: decrement_by_one:
 ; NOVSX:       # %bb.0:
-; NOVSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; NOVSX-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; NOVSX-NEXT:    addis 3, 2, .LC1@toc@ha
+; NOVSX-NEXT:    ld 3, .LC1@toc@l(3)
 ; NOVSX-NEXT:    lvx 3, 0, 3
 ; NOVSX-NEXT:    vsubuqm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %result = sub <1 x i128> %x, <i128 1>
   ret <1 x i128> %result
 }
 
 define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x float>
   ret <4 x float> %1

 ; CHECK-P9-NEXT:    xvcvuxwsp vs0, v4
 ; CHECK-P9-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = uitofp <8 x i16> %a to <8 x float>
   store <8 x float> %0, <8 x float>* %agg.result, align 32
   ret void
 }
 
 define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI3_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
 ; CHECK-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P8-NEXT:    lvx v4, 0, r4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI3_1@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    li r5, 16
-; CHECK-P8-NEXT:    lvx v0, 0, r6
-; CHECK-P8-NEXT:    li r6, 32
-; CHECK-P8-NEXT:    lvx v5, r4, r5
+; CHECK-P8-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-P8-NEXT:    lvx v0, r4, r6
 ; CHECK-P8-NEXT:    li r4, 48
+; CHECK-P8-NEXT:    lvx v2, 0, r5
+; CHECK-P8-NEXT:    lvx v5, r5, r6
+; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    vperm v1, v3, v4, v2
-; CHECK-P8-NEXT:    vperm v2, v3, v5, v2
-; CHECK-P8-NEXT:    vperm v5, v3, v5, v0
-; CHECK-P8-NEXT:    vperm v3, v3, v4, v0
+; CHECK-P8-NEXT:    vperm v6, v3, v0, v5
+; CHECK-P8-NEXT:    vperm v2, v3, v0, v2
+; CHECK-P8-NEXT:    vperm v3, v3, v4, v5
 ; CHECK-P8-NEXT:    xvcvuxwsp v4, v1
+; CHECK-P8-NEXT:    xvcvuxwsp v5, v6
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
-; CHECK-P8-NEXT:    xvcvuxwsp v5, v5
 ; CHECK-P8-NEXT:    xvcvuxwsp v3, v3
 ; CHECK-P8-NEXT:    stvx v4, 0, r3
-; CHECK-P8-NEXT:    stvx v2, r3, r6
 ; CHECK-P8-NEXT:    stvx v5, r3, r4
-; CHECK-P8-NEXT:    stvx v3, r3, r5
+; CHECK-P8-NEXT:    stvx v2, r3, r5
+; CHECK-P8-NEXT:    stvx v3, r3, r6
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv v2, 16(r4)
-; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v5, v5, v5
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-P9-NEXT:    lxvx v4, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-P9-NEXT:    vperm v0, v5, v3, v4
-; CHECK-P9-NEXT:    xvcvuxwsp vs0, v0
-; CHECK-P9-NEXT:    lxvx v0, 0, r4
-; CHECK-P9-NEXT:    vperm v3, v5, v3, v0
+; CHECK-P9-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-P9-NEXT:    lxv v2, 0(r4)
+; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-P9-NEXT:    lxvx v3, 0, r5
+; CHECK-P9-NEXT:    lxv v0, 16(r5)
+; CHECK-P9-NEXT:    vperm v5, v4, v2, v3
+; CHECK-P9-NEXT:    vperm v2, v4, v2, v0
+; CHECK-P9-NEXT:    xvcvuxwsp vs0, v5
+; CHECK-P9-NEXT:    lxv v5, 16(r4)
+; CHECK-P9-NEXT:    xvcvuxwsp vs1, v2
+; CHECK-P9-NEXT:    vperm v2, v4, v5, v3
+; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xvcvuxwsp vs1, v3
-; CHECK-P9-NEXT:    vperm v3, v5, v2, v4
-; CHECK-P9-NEXT:    vperm v2, v5, v2, v0
-; CHECK-P9-NEXT:    xvcvuxwsp vs2, v3
+; CHECK-P9-NEXT:    xvcvuxwsp vs2, v2
+; CHECK-P9-NEXT:    vperm v2, v4, v5, v0
 ; CHECK-P9-NEXT:    xvcvuxwsp vs3, v2
-; CHECK-P9-NEXT:    stxv vs1, 16(r3)
-; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
+; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv v2, 16(r4)
-; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v5, v5, v5
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v0, v3, v5, v4
-; CHECK-BE-NEXT:    xvcvuxwsp vs0, v0
-; CHECK-BE-NEXT:    lxvx v0, 0, r4
-; CHECK-BE-NEXT:    vperm v3, v5, v3, v0
+; CHECK-BE-NEXT:    addis r5, r2, .LC2@toc@ha
+; CHECK-BE-NEXT:    lxv v2, 0(r4)
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    ld r5, .LC2@toc@l(r5)
+; CHECK-BE-NEXT:    lxvx v3, 0, r5
+; CHECK-BE-NEXT:    lxv v0, 16(r5)
+; CHECK-BE-NEXT:    vperm v5, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v0
+; CHECK-BE-NEXT:    xvcvuxwsp vs0, v5
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    xvcvuxwsp vs1, v2
+; CHECK-BE-NEXT:    vperm v2, v5, v4, v3
+; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
-; CHECK-BE-NEXT:    xvcvuxwsp vs1, v3
-; CHECK-BE-NEXT:    vperm v3, v2, v5, v4
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v0
-; CHECK-BE-NEXT:    xvcvuxwsp vs2, v3
+; CHECK-BE-NEXT:    xvcvuxwsp vs2, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v5, v0
 ; CHECK-BE-NEXT:    xvcvuxwsp vs3, v2
-; CHECK-BE-NEXT:    stxv vs1, 16(r3)
-; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
+; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x i16>, <16 x i16>* %0, align 32
   %1 = uitofp <16 x i16> %a to <16 x float>
   store <16 x float> %1, <16 x float>* %agg.result, align 64
   ret void
 }
 

 ; CHECK-P9-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v2
 ; CHECK-BE-NEXT:    vextsh2w v3, v3
 ; CHECK-BE-NEXT:    vextsh2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)

 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 16(r4)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC4@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v5, v5, v5
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v4, 0, r4
 ; CHECK-BE-NEXT:    vperm v0, v5, v3, v4
 ; CHECK-BE-NEXT:    vperm v4, v5, v2, v4
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v2
 ; CHECK-BE-NEXT:    vextsh2w v0, v0
 ; CHECK-BE-NEXT:    vextsh2w v4, v4
 ; CHECK-BE-NEXT:    vextsh2w v3, v3

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v2, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI1_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC1@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
 ; CHECK-P8-NEXT:    mtvsrd v2, r4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r6, .LCPI1_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
-; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    lvx v3, r5, r6
+; CHECK-P8-NEXT:    lvx v5, 0, r5
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v5
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    stxvd2x vs0, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void
 }
 
 define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_2@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC2@toc@ha
+; CHECK-P8-NEXT:    li r5, 16
+; CHECK-P8-NEXT:    li r6, 48
+; CHECK-P8-NEXT:    li r7, 32
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_2@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_3@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_1@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r4
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    li r5, 32
+; CHECK-P8-NEXT:    lvx v5, r4, r5
+; CHECK-P8-NEXT:    lvx v0, r4, r6
+; CHECK-P8-NEXT:    lvx v1, r4, r7
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
 ; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v1
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v5
 ; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
 ; CHECK-P8-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r5
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = uitofp <8 x i16> %a to <8 x double>
   store <8 x double> %0, <8 x double>* %agg.result, align 64
   ret void
 }
 
 define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI3_2@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC3@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
+; CHECK-P8-NEXT:    li r7, 32
 ; CHECK-P8-NEXT:    lvx v4, 0, r4
 ; CHECK-P8-NEXT:    xxlxor v3, v3, v3
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI3_2@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    lvx v5, 0, r6
-; CHECK-P8-NEXT:    li r6, 16
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_1@toc@ha
+; CHECK-P8-NEXT:    li r8, 96
+; CHECK-P8-NEXT:    ld r5, .LC3@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v0, r4, r6
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_1@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_3@toc@l
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    li r5, 96
-; CHECK-P8-NEXT:    lvx v8, 0, r4
+; CHECK-P8-NEXT:    li r4, 48
+; CHECK-P8-NEXT:    lvx v2, 0, r5
+; CHECK-P8-NEXT:    lvx v5, r5, r6
+; CHECK-P8-NEXT:    lvx v1, r5, r7
+; CHECK-P8-NEXT:    lvx v7, r5, r4
+; CHECK-P8-NEXT:    li r5, 112
 ; CHECK-P8-NEXT:    vperm v6, v3, v4, v2
-; CHECK-P8-NEXT:    li r4, 112
-; CHECK-P8-NEXT:    vperm v7, v3, v4, v5
-; CHECK-P8-NEXT:    vperm v2, v3, v0, v2
+; CHECK-P8-NEXT:    vperm v8, v3, v0, v5
 ; CHECK-P8-NEXT:    vperm v9, v3, v0, v1
-; CHECK-P8-NEXT:    vperm v5, v3, v0, v5
-; CHECK-P8-NEXT:    vperm v0, v3, v0, v8
+; CHECK-P8-NEXT:    vperm v2, v3, v0, v2
+; CHECK-P8-NEXT:    vperm v0, v3, v0, v7
 ; CHECK-P8-NEXT:    vperm v1, v3, v4, v1
-; CHECK-P8-NEXT:    vperm v3, v3, v4, v8
-; CHECK-P8-NEXT:    xvcvuxddp vs1, v2
-; CHECK-P8-NEXT:    xvcvuxddp vs4, v9
-; CHECK-P8-NEXT:    xvcvuxddp vs2, v5
-; CHECK-P8-NEXT:    xvcvuxddp vs3, v0
-; CHECK-P8-NEXT:    xvcvuxddp vs0, v7
+; CHECK-P8-NEXT:    vperm v5, v3, v4, v5
+; CHECK-P8-NEXT:    vperm v3, v3, v4, v7
+; CHECK-P8-NEXT:    xvcvuxddp vs1, v9
+; CHECK-P8-NEXT:    xvcvuxddp vs0, v8
+; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
+; CHECK-P8-NEXT:    xvcvuxddp vs3, v1
+; CHECK-P8-NEXT:    xvcvuxddp vs4, v2
 ; CHECK-P8-NEXT:    xvcvuxddp vs5, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs6, v6
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    xvcvuxddp vs7, v1
-; CHECK-P8-NEXT:    xxswapd vs4, vs4
+; CHECK-P8-NEXT:    xvcvuxddp vs7, v5
+; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    xxswapd vs0, vs0
+; CHECK-P8-NEXT:    xxswapd vs4, vs4
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
 ; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
-; CHECK-P8-NEXT:    li r4, 80
-; CHECK-P8-NEXT:    li r5, 64
-; CHECK-P8-NEXT:    xxswapd vs2, vs7
-; CHECK-P8-NEXT:    xxswapd vs3, vs6
-; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
+; CHECK-P8-NEXT:    li r5, 80
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r8
+; CHECK-P8-NEXT:    xxswapd vs2, vs6
+; CHECK-P8-NEXT:    li r8, 64
+; CHECK-P8-NEXT:    xxswapd vs1, vs7
 ; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r6
-; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
+; CHECK-P8-NEXT:    stxvd2x vs4, r3, r8
+; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs2, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 16(r4)
 ; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v5, v5, v5
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC3@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v4, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
 ; CHECK-P9-NEXT:    vperm v0, v5, v3, v4
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v0
-; CHECK-P9-NEXT:    lxvx v0, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-P9-NEXT:    lxv v0, 16(r4)
 ; CHECK-P9-NEXT:    vperm v1, v5, v3, v0
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v1
-; CHECK-P9-NEXT:    lxvx v1, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_3@toc@l
+; CHECK-P9-NEXT:    lxv v1, 32(r4)
 ; CHECK-P9-NEXT:    vperm v6, v5, v3, v1
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs2, v6
-; CHECK-P9-NEXT:    lxvx v6, 0, r4
+; CHECK-P9-NEXT:    lxv v6, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v5, v3, v6
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs3, v3
 ; CHECK-P9-NEXT:    vperm v3, v5, v2, v4
 ; CHECK-P9-NEXT:    xvcvuxddp vs4, v3
 ; CHECK-P9-NEXT:    vperm v3, v5, v2, v0
 ; CHECK-P9-NEXT:    xvcvuxddp vs5, v3
 ; CHECK-P9-NEXT:    vperm v3, v5, v2, v1
 ; CHECK-P9-NEXT:    vperm v2, v5, v2, v6
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs6, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs7, v2
 ; CHECK-P9-NEXT:    stxv vs4, 64(r3)
 ; CHECK-P9-NEXT:    stxv vs5, 80(r3)
 ; CHECK-P9-NEXT:    stxv vs7, 112(r3)
 ; CHECK-P9-NEXT:    stxv vs6, 96(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 16(r4)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v5, v5, v5
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
 ; CHECK-BE-NEXT:    vperm v0, v3, v5, v4
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v0
-; CHECK-BE-NEXT:    lxvx v0, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-BE-NEXT:    lxv v0, 16(r4)
 ; CHECK-BE-NEXT:    vperm v1, v5, v3, v0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v1
-; CHECK-BE-NEXT:    lxvx v1, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
+; CHECK-BE-NEXT:    lxv v1, 32(r4)
 ; CHECK-BE-NEXT:    vperm v6, v5, v3, v1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs2, v6
-; CHECK-BE-NEXT:    lxvx v6, 0, r4
+; CHECK-BE-NEXT:    lxv v6, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v5, v3, v6
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs3, v3
 ; CHECK-BE-NEXT:    vperm v3, v2, v5, v4
 ; CHECK-BE-NEXT:    xvcvuxddp vs4, v3
 ; CHECK-BE-NEXT:    vperm v3, v5, v2, v0
 ; CHECK-BE-NEXT:    xvcvuxddp vs5, v3
 ; CHECK-BE-NEXT:    vperm v3, v5, v2, v1
entry:
   %1 = uitofp <16 x i16> %a to <16 x double>
   store <16 x double> %1, <16 x double>* %agg.result, align 128
   ret void
 }
 
 define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC5@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v3, r3
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC5@toc@l(r5)
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI5_2@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC6@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
+; CHECK-P8-NEXT:    addis r7, r2, .LC7@toc@ha
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI5_2@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    ld r5, .LC6@toc@l(r5)
+; CHECK-P8-NEXT:    ld r7, .LC7@toc@l(r7)
+; CHECK-P8-NEXT:    lvx v2, r5, r6
 ; CHECK-P8-NEXT:    lvx v4, 0, r5
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r7
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_1@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = sitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void
 }
 
 define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_2@toc@ha
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_3@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_2@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI6_3@toc@l
-; CHECK-P8-NEXT:    lvx v4, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_4@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC8@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC9@toc@ha
+; CHECK-P8-NEXT:    li r6, 32
+; CHECK-P8-NEXT:    li r7, 16
+; CHECK-P8-NEXT:    li r8, 48
+; CHECK-P8-NEXT:    ld r4, .LC8@toc@l(r4)
+; CHECK-P8-NEXT:    ld r5, .LC9@toc@l(r5)
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    lvx v5, 0, r6
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_4@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_1@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r5
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    li r5, 32
+; CHECK-P8-NEXT:    lvx v4, r4, r6
+; CHECK-P8-NEXT:    lvx v5, r4, r7
+; CHECK-P8-NEXT:    lvx v0, r4, r8
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v0
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v3, v3, v0
-; CHECK-P8-NEXT:    vsrad v2, v2, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0
-; CHECK-P8-NEXT:    xvcvsxddp vs2, v2
+; CHECK-P8-NEXT:    vsrad v2, v2, v0
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v5
+; CHECK-P8-NEXT:    xvcvsxddp vs2, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs3, v4
-; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r8
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r7
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC6@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vextsh2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC6@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_1@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = sitofp <8 x i16> %a to <8 x double>
   store <8 x double> %0, <8 x double>* %agg.result, align 64
   ret void
 }
 
 define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_2@toc@ha
-; CHECK-P8-NEXT:    lvx v4, 0, r4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_2@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_3@toc@ha
-; CHECK-P8-NEXT:    lvx v3, 0, r6
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_4@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_3@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_4@toc@l
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    lvx v0, 0, r6
+; CHECK-P8-NEXT:    addis r5, r2, .LC10@toc@ha
 ; CHECK-P8-NEXT:    li r6, 16
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_1@toc@ha
-; CHECK-P8-NEXT:    lvx v7, r4, r6
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_1@toc@l
-; CHECK-P8-NEXT:    vperm v1, v4, v4, v2
+; CHECK-P8-NEXT:    li r7, 32
+; CHECK-P8-NEXT:    addis r8, r2, .LC11@toc@ha
+; CHECK-P8-NEXT:    li r9, 48
+; CHECK-P8-NEXT:    lvx v6, 0, r4
+; CHECK-P8-NEXT:    ld r5, .LC10@toc@l(r5)
+; CHECK-P8-NEXT:    ld r8, .LC11@toc@l(r8)
+; CHECK-P8-NEXT:    lvx v3, r4, r6
 ; CHECK-P8-NEXT:    li r4, 112
-; CHECK-P8-NEXT:    vperm v6, v4, v4, v3
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r5
+; CHECK-P8-NEXT:    lvx v2, r5, r6
+; CHECK-P8-NEXT:    lvx v4, r5, r7
+; CHECK-P8-NEXT:    lvx v5, r5, r9
+; CHECK-P8-NEXT:    lvx v0, 0, r5
 ; CHECK-P8-NEXT:    li r5, 96
-; CHECK-P8-NEXT:    vperm v8, v4, v4, v5
-; CHECK-P8-NEXT:    vperm v4, v4, v4, v0
-; CHECK-P8-NEXT:    vperm v5, v7, v7, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs0
-; CHECK-P8-NEXT:    vperm v0, v7, v7, v0
-; CHECK-P8-NEXT:    vperm v2, v7, v7, v2
-; CHECK-P8-NEXT:    vperm v3, v7, v7, v3
-; CHECK-P8-NEXT:    vsld v1, v1, v9
-; CHECK-P8-NEXT:    vsld v6, v6, v9
-; CHECK-P8-NEXT:    vsld v5, v5, v9
-; CHECK-P8-NEXT:    vsld v0, v0, v9
-; CHECK-P8-NEXT:    vsld v2, v2, v9
-; CHECK-P8-NEXT:    vsld v3, v3, v9
-; CHECK-P8-NEXT:    vsrad v5, v5, v9
-; CHECK-P8-NEXT:    vsrad v0, v0, v9
-; CHECK-P8-NEXT:    vsld v7, v8, v9
-; CHECK-P8-NEXT:    vsld v4, v4, v9
-; CHECK-P8-NEXT:    vsrad v2, v2, v9
-; CHECK-P8-NEXT:    vsrad v3, v3, v9
-; CHECK-P8-NEXT:    xvcvsxddp vs2, v5
-; CHECK-P8-NEXT:    xvcvsxddp vs3, v0
-; CHECK-P8-NEXT:    vsrad v1, v1, v9
-; CHECK-P8-NEXT:    vsrad v6, v6, v9
-; CHECK-P8-NEXT:    vsrad v7, v7, v9
-; CHECK-P8-NEXT:    vsrad v4, v4, v9
-; CHECK-P8-NEXT:    xvcvsxddp vs1, v2
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r8
+; CHECK-P8-NEXT:    vperm v1, v3, v3, v2
+; CHECK-P8-NEXT:    vperm v7, v3, v3, v4
+; CHECK-P8-NEXT:    xxswapd v10, vs0
+; CHECK-P8-NEXT:    vperm v8, v3, v3, v5
+; CHECK-P8-NEXT:    vperm v9, v6, v6, v0
+; CHECK-P8-NEXT:    vperm v2, v6, v6, v2
+; CHECK-P8-NEXT:    vperm v4, v6, v6, v4
+; CHECK-P8-NEXT:    vperm v5, v6, v6, v5
+; CHECK-P8-NEXT:    vperm v3, v3, v3, v0
+; CHECK-P8-NEXT:    vsld v0, v1, v10
+; CHECK-P8-NEXT:    vsld v1, v7, v10
+; CHECK-P8-NEXT:    vsld v6, v8, v10
+; CHECK-P8-NEXT:    vsrad v1, v1, v10
+; CHECK-P8-NEXT:    vsrad v6, v6, v10
+; CHECK-P8-NEXT:    vsld v7, v9, v10
+; CHECK-P8-NEXT:    vsld v2, v2, v10
+; CHECK-P8-NEXT:    vsld v4, v4, v10
+; CHECK-P8-NEXT:    vsld v5, v5, v10
+; CHECK-P8-NEXT:    vsld v3, v3, v10
+; CHECK-P8-NEXT:    xvcvsxddp vs1, v1
+; CHECK-P8-NEXT:    xvcvsxddp vs2, v6
+; CHECK-P8-NEXT:    vsrad v0, v0, v10
+; CHECK-P8-NEXT:    vsrad v7, v7, v10
+; CHECK-P8-NEXT:    vsrad v2, v2, v10
+; CHECK-P8-NEXT:    vsrad v4, v4, v10
+; CHECK-P8-NEXT:    vsrad v5, v5, v10
+; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    vsrad v3, v3, v10
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
+; CHECK-P8-NEXT:    xvcvsxddp vs0, v0
+; CHECK-P8-NEXT:    xvcvsxddp vs3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs4, v3
-; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    xvcvsxddp vs0, v7
-; CHECK-P8-NEXT:    xvcvsxddp vs5, v4
-; CHECK-P8-NEXT:    xvcvsxddp vs6, v1
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
 ; CHECK-P8-NEXT:    li r4, 80
-; CHECK-P8-NEXT:    xvcvsxddp vs7, v6
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
+; CHECK-P8-NEXT:    xvcvsxddp vs5, v5
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
 ; CHECK-P8-NEXT:    li r5, 64
-; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    xxswapd vs4, vs4
+; CHECK-P8-NEXT:    xvcvsxddp vs6, v7
+; CHECK-P8-NEXT:    xvcvsxddp vs7, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
+; CHECK-P8-NEXT:    xxswapd vs3, vs3
+; CHECK-P8-NEXT:    xxswapd vs4, vs4
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    xxswapd vs3, vs6
-; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    xxswapd vs2, vs7
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r6
-; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
+; CHECK-P8-NEXT:    stxvd2x vs0, r3, r4
+; CHECK-P8-NEXT:    xxswapd vs2, vs6
+; CHECK-P8-NEXT:    xxswapd vs1, vs7
+; CHECK-P8-NEXT:    stxvd2x vs4, r3, r5
+; CHECK-P8-NEXT:    stxvd2x vs5, r3, r9
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs2, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
+; CHECK-P9-NEXT:    addis r5, r2, .LC7@toc@ha
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
-; CHECK-P9-NEXT:    addi r5, r5, .LCPI7_0@toc@l
+; CHECK-P9-NEXT:    ld r5, .LC7@toc@l(r5)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r5
-; CHECK-P9-NEXT:    addis r5, r2, .LCPI7_1@toc@ha
-; CHECK-P9-NEXT:    addi r5, r5, .LCPI7_1@toc@l
-; CHECK-P9-NEXT:    lxvx v5, 0, r5
-; CHECK-P9-NEXT:    addis r5, r2, .LCPI7_2@toc@ha
+; CHECK-P9-NEXT:    lxv v5, 16(r5)
+; CHECK-P9-NEXT:    lxv v0, 32(r5)
+; CHECK-P9-NEXT:    lxv v1, 48(r5)
 ; CHECK-P9-NEXT:    vperm v4, v2, v2, v3
-; CHECK-P9-NEXT:    addi r5, r5, .LCPI7_2@toc@l
 ; CHECK-P9-NEXT:    vextsh2d v4, v4
-; CHECK-P9-NEXT:    lxvx v0, 0, r5
-; CHECK-P9-NEXT:    addis r5, r2, .LCPI7_3@toc@ha
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v4
 ; CHECK-P9-NEXT:    vperm v4, v2, v2, v5
-; CHECK-P9-NEXT:    addi r5, r5, .LCPI7_3@toc@l
-; CHECK-P9-NEXT:    lxvx v1, 0, r5
 ; CHECK-P9-NEXT:    vextsh2d v4, v4
+; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v4
 ; CHECK-P9-NEXT:    vperm v4, v2, v2, v0
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v1
-; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsh2d v4, v4
+; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs2, v4
 ; CHECK-P9-NEXT:    lxv v4, 16(r4)
-; CHECK-P9-NEXT:    stxv vs1, 16(r3)
-; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs3, v2
+; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vperm v2, v4, v4, v3
+; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
-; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    xvcvsxddp vs4, v2
 ; CHECK-P9-NEXT:    vperm v2, v4, v4, v5
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs5, v2
 ; CHECK-P9-NEXT:    vperm v2, v4, v4, v0
 ; CHECK-P9-NEXT:    stxv vs4, 64(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs6, v2
 ; CHECK-P9-NEXT:    vperm v2, v4, v4, v1
 ; CHECK-P9-NEXT:    stxv vs5, 80(r3)
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs7, v2
 ; CHECK-P9-NEXT:    stxv vs6, 96(r3)
 ; CHECK-P9-NEXT:    stxv vs7, 112(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    lxv v4, 0(r4)
-; CHECK-BE-NEXT:    lxv v1, 16(r4)
+; CHECK-BE-NEXT:    lxv v2, 16(r4)
+; CHECK-BE-NEXT:    lxv v3, 0(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LC7@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v5, v5, v5
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_2@toc@l
-; CHECK-BE-NEXT:    lxvx v2, 0, r5
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_1@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_1@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r5
-; CHECK-BE-NEXT:    vperm v0, v5, v4, v2
-; CHECK-BE-NEXT:    vperm v2, v5, v1, v2
-; CHECK-BE-NEXT:    vextsh2d v2, v2
+; CHECK-BE-NEXT:    ld r4, .LC7@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v4, 16(r4)
+; CHECK-BE-NEXT:    vperm v0, v5, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v5, v2, v4
 ; CHECK-BE-NEXT:    vextsh2d v0, v0
-; CHECK-BE-NEXT:    xvcvsxddp vs2, v2
-; CHECK-BE-NEXT:    vperm v2, v5, v1, v3
+; CHECK-BE-NEXT:    vextsh2d v4, v4
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v0
-; CHECK-BE-NEXT:    vperm v0, v5, v4, v3
-; CHECK-BE-NEXT:    vextsh2d v2, v2
-; CHECK-BE-NEXT:    vextsh2d v0, v0
-; CHECK-BE-NEXT:    xvcvsxddp vs3, v2
-; CHECK-BE-NEXT:    lxvx v2, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-BE-NEXT:    xvcvsxddp vs1, v0
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_3@toc@l
+; CHECK-BE-NEXT:    lxv v0, 48(r4)
+; CHECK-BE-NEXT:    xvcvsxddp vs2, v4
+; CHECK-BE-NEXT:    vperm v4, v5, v2, v0
+; CHECK-BE-NEXT:    vperm v1, v5, v3, v0
 ; CHECK-BE-NEXT:    stxv vs2, 80(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
-; CHECK-BE-NEXT:    vperm v3, v4, v4, v2
-; CHECK-BE-NEXT:    vperm v2, v1, v1, v2
+; CHECK-BE-NEXT:    vextsh2d v4, v4
+; CHECK-BE-NEXT:    vextsh2d v1, v1
+; CHECK-BE-NEXT:    xvcvsxddp vs3, v4
+; CHECK-BE-NEXT:    lxvx v4, 0, r4
+; CHECK-BE-NEXT:    xvcvsxddp vs1, v1
+; CHECK-BE-NEXT:    vperm v5, v3, v3, v4
 ; CHECK-BE-NEXT:    stxv vs3, 112(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
-; CHECK-BE-NEXT:    vextsh2d v3, v3
-; CHECK-BE-NEXT:    vextsh2d v2, v2
-; CHECK-BE-NEXT:    xvcvsxddp vs4, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    xvcvsxddp vs6, v2
-; CHECK-BE-NEXT:    vperm v4, v4, v4, v3
-; CHECK-BE-NEXT:    vperm v2, v1, v1, v3
-; CHECK-BE-NEXT:    stxv vs6, 64(r3)
+; CHECK-BE-NEXT:    vextsh2d v5, v5
+; CHECK-BE-NEXT:    xvcvsxddp vs4, v5
+; CHECK-BE-NEXT:    lxv v5, 32(r4)
+; CHECK-BE-NEXT:    vperm v3, v3, v3, v5
 ; CHECK-BE-NEXT:    stxv vs4, 0(r3)
-; CHECK-BE-NEXT:    vextsh2d v4, v4
+; CHECK-BE-NEXT:    vextsh2d v3, v3
+; CHECK-BE-NEXT:    xvcvsxddp vs5, v3
+; CHECK-BE-NEXT:    vperm v3, v2, v2, v4
+; CHECK-BE-NEXT:    vperm v2, v2, v2, v5
+; CHECK-BE-NEXT:    stxv vs5, 32(r3)
+; CHECK-BE-NEXT:    vextsh2d v3, v3
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
-; CHECK-BE-NEXT:    xvcvsxddp vs5, v4
+; CHECK-BE-NEXT:    xvcvsxddp vs6, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs7, v2
 ; CHECK-BE-NEXT:    stxv vs7, 96(r3)
-; CHECK-BE-NEXT:    stxv vs5, 32(r3)
+; CHECK-BE-NEXT:    stxv vs6, 64(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x i16>, <16 x i16>* %0, align 32
   %1 = sitofp <16 x i16> %a to <16 x double>
   store <16 x double> %1, <16 x double>* %agg.result, align 128
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

entry:
   %1 = uitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }
 
 define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v2, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI1_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI2_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC1@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
 ; CHECK-P8-NEXT:    mtvsrd v2, r4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r6, .LCPI2_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
-; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    lvx v3, r5, r6
+; CHECK-P8-NEXT:    lvx v5, 0, r5
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v5
 ; CHECK-P8-NEXT:    xvcvuxwsp v3, v3
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P8-NEXT:    stvx v3, 0, r3
-; CHECK-P8-NEXT:    stvx v2, r3, r4
+; CHECK-P8-NEXT:    stvx v2, r3, r6
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_1@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxwsp vs0, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <8 x i8>
   %1 = uitofp <8 x i8> %0 to <8 x float>
   store <8 x float> %1, <8 x float>* %agg.result, align 32
   ret void
 }
 
 define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_2@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC2@toc@ha
+; CHECK-P8-NEXT:    li r5, 48
+; CHECK-P8-NEXT:    li r6, 32
+; CHECK-P8-NEXT:    li r7, 16
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_2@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC2@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_3@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_1@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r4
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
+; CHECK-P8-NEXT:    lvx v5, r4, r5
+; CHECK-P8-NEXT:    lvx v0, r4, r6
+; CHECK-P8-NEXT:    lvx v1, r4, r7
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
 ; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v1
-; CHECK-P8-NEXT:    xvcvuxwsp v4, v5
 ; CHECK-P8-NEXT:    xvcvuxwsp v3, v3
+; CHECK-P8-NEXT:    xvcvuxwsp v4, v5
 ; CHECK-P8-NEXT:    xvcvuxwsp v5, v0
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
-; CHECK-P8-NEXT:    stvx v4, r3, r5
-; CHECK-P8-NEXT:    stvx v3, 0, r3
-; CHECK-P8-NEXT:    stvx v5, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stvx v2, r3, r4
+; CHECK-P8-NEXT:    stvx v3, r3, r5
+; CHECK-P8-NEXT:    stvx v4, 0, r3
+; CHECK-P8-NEXT:    stvx v5, r3, r6
+; CHECK-P8-NEXT:    stvx v2, r3, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxwsp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxwsp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    xvcvuxwsp vs2, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    xvcvuxwsp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs2, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
entry:
   %1 = sitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }
 
 define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC3@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v3, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC3@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vspltisw v3, 12
 ; CHECK-P8-NEXT:    vadduwm v3, v3, v3
 ; CHECK-P8-NEXT:    vslw v2, v2, v3
 ; CHECK-P8-NEXT:    vsraw v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = sitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC4@toc@ha
+; CHECK-P8-NEXT:    li r6, 16
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
 ; CHECK-P8-NEXT:    vspltisw v5, 12
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI6_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC4@toc@l(r5)
+; CHECK-P8-NEXT:    lvx v2, r5, r6
 ; CHECK-P8-NEXT:    lvx v4, 0, r5
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-P8-NEXT:    vadduwm v4, v5, v5
 ; CHECK-P8-NEXT:    vslw v2, v2, v4
 ; CHECK-P8-NEXT:    vslw v3, v3, v4
 ; CHECK-P8-NEXT:    vsraw v2, v2, v4
 ; CHECK-P8-NEXT:    vsraw v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    xvcvsxwsp v3, v3
-; CHECK-P8-NEXT:    stvx v2, 0, r3
-; CHECK-P8-NEXT:    stvx v3, r3, r4
+; CHECK-P8-NEXT:    stvx v2, r3, r6
+; CHECK-P8-NEXT:    stvx v3, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2w v3, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsb2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    ld r4, .LC4@toc@l(r4)
+; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsb2w v3, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <8 x i8>
   %1 = sitofp <8 x i8> %0 to <8 x float>
   store <8 x float> %1, <8 x float>* %agg.result, align 32
   ret void
 }
 
 define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_2@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-P8-NEXT:    li r5, 48
+; CHECK-P8-NEXT:    li r6, 32
+; CHECK-P8-NEXT:    li r7, 16
 ; CHECK-P8-NEXT:    vspltisw v1, 12
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_2@toc@l
-; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-P8-NEXT:    lvx v4, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_3@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_1@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-P8-NEXT:    lvx v3, r4, r5
+; CHECK-P8-NEXT:    lvx v4, r4, r6
 ; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    lvx v0, 0, r5
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    li r5, 32
+; CHECK-P8-NEXT:    lvx v0, r4, r7
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v0
 ; CHECK-P8-NEXT:    vadduwm v0, v1, v1
 ; CHECK-P8-NEXT:    vslw v3, v3, v0
 ; CHECK-P8-NEXT:    vslw v4, v4, v0
 ; CHECK-P8-NEXT:    vslw v5, v5, v0
 ; CHECK-P8-NEXT:    vslw v2, v2, v0
 ; CHECK-P8-NEXT:    vsraw v3, v3, v0
 ; CHECK-P8-NEXT:    vsraw v4, v4, v0
 ; CHECK-P8-NEXT:    vsraw v5, v5, v0
 ; CHECK-P8-NEXT:    vsraw v2, v2, v0
 ; CHECK-P8-NEXT:    xvcvsxwsp v3, v3
 ; CHECK-P8-NEXT:    xvcvsxwsp v4, v4
 ; CHECK-P8-NEXT:    xvcvsxwsp v5, v5
 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    stvx v3, 0, r3
-; CHECK-P8-NEXT:    stvx v4, r3, r5
-; CHECK-P8-NEXT:    stvx v5, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stvx v2, r3, r4
+; CHECK-P8-NEXT:    stvx v4, r3, r6
+; CHECK-P8-NEXT:    stvx v5, r3, r5
+; CHECK-P8-NEXT:    stvx v2, r3, r7
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_1@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2w v3, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsb2w v3, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vextsb2w v3, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs2, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsb2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC5@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsb2w v3, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsb2w v3, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
 ; CHECK-BE-NEXT:    vextsb2w v3, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs2, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = sitofp <16 x i8> %a to <16 x float>
   store <16 x float> %0, <16 x float>* %agg.result, align 64
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-BE
 
 define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v2, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-P9-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P9-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI1_1@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC1@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v2, r4
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI1_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r6, .LCPI1_1@toc@l
+; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    ld r5, .LC1@toc@l(r5)
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r5
-; CHECK-P8-NEXT:    lvx v5, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    lvx v5, r5, r4
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v5
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    stxvd2x vs0, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI1_1@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC1@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC1@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void
 }
 
 define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test8elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI2_2@toc@ha
-; CHECK-P8-NEXT:    mtvsrd v2, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_3@toc@l
-; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    lvx v3, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI2_2@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI2_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI2_1@toc@l
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
-; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
-; CHECK-P8-NEXT:    vperm v2, v4, v2, v1
-; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
+; CHECK-P8-NEXT:    addis r5, r2, .LC2@toc@ha
+; CHECK-P8-NEXT:    li r6, 32
+; CHECK-P8-NEXT:    li r7, 48
+; CHECK-P8-NEXT:    mtvsrd v4, r4
+; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    ld r5, .LC2@toc@l(r5)
+; CHECK-P8-NEXT:    xxlxor v2, v2, v2
+; CHECK-P8-NEXT:    lvx v3, r5, r6
+; CHECK-P8-NEXT:    lvx v5, r5, r7
+; CHECK-P8-NEXT:    lvx v0, 0, r5
+; CHECK-P8-NEXT:    lvx v1, r5, r4
+; CHECK-P8-NEXT:    vperm v3, v2, v4, v3
+; CHECK-P8-NEXT:    vperm v5, v2, v4, v5
+; CHECK-P8-NEXT:    vperm v0, v2, v4, v0
+; CHECK-P8-NEXT:    vperm v2, v2, v4, v1
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs1, v5
+; CHECK-P8-NEXT:    xvcvuxddp vs2, v0
 ; CHECK-P8-NEXT:    xvcvuxddp vs3, v2
-; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
 ; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_1@toc@l
+; CHECK-P9-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC2@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC2@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_2@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <8 x i8>
   %1 = uitofp <8 x i8> %0 to <8 x double>
   store <8 x double> %1, <8 x double>* %agg.result, align 64
   ret void
 }
 
 define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test16elt:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_1@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC3@toc@ha
+; CHECK-P8-NEXT:    li r5, 112
+; CHECK-P8-NEXT:    li r6, 48
+; CHECK-P8-NEXT:    li r7, 32
+; CHECK-P8-NEXT:    li r8, 16
+; CHECK-P8-NEXT:    li r9, 80
+; CHECK-P8-NEXT:    li r10, 96
+; CHECK-P8-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-P8-NEXT:    li r11, 64
 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_1@toc@l
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_4@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_2@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_4@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_7@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_6@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_7@toc@l
+; CHECK-P8-NEXT:    lvx v5, r4, r5
+; CHECK-P8-NEXT:    lvx v0, r4, r6
+; CHECK-P8-NEXT:    lvx v1, r4, r7
+; CHECK-P8-NEXT:    lvx v6, r4, r8
+; CHECK-P8-NEXT:    lvx v7, r4, r9
+; CHECK-P8-NEXT:    lvx v8, r4, r10
+; CHECK-P8-NEXT:    lvx v9, r4, r11
 ; CHECK-P8-NEXT:    vperm v3, v4, v2, v3
-; CHECK-P8-NEXT:    lvx v6, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
-; CHECK-P8-NEXT:    lvx v7, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI3_3@toc@ha
 ; CHECK-P8-NEXT:    vperm v5, v4, v2, v5
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI3_5@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI3_3@toc@l
 ; CHECK-P8-NEXT:    vperm v0, v4, v2, v0
-; CHECK-P8-NEXT:    lvx v8, 0, r4
-; CHECK-P8-NEXT:    lvx v9, 0, r5
 ; CHECK-P8-NEXT:    vperm v1, v4, v2, v1
-; CHECK-P8-NEXT:    li r4, 112
-; CHECK-P8-NEXT:    li r5, 96
 ; CHECK-P8-NEXT:    vperm v6, v4, v2, v6
 ; CHECK-P8-NEXT:    vperm v7, v4, v2, v7
 ; CHECK-P8-NEXT:    vperm v8, v4, v2, v8
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v9
-; CHECK-P8-NEXT:    xvcvuxddp vs0, v0
-; CHECK-P8-NEXT:    xvcvuxddp vs1, v1
-; CHECK-P8-NEXT:    xvcvuxddp vs2, v6
+; CHECK-P8-NEXT:    xvcvuxddp vs0, v3
+; CHECK-P8-NEXT:    xvcvuxddp vs1, v5
+; CHECK-P8-NEXT:    xvcvuxddp vs2, v1
 ; CHECK-P8-NEXT:    xvcvuxddp vs3, v7
 ; CHECK-P8-NEXT:    xvcvuxddp vs4, v8
 ; CHECK-P8-NEXT:    xvcvuxddp vs5, v2
-; CHECK-P8-NEXT:    xvcvuxddp vs6, v3
+; CHECK-P8-NEXT:    xvcvuxddp vs6, v6
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    xvcvuxddp vs7, v5
+; CHECK-P8-NEXT:    xvcvuxddp vs7, v0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
+; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
 ; CHECK-P8-NEXT:    xxswapd vs4, vs4
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
-; CHECK-P8-NEXT:    li r4, 80
-; CHECK-P8-NEXT:    li r5, 64
-; CHECK-P8-NEXT:    xxswapd vs2, vs7
-; CHECK-P8-NEXT:    xxswapd vs3, vs6
-; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
+; CHECK-P8-NEXT:    xxswapd vs6, vs6
+; CHECK-P8-NEXT:    xxswapd vs7, vs7
+; CHECK-P8-NEXT:    stxvd2x vs4, r3, r10
+; CHECK-P8-NEXT:    stxvd2x vs5, r3, r9
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r11
+; CHECK-P8-NEXT:    stxvd2x vs6, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs7, r3, r8
+; CHECK-P8-NEXT:    stxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_2@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    addis r4, r2, .LC3@toc@ha
+; CHECK-P9-NEXT:    xxlxor v3, v3, v3
+; CHECK-P9-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v4, 112(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
+; CHECK-P9-NEXT:    xvcvuxddp vs0, v4
+; CHECK-P9-NEXT:    lxv v4, 48(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_3@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs1, v4
+; CHECK-P9-NEXT:    lxv v4, 32(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_4@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_4@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs2, v4
+; CHECK-P9-NEXT:    lxv v4, 16(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs3, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_5@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs3, v4
+; CHECK-P9-NEXT:    lxv v4, 80(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs4, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_6@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs4, v4
+; CHECK-P9-NEXT:    lxv v4, 64(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs4, 64(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs5, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI3_7@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI3_7@toc@l
-; CHECK-P9-NEXT:    vperm v3, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs5, v4
+; CHECK-P9-NEXT:    lxv v4, 96(r4)
+; CHECK-P9-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs5, 80(r3)
-; CHECK-P9-NEXT:    xvcvuxddp vs6, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
+; CHECK-P9-NEXT:    xvcvuxddp vs6, v4
+; CHECK-P9-NEXT:    lxvx v4, 0, r4
+; CHECK-P9-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-P9-NEXT:    stxv vs6, 96(r3)
 ; CHECK-P9-NEXT:    xvcvuxddp vs7, v2
 ; CHECK-P9-NEXT:    stxv vs7, 112(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
-; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    addis r4, r2, .LC3@toc@ha
+; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    ld r4, .LC3@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v4, 112(r4)
+; CHECK-BE-NEXT:    vperm v4, v2, v3, v4
+; CHECK-BE-NEXT:    xvcvuxddp vs0, v4
+; CHECK-BE-NEXT:    lxv v4, 48(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs1, v4
+; CHECK-BE-NEXT:    lxv v4, 32(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_4@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_4@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs2, v4
+; CHECK-BE-NEXT:    lxv v4, 16(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs3, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_5@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_5@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs3, v4
+; CHECK-BE-NEXT:    lxv v4, 80(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs4, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_6@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_6@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs4, v4
+; CHECK-BE-NEXT:    lxv v4, 64(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs4, 64(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs5, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_7@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_7@toc@l
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs5, v4
+; CHECK-BE-NEXT:    lxv v4, 96(r4)
+; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs5, 80(r3)
-; CHECK-BE-NEXT:    xvcvuxddp vs6, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xvcvuxddp vs6, v4
+; CHECK-BE-NEXT:    lxvx v4, 0, r4
+; CHECK-BE-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs7, v2
 ; CHECK-BE-NEXT:    stxv vs7, 112(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = uitofp <16 x i8> %a to <16 x double>
   store <16 x double> %0, <16 x double>* %agg.result, align 128
   ret void
 }
 
 define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC4@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC5@toc@ha
 ; CHECK-P8-NEXT:    mtvsrwz v3, r3
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
+; CHECK-P8-NEXT:    ld r4, .LC4@toc@l(r4)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    ld r4, .LC5@toc@l(r5)
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v3
 ; CHECK-P8-NEXT:    vsrad v2, v2, v3
 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P9-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-P9-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    addis r3, r2, .LC4@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC4@toc@l(r3)
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test4elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI5_2@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC6@toc@ha
+; CHECK-P8-NEXT:    addis r6, r2, .LC7@toc@ha
+; CHECK-P8-NEXT:    li r7, 16
 ; CHECK-P8-NEXT:    mtvsrwz v3, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI5_1@toc@l
+; CHECK-P8-NEXT:    ld r5, .LC6@toc@l(r5)
+; CHECK-P8-NEXT:    ld r6, .LC7@toc@l(r6)
 ; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI5_2@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    lvx v4, 0, r5
+; CHECK-P8-NEXT:    lvx v4, r5, r7
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r6
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v4
 ; CHECK-P8-NEXT:    xxswapd v4, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v4
 ; CHECK-P8-NEXT:    vsld v3, v3, v4
 ; CHECK-P8-NEXT:    vsrad v2, v2, v4
 ; CHECK-P8-NEXT:    vsrad v3, v3, v4
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P8-NEXT:    xvcvsxddp vs1, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r7
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC5@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    addis r4, r2, .LC5@toc@ha
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    ld r4, .LC5@toc@l(r4)
+; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = sitofp <4 x i8> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void
 }
 
 define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
 ; CHECK-P8-LABEL: test8elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_2@toc@ha
+; CHECK-P8-NEXT:    addis r5, r2, .LC8@toc@ha
+; CHECK-P8-NEXT:    li r6, 32
+; CHECK-P8-NEXT:    addis r7, r2, .LC9@toc@ha
+; CHECK-P8-NEXT:    li r8, 48
 ; CHECK-P8-NEXT:    mtvsrd v3, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_0@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI6_2@toc@l
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_1@toc@l
-; CHECK-P8-NEXT:    lvx v2, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI6_3@toc@ha
-; CHECK-P8-NEXT:    lvx v4, 0, r6
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI6_4@toc@ha
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI6_3@toc@l
-; CHECK-P8-NEXT:    lvx v5, 0, r5
-; CHECK-P8-NEXT:    addi r5, r6, .LCPI6_4@toc@l
+; CHECK-P8-NEXT:    li r4, 16
+; CHECK-P8-NEXT:    ld r5, .LC8@toc@l(r5)
+; CHECK-P8-NEXT:    ld r7, .LC9@toc@l(r7)
+; CHECK-P8-NEXT:    lvx v2, r5, r6
+; CHECK-P8-NEXT:    lvx v4, r5, r8
+; CHECK-P8-NEXT:    lvx v5, r5, r4
 ; CHECK-P8-NEXT:    lvx v0, 0, r5
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r7
 ; CHECK-P8-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P8-NEXT:    li r5, 32
 ; CHECK-P8-NEXT:    vperm v4, v3, v3, v4
 ; CHECK-P8-NEXT:    vperm v5, v3, v3, v5
 ; CHECK-P8-NEXT:    vperm v3, v3, v3, v0
 ; CHECK-P8-NEXT:    xxswapd v0, vs0
 ; CHECK-P8-NEXT:    vsld v2, v2, v0
 ; CHECK-P8-NEXT:    vsld v4, v4, v0
 ; CHECK-P8-NEXT:    vsld v5, v5, v0
 ; CHECK-P8-NEXT:    vsld v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v2, v2, v0
-; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    vsrad v4, v4, v0
 ; CHECK-P8-NEXT:    vsrad v5, v5, v0
-; CHECK-P8-NEXT:    xvcvsxddp vs2, v3
+; CHECK-P8-NEXT:    vsrad v3, v3, v0
 ; CHECK-P8-NEXT:    xvcvsxddp vs0, v2
-; CHECK-P8-NEXT:    xvcvsxddp vs1, v5
-; CHECK-P8-NEXT:    xvcvsxddp vs3, v4
-; CHECK-P8-NEXT:    xxswapd vs2, vs2
+; CHECK-P8-NEXT:    xvcvsxddp vs1, v4
+; CHECK-P8-NEXT:    xvcvsxddp vs2, v5
+; CHECK-P8-NEXT:    xvcvsxddp vs3, v3
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    xxswapd vs1, vs1
+; CHECK-P8-NEXT:    xxswapd vs2, vs2
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r8
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs0, r3, r4
+; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test8elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrd v2, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_0@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC6@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC6@toc@l(r4)
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_1@toc@l
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI6_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC6@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC6@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_3@toc@l
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs2, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-BE-NEXT:    stxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <8 x i8>
   %1 = sitofp <8 x i8> %0 to <8 x double>
   store <8 x double> %1, <8 x double>* %agg.result, align 64
   ret void
 }
 
 define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
 ; CHECK-P8-LABEL: test16elt_signed:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_2@toc@ha
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_3@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_2@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_3@toc@l
-; CHECK-P8-NEXT:    lvx v3, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
-; CHECK-P8-NEXT:    lvx v4, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_5@toc@ha
-; CHECK-P8-NEXT:    lvx v5, 0, r6
-; CHECK-P8-NEXT:    addis r6, r2, .LCPI7_1@toc@ha
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_4@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_5@toc@l
-; CHECK-P8-NEXT:    addi r6, r6, .LCPI7_1@toc@l
-; CHECK-P8-NEXT:    lvx v0, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
-; CHECK-P8-NEXT:    lvx v1, 0, r5
-; CHECK-P8-NEXT:    addis r5, r2, .LCPI7_7@toc@ha
-; CHECK-P8-NEXT:    lxvd2x vs0, 0, r6
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_6@toc@l
-; CHECK-P8-NEXT:    addi r5, r5, .LCPI7_7@toc@l
+; CHECK-P8-NEXT:    addis r7, r2, .LC10@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LC11@toc@ha
+; CHECK-P8-NEXT:    li r5, 112
+; CHECK-P8-NEXT:    li r6, 48
+; CHECK-P8-NEXT:    li r8, 32
+; CHECK-P8-NEXT:    li r9, 16
+; CHECK-P8-NEXT:    li r10, 80
+; CHECK-P8-NEXT:    li r11, 64
+; CHECK-P8-NEXT:    ld r7, .LC10@toc@l(r7)
+; CHECK-P8-NEXT:    ld r4, .LC11@toc@l(r4)
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r7
+; CHECK-P8-NEXT:    li r7, 96
+; CHECK-P8-NEXT:    lvx v3, r4, r5
+; CHECK-P8-NEXT:    lvx v4, r4, r6
+; CHECK-P8-NEXT:    lvx v5, r4, r8
+; CHECK-P8-NEXT:    lvx v0, r4, r9
+; CHECK-P8-NEXT:    lvx v1, r4, r10
+; CHECK-P8-NEXT:    lvx v6, r4, r11
+; CHECK-P8-NEXT:    lvx v7, r4, r7
+; CHECK-P8-NEXT:    lvx v8, 0, r4
 ; CHECK-P8-NEXT:    vperm v3, v2, v2, v3
-; CHECK-P8-NEXT:    lvx v6, 0, r4
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI7_8@toc@ha
-; CHECK-P8-NEXT:    lvx v7, 0, r5
+; CHECK-P8-NEXT:    xxswapd v9, vs0
 ; CHECK-P8-NEXT:    vperm v4, v2, v2, v4
-; CHECK-P8-NEXT:    li r5, 96
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI7_8@toc@l
 ; CHECK-P8-NEXT:    vperm v5, v2, v2, v5
-; CHECK-P8-NEXT:    xxswapd v9, vs0
-; CHECK-P8-NEXT:    lvx v8, 0, r4
 ; CHECK-P8-NEXT:    vperm v0, v2, v2, v0
-; CHECK-P8-NEXT:    li r4, 112
 ; CHECK-P8-NEXT:    vperm v1, v2, v2, v1
 ; CHECK-P8-NEXT:    vperm v6, v2, v2, v6
 ; CHECK-P8-NEXT:    vperm v7, v2, v2, v7
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v8
 ; CHECK-P8-NEXT:    vsld v3, v3, v9
+; CHECK-P8-NEXT:    vsld v4, v4, v9
+; CHECK-P8-NEXT:    vsld v5, v5, v9
 ; CHECK-P8-NEXT:    vsld v0, v0, v9
 ; CHECK-P8-NEXT:    vsld v1, v1, v9
 ; CHECK-P8-NEXT:    vsld v6, v6, v9
 ; CHECK-P8-NEXT:    vsld v7, v7, v9
 ; CHECK-P8-NEXT:    vsld v2, v2, v9
-; CHECK-P8-NEXT:    vsrad v7, v7, v9
-; CHECK-P8-NEXT:    vsrad v2, v2, v9
-; CHECK-P8-NEXT:    vsld v4, v4, v9
-; CHECK-P8-NEXT:    vsld v5, v5, v9
-; CHECK-P8-NEXT:    vsrad v6, v6, v9
-; CHECK-P8-NEXT:    vsrad v0, v0, v9
-; CHECK-P8-NEXT:    vsrad v1, v1, v9
-; CHECK-P8-NEXT:    xvcvsxddp vs2, v7
-; CHECK-P8-NEXT:    xvcvsxddp vs3, v2
 ; CHECK-P8-NEXT:    vsrad v3, v3, v9
 ; CHECK-P8-NEXT:    vsrad v4, v4, v9
 ; CHECK-P8-NEXT:    vsrad v5, v5, v9
-; CHECK-P8-NEXT:    xvcvsxddp vs4, v6
-; CHECK-P8-NEXT:    xvcvsxddp vs1, v1
+; CHECK-P8-NEXT:    vsrad v0, v0, v9
+; CHECK-P8-NEXT:    vsrad v1, v1, v9
+; CHECK-P8-NEXT:    vsrad v6, v6, v9
+; CHECK-P8-NEXT:    vsrad v7, v7, v9
+; CHECK-P8-NEXT:    vsrad v2, v2, v9
+; CHECK-P8-NEXT:    xvcvsxddp vs0, v3
+; CHECK-P8-NEXT:    xvcvsxddp vs1, v5
+; CHECK-P8-NEXT:    xvcvsxddp vs2, v1
+; CHECK-P8-NEXT:    xvcvsxddp vs3, v7
+; CHECK-P8-NEXT:    xvcvsxddp vs4, v2
+; CHECK-P8-NEXT:    xvcvsxddp vs5, v6
+; CHECK-P8-NEXT:    xvcvsxddp vs6, v0
+; CHECK-P8-NEXT:    xxswapd vs0, vs0
+; CHECK-P8-NEXT:    xvcvsxddp vs7, v4
+; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xxswapd vs2, vs2
-; CHECK-P8-NEXT:    xvcvsxddp vs5, v0
 ; CHECK-P8-NEXT:    xxswapd vs3, vs3
-; CHECK-P8-NEXT:    xvcvsxddp vs0, v5
-; CHECK-P8-NEXT:    xvcvsxddp vs6, v3
-; CHECK-P8-NEXT:    xvcvsxddp vs7, v4
-; CHECK-P8-NEXT:    stxvd2x vs3, r3, r4
-; CHECK-P8-NEXT:    li r4, 80
 ; CHECK-P8-NEXT:    xxswapd vs4, vs4
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r5
-; CHECK-P8-NEXT:    li r5, 64
-; CHECK-P8-NEXT:    xxswapd vs1, vs1
 ; CHECK-P8-NEXT:    xxswapd vs5, vs5
-; CHECK-P8-NEXT:    xxswapd vs0, vs0
-; CHECK-P8-NEXT:    stxvd2x vs4, r3, r4
-; CHECK-P8-NEXT:    li r4, 48
-; CHECK-P8-NEXT:    xxswapd vs3, vs6
-; CHECK-P8-NEXT:    stxvd2x vs1, r3, r5
-; CHECK-P8-NEXT:    li r5, 32
-; CHECK-P8-NEXT:    xxswapd vs2, vs7
-; CHECK-P8-NEXT:    stxvd2x vs5, r3, r4
-; CHECK-P8-NEXT:    li r4, 16
-; CHECK-P8-NEXT:    stxvd2x vs0, r3, r5
-; CHECK-P8-NEXT:    stxvd2x vs2, r3, r4
-; CHECK-P8-NEXT:    stxvd2x vs3, 0, r3
+; CHECK-P8-NEXT:    xxswapd vs6, vs6
+; CHECK-P8-NEXT:    xxswapd vs7, vs7
+; CHECK-P8-NEXT:    stxvd2x vs4, r3, r5
+; CHECK-P8-NEXT:    stxvd2x vs3, r3, r7
+; CHECK-P8-NEXT:    stxvd2x vs5, r3, r10
+; CHECK-P8-NEXT:    stxvd2x vs2, r3, r11
+; CHECK-P8-NEXT:    stxvd2x vs6, r3, r6
+; CHECK-P8-NEXT:    stxvd2x vs1, r3, r8
+; CHECK-P8-NEXT:    stxvd2x vs7, r3, r9
+; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test16elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_1@toc@l
+; CHECK-P9-NEXT:    addis r4, r2, .LC7@toc@ha
+; CHECK-P9-NEXT:    ld r4, .LC7@toc@l(r4)
+; CHECK-P9-NEXT:    lxv v3, 112(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_2@toc@l
+; CHECK-P9-NEXT:    lxv v3, 48(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_3@toc@l
+; CHECK-P9-NEXT:    lxv v3, 32(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs2, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_4@toc@l
+; CHECK-P9-NEXT:    lxv v3, 16(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs3, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_5@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_5@toc@l
+; CHECK-P9-NEXT:    lxv v3, 80(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs4, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_6@toc@l
+; CHECK-P9-NEXT:    lxv v3, 64(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs4, 64(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs5, v3
-; CHECK-P9-NEXT:    lxvx v3, 0, r4
-; CHECK-P9-NEXT:    addis r4, r2, .LCPI7_7@toc@ha
-; CHECK-P9-NEXT:    addi r4, r4, .LCPI7_7@toc@l
+; CHECK-P9-NEXT:    lxv v3, 96(r4)
 ; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs5, 80(r3)
 ; CHECK-P9-NEXT:    vextsb2d v3, v3
 ; CHECK-P9-NEXT:    xvcvsxddp vs6, v3
 ; CHECK-P9-NEXT:    lxvx v3, 0, r4
 ; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P9-NEXT:    stxv vs6, 96(r3)
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs7, v2
 ; CHECK-P9-NEXT:    stxv vs7, 112(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addis r4, r2, .LC7@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v3, v3, v3
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_1@toc@l
+; CHECK-BE-NEXT:    ld r4, .LC7@toc@l(r4)
+; CHECK-BE-NEXT:    lxv v4, 96(r4)
 ; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    vextsb2d v4, v4
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v4
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_2@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_2@toc@l
+; CHECK-BE-NEXT:    lxv v4, 80(r4)
 ; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsb2d v4, v4
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v4
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_3@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_3@toc@l
+; CHECK-BE-NEXT:    lxv v4, 112(r4)
 ; CHECK-BE-NEXT:    vperm v4, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
 ; CHECK-BE-NEXT:    vextsb2d v4, v4
 ; CHECK-BE-NEXT:    xvcvsxddp vs2, v4
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_4@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_4@toc@l
+; CHECK-BE-NEXT:    lxv v4, 64(r4)
 ; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
 ; CHECK-BE-NEXT:    stxv vs2, 80(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs3, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_5@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_5@toc@l
+; CHECK-BE-NEXT:    lxv v3, 48(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs3, 112(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs4, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_6@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_6@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs4, 0(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs5, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_7@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_7@toc@l
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs5, 32(r3)
 ; CHECK-BE-NEXT:    vextsb2d v3, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs6, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
+; CHECK-BE-NEXT:    lxv v3, 32(r4)
 ; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-BE-NEXT:    stxv vs6, 64(r3)
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs7, v2
 ; CHECK-BE-NEXT:    stxv vs7, 96(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = sitofp <16 x i8> %a to <16 x double>
   store <16 x double> %0, <16 x double>* %agg.result, align 128
   ret void
 }

llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2d:
 ; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
 ; CHECK-P9-NOALTIVEC-NEXT:    extsb 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsb 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsb2d:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-P8-NEXT:    xxswapd 35, 0
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 56, i64 56>
   %shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>

 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2d:
 ; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
 ; CHECK-P9-NOALTIVEC-NEXT:    extsh 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsh 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsh2d:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC1@toc@l(3)
 ; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-P8-NEXT:    xxswapd 35, 0
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 48, i64 48>
   %shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>

 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsw2d:
 ; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
 ; CHECK-P9-NOALTIVEC-NEXT:    extsw 3, 3
 ; CHECK-P9-NOALTIVEC-NEXT:    extsw 4, 4
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_vextsw2d:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-P8-NEXT:    xxswapd 35, 0
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 32, i64 32>
   %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
   ret <2 x i64> %shr
 }
 
 define <2 x i64> @test_none(<2 x i64> %m) {
 ; CHECK-P9-LABEL: test_none:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; CHECK-P9-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-P9-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-P9-NEXT:    lxvx 35, 0, 3
 ; CHECK-P9-NEXT:    vsld 2, 2, 3
 ; CHECK-P9-NEXT:    vsrad 2, 2, 3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-NOALTIVEC-LABEL: test_none:
 ; CHECK-P9-NOALTIVEC:       # %bb.0: # %entry
 ; CHECK-P9-NOALTIVEC-NEXT:    sldi 3, 3, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    sldi 4, 4, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    sradi 3, 3, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    sradi 4, 4, 16
 ; CHECK-P9-NOALTIVEC-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_none:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; CHECK-P8-NEXT:    addis 3, 2, .LC3@toc@ha
+; CHECK-P8-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-P8-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-P8-NEXT:    xxswapd 35, 0
 ; CHECK-P8-NEXT:    vsld 2, 2, 3
 ; CHECK-P8-NEXT:    vsrad 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %shl = shl <2 x i64> %m, <i64 16, i64 16>
   %shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>
   ret <2 x i64> %shr
 }

llvm/test/CodeGen/PowerPC/vector-rotates.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
 ; RUN:   -verify-machineinstrs -mcpu=pwr8 < %s | \
 ; RUN:   FileCheck --check-prefix=CHECK-P8 %s
 ; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
 ; RUN:   -verify-machineinstrs -mcpu=pwr7 < %s | \
 ; RUN:   FileCheck --check-prefix=CHECK-P7 %s
 
 define <16 x i8> @rotl_v16i8(<16 x i8> %a) {
 ; CHECK-P8-LABEL: rotl_v16i8:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vrlb v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: rotl_v16i8:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P7-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P7-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-P7-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-P7-NEXT:    lxvw4x vs35, 0, r3
 ; CHECK-P7-NEXT:    vrlb v2, v2, v3
 ; CHECK-P7-NEXT:    blr
 entry:
   %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8>
   %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0>
   %d = or <16 x i8> %b, %c
   ret <16 x i8> %d
 }
 
 define <8 x i16> @rotl_v8i16(<8 x i16> %a) {
 ; CHECK-P8-LABEL: rotl_v8i16:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vrlh v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: rotl_v8i16:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P7-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P7-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-P7-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P7-NEXT:    lxvw4x vs35, 0, r3
 ; CHECK-P7-NEXT:    vrlh v2, v2, v3
 ; CHECK-P7-NEXT:    blr
 entry:
   %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16>
   %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0>
   %d = or <8 x i16> %b, %c
   ret <8 x i16> %d
 }
 
 define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) {
 ; CHECK-P8-LABEL: rotl_v4i32_0:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-P8-NEXT:    lvx v3, 0, r3
 ; CHECK-P8-NEXT:    vrlw v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: rotl_v4i32_0:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-P7-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-P7-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-P7-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-P7-NEXT:    lxvw4x vs35, 0, r3
 ; CHECK-P7-NEXT:    vrlw v2, v2, v3
 ; CHECK-P7-NEXT:    blr
 entry:
   %b = shl <4 x i32> %a, <i32 29, i32 19, i32 17, i32 11>
   %c = lshr <4 x i32> %a, <i32 3, i32 13, i32 15, i32 21>
   %d = or <4 x i32> %b, %c
   ret <4 x i32> %d
entry:
   %c = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9>
   %d = or <4 x i32> %b, %c
   ret <4 x i32> %d
 }
 
 define <2 x i64> @rotl_v2i64(<2 x i64> %a) {
 ; CHECK-P8-LABEL: rotl_v2i64:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P8-NEXT:    addis r3, r2, .LC3@toc@ha
+; CHECK-P8-NEXT:    ld r3, .LC3@toc@l(r3)
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    xxswapd vs35, vs0
 ; CHECK-P8-NEXT:    vrld v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: rotl_v2i64:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    addi r3, r1, -48

llvm/test/CodeGen/PowerPC/vperm-lowering.ll

 ; CHECK: .byte 13
 ; CHECK: .byte 18
 ; CHECK: .byte 23
 ; CHECK: .byte 28
 ; CHECK: .byte 1
 ; CHECK: .byte 6
 ; CHECK: .byte 11
 ; CHECK: foo:
-; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_0@toc@ha
-; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_0@toc@l
+; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
+; CHECK: ld [[REG2:[0-9]+]], .LC0@toc@l([[REG1]])
 ; CHECK: lvx [[REG3:[0-9]+]], 0, [[REG2]]
+; CHECK: .LC0:
+; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/vselect-constants.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 ; First, check the generic pattern for any 2 vector constants. Then, check special cases where
 ; the constants are all off-by-one. Finally, check the extra special cases where the constants
 ; include 0 or -1.
 ; Each minimal select test is repeated with a more typical pattern that includes a compare to
 ; generate the condition value.
 
 define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_C1_or_C2_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
-; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-NEXT:    addi 4, 4, .LCPI0_1@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
-; CHECK-NEXT:    lvx 4, 0, 4
+; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    vslw 2, 2, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
-; CHECK-NEXT:    lvx 3, 0, 3
+; CHECK-NEXT:    lvx 3, 3, 4
 ; CHECK-NEXT:    xxsel 34, 36, 35, 34
 ; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; CHECK-NEXT:    addi 4, 4, .LCPI1_1@toc@l
-; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    lvx 4, 0, 4
+; CHECK-NEXT:    li 4, 16
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    lvx 3, 3, 4
+; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    xxsel 34, 36, 35, 34
 ; CHECK-NEXT:    blr
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cplus1_or_C_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
 ; CHECK-NEXT:    vspltisw 3, 1
-; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis 3, 2, .LC3@toc@ha
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI3_0@toc@l
+; CHECK-NEXT:    ld 3, .LC3@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vsubuwm 2, 3, 2
 ; CHECK-NEXT:    blr
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cminus1_or_C_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
-; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI4_0@toc@l
+; CHECK-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-NEXT:    ld 3, .LC4@toc@l(3)
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
 ; CHECK-NEXT:    vslw 2, 2, 3
 ; CHECK-NEXT:    vsraw 2, 2, 3
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    addis 3, 2, .LC5@toc@ha
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI5_0@toc@l
+; CHECK-NEXT:    ld 3, .LC5@toc@l(3)
 ; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    vadduwm 2, 2, 3
 ; CHECK-NEXT:    blr
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
   ret <4 x i32> %add
 }
 

llvm/test/CodeGen/PowerPC/vsx.ll

 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test69(<2 x i16> %a) {
 ; CHECK-LABEL: test69:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI63_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    lha r3, -18(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lha r3, -26(r1)
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    xvcvsxddp v2, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test69:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
-; CHECK-REG-NEXT:    addi r3, r3, .LCPI63_0@toc@l
+; CHECK-REG-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-REG-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    lha r3, -18(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lha r3, -26(r1)
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    xvcvsxddp v2, v2
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test69:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
-; CHECK-FISL-NEXT:    addi r3, r3, .LCPI63_0@toc@l
+; CHECK-FISL-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-FISL-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
 ; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-FISL-NEXT:    lha r3, -18(r1)
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    lha r3, -26(r1)
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test69:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
-; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_0@toc@l
+; CHECK-LE-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-LE-NEXT:    addis r4, r2, .LC1@toc@ha
+; CHECK-LE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-LE-NEXT:    lvx v3, 0, r3
-; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_1@toc@ha
-; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_1@toc@l
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    ld r3, .LC1@toc@l(r4)
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-NEXT:    vsld v2, v2, v3
 ; CHECK-LE-NEXT:    vsrad v2, v2, v3
 ; CHECK-LE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i16> %a to <2 x double>
   ret <2 x double> %w
 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x double> @test70(<2 x i8> %a) {
 ; CHECK-LABEL: test70:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
-; CHECK-NEXT:    addi r3, r3, .LCPI64_0@toc@l
+; CHECK-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    extsb r3, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    ld r3, -32(r1)
 ; CHECK-NEXT:    extsb r3, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    xvcvsxddp v2, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test70:
 ; CHECK-REG:       # %bb.0:
-; CHECK-REG-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
-; CHECK-REG-NEXT:    addi r3, r3, .LCPI64_0@toc@l
+; CHECK-REG-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-REG-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    extsb r3, r3
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
 ; CHECK-REG-NEXT:    extsb r3, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    xvcvsxddp v2, v2
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test70:
 ; CHECK-FISL:       # %bb.0:
-; CHECK-FISL-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
-; CHECK-FISL-NEXT:    addi r3, r3, .LCPI64_0@toc@l
+; CHECK-FISL-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-FISL-NEXT:    ld r3, .LC1@toc@l(r3)
 ; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-FISL-NEXT:    xxlor vs0, v2, v2
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
 ; CHECK-FISL-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-FISL-NEXT:    ld r3, -24(r1)
 ; CHECK-FISL-NEXT:    extsb r3, r3
 ; CHECK-FISL-NEXT:    std r3, -8(r1)
 ; CHECK-FISL-NEXT:    ld r3, -32(r1)
 ; CHECK-FISL-NEXT:    extsb r3, r3
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test70:
 ; CHECK-LE:       # %bb.0:
-; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
-; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_0@toc@l
+; CHECK-LE-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-LE-NEXT:    addis r4, r2, .LC3@toc@ha
+; CHECK-LE-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-LE-NEXT:    lvx v3, 0, r3
-; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_1@toc@ha
-; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_1@toc@l
-; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-NEXT:    ld r3, .LC3@toc@l(r4)
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-LE-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-NEXT:    vsld v2, v2, v3
 ; CHECK-LE-NEXT:    vsrad v2, v2, v3
 ; CHECK-LE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-LE-NEXT:    blr
   %w = sitofp <2 x i8> %a to <2 x double>
   ret <2 x double> %w
 
 
 }
 
 ; This gets scalarized so the code isn't great
 define <2 x i32> @test80(i32 %v) {
 ; CHECK-LABEL: test80:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r4, r1, -16
 ; CHECK-NEXT:    stw r3, -16(r1)
-; CHECK-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
+; CHECK-NEXT:    addis r3, r2, .LC2@toc@ha
 ; CHECK-NEXT:    lxvw4x vs0, 0, r4
-; CHECK-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxvw4x v3, 0, r3
+; CHECK-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-NEXT:    xxspltw v2, vs0, 0
+; CHECK-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-NEXT:    vadduwm v2, v2, v3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test80:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r4, r1, -16
 ; CHECK-REG-NEXT:    stw r3, -16(r1)
-; CHECK-REG-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
+; CHECK-REG-NEXT:    addis r3, r2, .LC2@toc@ha
 ; CHECK-REG-NEXT:    lxvw4x vs0, 0, r4
-; CHECK-REG-NEXT:    addi r3, r3, .LCPI65_0@toc@l
-; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
+; CHECK-REG-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-REG-NEXT:    xxspltw v2, vs0, 0
+; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-REG-NEXT:    vadduwm v2, v2, v3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test80:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-FISL-NEXT:    stw r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
 ; CHECK-FISL-NEXT:    xxspltw v2, vs0, 0
-; CHECK-FISL-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
-; CHECK-FISL-NEXT:    addi r3, r3, .LCPI65_0@toc@l
+; CHECK-FISL-NEXT:    addis r3, r2, .LC2@toc@ha
+; CHECK-FISL-NEXT:    ld r3, .LC2@toc@l(r3)
 ; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-FISL-NEXT:    vadduwm v2, v2, v3
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test80:
 ; CHECK-LE:       # %bb.0:
+; CHECK-LE-NEXT:    addis r4, r2, .LC4@toc@ha
 ; CHECK-LE-NEXT:    mtfprwz f0, r3
-; CHECK-LE-NEXT:    addis r4, r2, .LCPI65_0@toc@ha
-; CHECK-LE-NEXT:    addi r3, r4, .LCPI65_0@toc@l
+; CHECK-LE-NEXT:    ld r3, .LC4@toc@l(r4)
 ; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-LE-NEXT:    lvx v3, 0, r3
 ; CHECK-LE-NEXT:    vadduwm v2, v2, v3
 ; CHECK-LE-NEXT:    blr
   %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
   %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
   %i = add <2 x i32> %b2, <i32 2, i32 3>
   ret <2 x i32> %i