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[llvm][AArch64] Simplify (and (sign_extend..) #bitmask).
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Authored by fpetrogalli on Nov 2 2020, 6:01 AM.

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VT = (and (sign_extend NarrowVT to VT) #bitmask)

into

VT = (zero_extend NarrowVT)

With this combine, the test replaces a sign extended load + an
unsigned extention with a zero extended load to render one of the
operands of the last multiplication.

BEFORE                       |  AFTER
  f_i16_i32:                 |    f_i16_i32:
       .fnstart              |           .fnstart
       ldrsh   r0, [r0]      |           ldrh    r1, [r1]
       ldrsh   r1, [r1]      |           ldrsh   r0, [r0]
       smulbb  r0, r1, r0    |           smulbb  r0, r0, r1
       uxth    r1, r1        |           mul     r0, r0, r1
       mul     r0, r0, r1    |           bx      lr
       bx      lr            |

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Event Timeline

fpetrogalli created this revision.Nov 2 2020, 6:01 AM
fpetrogalli requested review of this revision.Nov 2 2020, 6:01 AM
resistor added inline comments.
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
5742

I think it would be simpler to fetch LHS.getOperand(0).getValueType().getSizeInBits() and just do C->getAPIntValue().isMask(SizeInBits)

I believe that would obviate the need for most of the rest of the logic in here.

Thank you for your review @resistor. I simplified the logic in the
lambda function as suggested in your comment.

fpetrogalli marked an inline comment as done.Nov 3 2020, 4:58 AM
resistor accepted this revision.Nov 3 2020, 10:22 AM
This revision is now accepted and ready to land.Nov 3 2020, 10:22 AM

NFC: rebase on top of master.

This revision was landed with ongoing or failed builds.Nov 9 2020, 4:53 AM
This revision was automatically updated to reflect the committed changes.