[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic

[stefanp]

Summary

Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.

The compiler will produce code that looks like:

pla r3, x@got@tlsgd@pcrel            R_PPC64_GOT_TLSGD_PCREL34
bl __tls_get_addr@notoc(x@tlsgd)     R_PPC64_TLSGD
                                     R_PPC64_REL24_NOTOC

LLD should be able to correctly compute the relocation for R_PPC64_GOT_TLSGD_PCREL34 as well as do the following two relaxations where possible:
General Dynamic to Local Exec:

paddi r3, r13, x@tprel
nop

and General Dynamic to Initial Exec:

pld r3, x@got@tprel@pcrel
add r3, r3, r13

Note:
This patch adds support for the PC Relative (no TOC) version of General Dynamic on top of the existing support for the TOC version of General Dynamic.
The ABI does not provide any way to tell by looking only at the relocation R_PPC64_TLSGD when it is being used in a TOC instruction sequence or and when it is being used in a no TOC sequence. The TOC sequence should always be 4 byte aligned. This patch adds one to the offset of the relocation when it is being used in a no TOC sequence. In this way LLD can tell by looking at the alignment of the offset of R_PPC64_TLSGD whether or not it is being used as part of a TOC or no TOC sequence.

[nemanjai]

Are the mentions of R_PPC64_GOT_TLSGD34 in the description typos of some sort? In the code, there are only mentions of R_PPC64_GOT_TLSGD_PCREL34.

[nemanjai]

If I'm not mistaken, this patch is dependent on another one. If so, please add the dependency in the review.

lld/ELF/Arch/PPC64.cpp

1369

Maybe just return expr? Or we can simply omit this and change the below condition to
if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE)

lld/ELF/Relocations.cpp

1374

I think you should mention here that we look at the next relocation to see if it is a NOTOC relocation.

[MaskRay]

Does this depend on D83404 or D86608?

[stefanp]

I've updated the description to only use the correct version of the relocation: R_PPC64_GOT_TLSGD_PCREL34.

I'm sorry that I didn't add the patches that this depends on. I've added all three patches now as parents to this patch.

I updated a comment and simplified one of the if conditions.

[MaskRay]

lld/ELF/Relocations.cpp

1361

I am not sure we want to add error checking for every relocation usage. We should add them considering the possibility of such errors (can a compiler/tool/assembly generate such erroneous relocation usage?)

[stefanp]

lld/ELF/Relocations.cpp

1361

I do not believe that the compiler can generate either of these situations from C source code.

I can generate the bad alignment in assembly (by adding .space 1 for example) but it is not likely that someone will do that.

In general there are a couple of reasons why I add code like this.
First, it is to prevent future development work from creating hidden bugs. Maybe a little like
https://llvm.org/docs/CodingStandards.html#assert-liberally
from a philosophical perspective. I know that these are not asserts but I think the argument remains valid...
Second, it is my way of documenting assumptions in the code.

I understand your point of view. You don't want want half the code to be error checking so if you really want me to remove these two errors I can. I just wanted to give you my perspective on this. Let me know what you think!

[stefanp]

Rebased this patch to Top of Trunk.
Fixed all of the error to errorOrWarn.
Made use of NOP.

This patch should now no longer have any dependencies.

[stefanp]

Fixed spacing that I missed.

[NeHuang]

lld/ELF/Arch/PPC64.cpp

731

nit: can we add the comment to elaborate Relax from ... to ... ?

735

ditto

745

nit: clang-format needed.

1411

nit: can we add more comments as existing cases like // Relax from ...... to .....?

1414

return?

1416

ditto, add the comment Relax from ... to ...

lld/ELF/Relocations.cpp

1365

Will the return be executed after the errorOrWarn?

1371

ditto

lld/test/ELF/ppc64-tls-pcrel-gd.s

68

Are we missing the relocation R_PPC64_TPREL34 here for GDTOLE?

144

alignment issue or phabricator display issue?

182

ditto

[sfertile]

lld/ELF/Arch/PPC64.cpp

1277

It looks like these 2 cases and R_PPC64_GOT_PCREL34 et al share the same implementation, we should combine them.

lld/ELF/Relocations.cpp

1361

We dereference 'i' so we need the check that i is still valid. The validation of the offset is less critical and could be omitted or converted to an assert.

[stefanp]

Addressed a number of nits.
Added an NFC change before this patch and rebased this patch.

lld/ELF/Arch/PPC64.cpp

1277

Initially I wanted to do this after all of the LLD patches were in. However, you are now the second person to ask for this so I'm going do it now.
I'm going to do this in an NFC patch and then rebase this patch on top.

lld/ELF/Relocations.cpp

1361

In that case I'll keep the check on i but I'll remove the offset check.

1365

Yes it could be executed. The function errorOrWarn will sometimes exit and it will sometimes return back here.

1371

Same as above. We may execute the return.

lld/test/ELF/ppc64-tls-pcrel-gd.s

68

That relocation should not be in the final linked object file. The linker can compute the value of it and just modify the immediate in the instruction.

[NeHuang]

LGTM but of course, please wait to hear from @sfertile/@MaskRay before committing.

[MaskRay]

lld/ELF/Arch/PPC64.cpp

733

The comment on this line is redundant.

747

Delete parens around %. ditto below

756

The comment is redundant

1428

Delete parens.

1433

User lower-case hexidecimal literals.

lld/ELF/Relocations.cpp

1375

config->isMips64EL -> /*isMips64EL=*/false

1376

The coding standard prefers ++offset

lld/test/ELF/ppc64-tls-pcrel-gd.s

185

Delete the trailing unrelated instructions

[stefanp]

Updated a number of formatting issues.
Updated the test case to remove instructions that are not needed.

[MaskRay]

lld/test/ELF/ppc64-tls-pcrel-gd.s

169

This function does not add coverage. Consider deleting it

[stefanp]

Removed the last function from the test assembly file.

[MaskRay]

lld/test/ELF/ppc64-tls-pcrel-gd.s

109

It seems that GDAddr vs GDVal does not add test coverage as well.

I think the test can be simply:

paddi 3, 0, x@got@tlsgd@pcrel, 1
bl __tls_get_addr@notoc(x@tlsgd)
paddi 4, 0, y@got@tlsgd@pcrel, 1
bl __tls_get_addr@notoc(y@tlsgd)
blr

[stefanp]

Further reduced the test case.

[sfertile]

lld/ELF/Arch/PPC64.cpp

1277

Thanks.

lld/ELF/Relocations.cpp

1369

The first line does a good job explaining what we are doing, the following then somewhat repeats it. I think we can pare this comment down without losing much:

// Offset the 4-byte aligned R_PPC64_TLSGD by one byte in the NOTOC case, so we can discern it later from the toc-case.

[MaskRay]

LGTM. Worth checking with @sfertile in case he has more comments

[stefanp]

Updated the comment.

[sfertile]

LGTM also.

[stefanp]

Reopening this to see why the test failed.

[stefanp]

Looks like .rela.dyn is located in different places depending on the machine.
From two different bots:

# GDTOIE-RELOC: Relocation section '.rela.dyn' at offset 0x10118 contains 2 entries:
                ^
<stdin>:2:1: note: scanning from here
Relocation section '.rela.dyn' at offset 0x10128 contains 2 entries:

or

# GDTOIE-RELOC: Relocation section '.rela.dyn' at offset 0x10118 contains 2 entries:
                ^
<stdin>:2:1: note: scanning from here
Relocation section '.rela.dyn' at offset 0x10148 contains 2 entries:

[MaskRay]

In D87318#2306973, @stefanp wrote:

Looks like .rela.dyn is located in different places depending on the machine.
From two different bots:

# GDTOIE-RELOC: Relocation section '.rela.dyn' at offset 0x10118 contains 2 entries:
                ^
<stdin>:2:1: note: scanning from here
Relocation section '.rela.dyn' at offset 0x10128 contains 2 entries:

or

# GDTOIE-RELOC: Relocation section '.rela.dyn' at offset 0x10118 contains 2 entries:
                ^
<stdin>:2:1: note: scanning from here
Relocation section '.rela.dyn' at offset 0x10148 contains 2 entries:

I mentioned this several times previously. If you use a shared object for another link, please set -soname=t or another fixed string.

[stefanp]

Ok, thank you MaskRay.
Sorry, in my head I didn't put the error together with what you had said previously.

lld/ELF/Arch/PPC64.cpp

 //===- PPC64.cpp ----------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "SymbolTable.h"
void PPC64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
   case R_PPC64_GOT_TLSGD16_HA:
     writeFromHalf16(loc, NOP);
     break;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13
     relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
     break;
-  case R_PPC64_TLSGD:
-    write32(loc, NOP);
+  case R_PPC64_GOT_TLSGD_PCREL34:
+    writePrefixedInstruction(loc, 0x06000000386d0000); // paddi r3, r13
+    relocateNoSym(loc, R_PPC64_TPREL34, val);
+    break;
+  case R_PPC64_TLSGD: {
+    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
+    if ((locAsInt % 4) == 0) {
+      write32(loc, NOP);            // nop
       write32(loc + 4, 0x38630000); // addi r3, r3
       // Since we are relocating a half16 type relocation and Loc + 4 points to
       // the start of an instruction we need to advance the buffer by an extra
       // 2 bytes on BE.
       relocateNoSym(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0),
                     R_PPC64_TPREL16_LO, val);
+    } else if ((locAsInt % 4) == 1) {
+      write32(loc - 1, NOP);     // nop
+    } else {
+      errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment");
+    }
     break;
+  }
   default:
     llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
   }
 }
 
 void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
                            uint64_t val) const {
   // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
   // The local dynamic code sequence for a global `x` will look like:
   // Instruction                    Relocation                Symbol
   // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
   // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
   // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
   //                                R_PPC64_REL24               __tls_get_addr
RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_REL64:
   case R_PPC64_PCREL34:
     return R_PC;
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_HA:
   case R_PPC64_GOT_TLSGD16_HI:
   case R_PPC64_GOT_TLSGD16_LO:
     return R_TLSGD_GOT;
+  case R_PPC64_GOT_TLSGD_PCREL34:
+    return R_TLSGD_PC;
   case R_PPC64_GOT_TLSLD16:
   case R_PPC64_GOT_TLSLD16_HA:
   case R_PPC64_GOT_TLSLD16_HI:
   case R_PPC64_GOT_TLSLD16_LO:
     return R_TLSLD_GOT;
   case R_PPC64_GOT_TPREL16_HA:
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS:
case R_PPC64_REL24_NOTOC: {
     checkInt(loc, val, 26, rel);
     checkAlignment(loc, val, 4, rel);
     write32(loc, (read32(loc) & ~mask) | (val & mask));
     break;
   }
   case R_PPC64_DTPREL64:
     write64(loc, val - dynamicThreadPointerOffset);
     break;
-  case R_PPC64_PCREL34: {
+  case R_PPC64_PCREL34:
+  case R_PPC64_GOT_TLSGD_PCREL34: {
     const uint64_t si0Mask = 0x00000003ffff0000;
     const uint64_t si1Mask = 0x000000000000ffff;
     const uint64_t fullMask = 0x0003ffff0000ffff;
     checkInt(loc, val, 34, rel);
 
     uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
     writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |
                              (val & si1Mask));
RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data,
   if ((type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT) &&
       config->pcRelOptimize) {
     // It only makes sense to optimize pld since paddi means that the address
     // of the object in the GOT is required rather than the object itself.
     assert(data && "Expecting an instruction encoding here");
     if ((readPrefixedInstruction(data) & 0xfc000000) == 0xe4000000)
       return R_PPC64_RELAX_GOT_PC;
   }
-  if (expr == R_RELAX_TLS_GD_TO_IE)
+
+  if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE)
     return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
   if (expr == R_RELAX_TLS_LD_TO_LE)
     return R_RELAX_TLS_LD_TO_LE_ABS;
   return expr;
 }
 
 // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
 // The general dynamic code sequence for a global `x` uses 4 instructions.
void PPC64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
   case R_PPC64_GOT_TLSGD16_LO: {
     // Relax from addi  r3, rA, sym@got@tlsgd@l to
     //            ld r3, sym@got@tprel@l(rA)
     uint32_t ra = (readFromHalf16(loc) & (0x1f << 16));
     writeFromHalf16(loc, 0xe8600000 | ra);
     relocateNoSym(loc, R_PPC64_GOT_TPREL16_LO_DS, val);
     return;
   }
-  case R_PPC64_TLSGD:
+  case R_PPC64_GOT_TLSGD_PCREL34: {
+    // pld r3, sym@got@tprel@pcrel
+    writePrefixedInstruction(loc, 0x04100000e4600000);
+    relocateNoSym(loc, R_PPC64_GOT_TPREL_PCREL34, val);
+    break;
+  }
+  case R_PPC64_TLSGD: {
+    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
+    if ((locAsInt % 4) == 0) {
       write32(loc, NOP);            // bl __tls_get_addr(sym@tlsgd) --> nop
       write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
+    } else if ((locAsInt % 4) == 1) {
+      // bl __tls_get_addr(sym@tlsgd) --> add r3, r3, r13
+      write32(loc - 1, 0x7c636A14);
+    } else {
+      errorOrWarn("R_PPC64_TLSGD has unexpected byte alignment");
+    }
     return;
+  }
   default:
     llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
   }
 }
 
 // The prologue for a split-stack function is expected to look roughly
 // like this:
 //    .Lglobal_entry_point:
 //      # TOC pointer initialization.
 //      ...
 //    .Llocal_entry_point:
 //      # load the __private_ss member of the threads tcbhead.
 //      ld r0,-0x7000-64(r13)

lld/ELF/Relocations.cpp

 //===- Relocations.cpp ----------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains platform-independent functions to process relocations.
if (config->emachine == EM_PPC64) {
     if (isPPC64SmallCodeModelTocReloc(type))
       sec.file->ppc64SmallCodeModelTocRelocs = true;
 
     // Record the TOC entry (.toc + addend) as not relaxable. See the comment in
     // InputSectionBase::relocateAlloc().
     if (type == R_PPC64_TOC16_LO && sym.isSection() && isa<Defined>(sym) &&
         cast<Defined>(sym).section->name == ".toc")
       ppc64noTocRelax.insert({&sym, addend});
+
+    if (type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) {
+      if (i == end) {
+        errorOrWarn("R_PPC64_TLSGD may not be the last relocation" +
+                    getLocation(sec, sym, offset));
+        return;
+      }
+
+      if ((offset%4) != 0) {
+        errorOrWarn("R_PPC64_TLSGD must be 4 byte aligned" +
+                    getLocation(sec, sym, offset));
+        return;
+      }
+
+      // Offset R_PPC64_TLSGD by one byte in the NOTOC case.
+      // Here we check the next relocation to see if it is R_PPC64_REL24_NOTOC.
+      // If the next relocation is a NOTOC then the R_PPC64_TLSGD is part of a
+      // NOTOC sequence and it needs to be handled differently later on.
+      // For the TOC case the relocaiton should always be 4 byte aligned
+      // by adding 1 we can mark the NOTOC case as it will be one byte offset
+      // from the 4 byte alignment.
+      if (i->getType(config->isMips64EL) == R_PPC64_REL24_NOTOC)
+        offset++;
+    }
   }
 
   // Relax relocations.
   //
   // If we know that a PLT entry will be resolved within the same ELF module, we
   // can skip PLT access and directly jump to the destination function. For
   // example, if we are linking a main executable, all dynamic symbols that can
   // be resolved within the executable will actually be resolved that way at

lld/test/ELF/ppc64-tls-pcrel-gd.s

+# REQUIRES: ppc
+# RUN: split-file %s %t
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %t/asm -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %t/defs -o %t-defs.o
+# RUN: ld.lld --shared %t-defs.o -o %t-defs.so
+# RUN: ld.lld -T %t/lds --shared %t.o -o %t-gd.so
+# RUN: ld.lld -T %t/lds %t.o %t-defs.so -o %t-gdtoie
+# RUN: ld.lld -T %t/lds %t.o %t-defs.o -o %t-gdtole
+
+# RUN: llvm-readelf -r %t-gd.so | FileCheck %s --check-prefix=GD-RELOC
+# RUN: llvm-readelf -s %t-gd.so | FileCheck %s --check-prefix=GD-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-gd.so | FileCheck %s --check-prefix=GD
+
+# RUN: llvm-readelf -r %t-gdtoie | FileCheck %s --check-prefix=GDTOIE-RELOC
+# RUN: llvm-readelf -s %t-gdtoie | FileCheck %s --check-prefix=GDTOIE-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-gdtoie | FileCheck %s --check-prefix=GDTOIE
+
+# RUN: llvm-readelf -r %t-gdtole | FileCheck %s --check-prefix=GDTOLE-RELOC
+# RUN: llvm-readelf -s %t-gdtole | FileCheck %s --check-prefix=GDTOLE-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-gdtole | FileCheck %s --check-prefix=GDTOLE
+
+## This test checks the General Dynamic PC Relative TLS implementation for lld.
+## GD - General Dynamic with no relaxation possible
+## GDTOIE - General Dynamic relaxed to Initial Exec
+## GDTOLE - General Dynamic relaxed to Local Exec
+
+#--- lds
+SECTIONS {
+  .text_addr 0x1001000 : { *(.text_addr) }
+  .text_val 0x1002000 : { *(.text_val) }
+  .text_twoval 0x1003000 : { *(.text_twoval) }
+  .text_incrval 0x1004000 : { *(.text_incrval) }
+}
+
+#--- defs
+.section .tbss,"awT",@nobits
+.globl  x
+x:
+  .long 0
+.globl  y
+y:
+  .long 0
+
+#--- asm
+
+# GD-RELOC: Relocation section '.rela.dyn' at offset 0x100b8 contains 4 entries:
+# GD-RELOC: 0000000001004158  0000000200000044 R_PPC64_DTPMOD64       0000000000000000 x + 0
+# GD-RELOC: 0000000001004160  000000020000004e R_PPC64_DTPREL64       0000000000000000 x + 0
+# GD-RELOC: 0000000001004168  0000000300000044 R_PPC64_DTPMOD64       0000000000000000 y + 0
+# GD-RELOC: 0000000001004170  000000030000004e R_PPC64_DTPREL64       0000000000000000 y + 0
+
+# GD-SYM:   Symbol table '.dynsym' contains 4 entries:
+# GD-SYM:   2: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND x
+# GD-SYM:   3: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND y
+
+
+# GDTOIE-RELOC: Relocation section '.rela.dyn' at offset 0x10118 contains 2 entries:
+# GDTOIE-RELOC: 00000000010040e8  0000000200000049 R_PPC64_TPREL64        0000000000000000 x + 0
+# GDTOIE-RELOC: 00000000010040f0  0000000300000049 R_PPC64_TPREL64        0000000000000000 y + 0
+
+# GDTOIE-SYM: Symbol table '.dynsym' contains 4 entries:
+# GDTOIE-SYM:   2: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND x
+# GDTOIE-SYM:   3: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND y
+
+
+# GDTOLE-RELOC: There are no relocations in this file.
+
+# GDTOLE-SYM: Symbol table '.symtab' contains 8 entries:
+# GDTOLE-SYM: 6: 0000000000000000     0 TLS     GLOBAL DEFAULT     6 x
+# GDTOLE-SYM: 7: 0000000000000004     0 TLS     GLOBAL DEFAULT     6 y
+
+
+# GD-LABEL: <GDAddr>:
+# GD-NEXT:    paddi 3, 0, 12632, 1
+# GD-NEXT:    bl
+# GD-NEXT:    blr
+# GDTOIE-LABEL: <GDAddr>:
+# GDTOIE-NEXT:    pld 3, 12520(0), 1
+# GDTOIE-NEXT:    add 3, 3, 13
+# GDTOIE-NEXT:    blr
+# GDTOLE-LABEL: <GDAddr>:
+# GDTOLE-NEXT:    paddi 3, 13, -28672, 0
+# GDTOLE-NEXT:    nop
+# GDTOLE-NEXT:    blr
+.section .text_addr, "ax", %progbits
+GDAddr:
+  paddi 3, 0, x@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsgd)
+  blr
+
+# GD-LABEL: <GDVal>:
+# GD-NEXT:    paddi 3, 0, 8536, 1
+# GD-NEXT:    bl
+# GD-NEXT:    lwz 3, 0(3)
+# GD-NEXT:    blr
+# GDTOIE-LABEL: <GDVal>:
+# GDTOIE-NEXT:    pld 3, 8424(0), 1
+# GDTOIE-NEXT:    add 3, 3, 13
+# GDTOIE-NEXT:    lwz 3, 0(3)
+# GDTOIE-NEXT:    blr
+# GDTOLE-LABEL: <GDVal>:
+# GDTOLE-NEXT:    paddi 3, 13, -28672, 0
+# GDTOLE-NEXT:    nop
+# GDTOLE-NEXT:    lwz 3, 0(3)
+# GDTOLE-NEXT:    blr
+.section .text_val, "ax", %progbits
+GDVal:
+  paddi 3, 0, x@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsgd)
+  lwz 3, 0(3)
+  blr
+
+# GD-LABEL: <GDTwoVal>:
+# GD-NEXT:    paddi 3, 0, 4440, 1
+# GD-NEXT:    bl
+# GD-NEXT:    lwz 2, 0(3)
+# GD-NEXT:    paddi 3, 0, 4440, 1
+# GD-NEXT:    bl
+# GD-NEXT:    lwz 3, 0(3)
+# GD-NEXT:    add 3, 3, 2
+# GD-NEXT:    blr
+# GDTOIE-LABEL: <GDTwoVal>:
+# GDTOIE-NEXT:    pld 3, 4328(0), 1
+# GDTOIE-NEXT:    add 3, 3, 13
+# GDTOIE-NEXT:    lwz 2, 0(3)
+# GDTOIE-NEXT:    pld 3, 4320(0), 1
+# GDTOIE-NEXT:    add 3, 3, 13
+# GDTOIE-NEXT:    lwz 3, 0(3)
+# GDTOIE-NEXT:    add 3, 3, 2
+# GDTOIE-NEXT:    blr
+# GDTOLE-LABEL: <GDTwoVal>:
+# GDTOLE-NEXT:    paddi 3, 13, -28672, 0
+# GDTOLE-NEXT:    nop
+# GDTOLE-NEXT:    lwz 2, 0(3)
+# GDTOLE-NEXT:    paddi 3, 13, -28668, 0
+# GDTOLE-NEXT:    nop
+# GDTOLE-NEXT:    lwz 3, 0(3)
+# GDTOLE-NEXT:    add 3, 3, 2
+# GDTOLE-NEXT:    blr
+.section .text_twoval, "ax", %progbits
+GDTwoVal:
+        paddi 3, 0, x@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsgd)
+  lwz 2, 0(3)
+  paddi 3, 0, y@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(y@tlsgd)
+  lwz 3, 0(3)
+  add 3, 3, 2
+  blr
+
+# GD-LABEL: <GDIncrementVal>:
+# GD-NEXT:    paddi 3, 0, 360, 1
+# GD-NEXT:    bl
+# GD-NEXT:    lwz 4, 0(3)
+# GD-NEXT:    addi 5, 4, 1
+# GD-NEXT:    clrldi 4, 5, 32
+# GD-NEXT:    stw 5, 0(3)
+# GD-NEXT:    mr 3, 4
+# GD-NEXT:    blr
+# GDTOIE-LABEL: <GDIncrementVal>:
+# GDTOIE-NEXT:    pld 3, 240(0), 1
+# GDTOIE-NEXT:    add 3, 3, 13
+# GDTOIE-NEXT:    lwz 4, 0(3)
+# GDTOIE-NEXT:    addi 5, 4, 1
+# GDTOIE-NEXT:    clrldi 4, 5, 32
+# GDTOIE-NEXT:    stw 5, 0(3)
+# GDTOIE-NEXT:    mr 3, 4
+# GDTOIE-NEXT:    blr
+# GDTOLE-LABEL: <GDIncrementVal>:
+# GDTOLE-NEXT:    paddi 3, 13, -28668, 0
+# GDTOLE-NEXT:    nop
+# GDTOLE-NEXT:    lwz 4, 0(3)
+# GDTOLE-NEXT:    addi 5, 4, 1
+# GDTOLE-NEXT:    clrldi 4, 5, 32
+# GDTOLE-NEXT:    stw 5, 0(3)
+# GDTOLE-NEXT:    mr 3, 4
+# GDTOLE-NEXT:    blr
+.section .text_incrval, "ax", %progbits
+GDIncrementVal:
+        paddi 3, 0, y@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(y@tlsgd)
+  lwz 4, 0(3)
+  addi 5, 4, 1
+  clrldi  4, 5, 32
+  stw 5, 0(3)
+  mr  3, 4
+  blr