[PowerPC][PCRelative] Thread Local Storage Support for General Dynamic

[kamaub]

Summary

This patch is the initial support for the General Dynamic Thread Local
Local Storage model to produce code sequence and relocations correct
to the ABI for the model when using PC relative memory operations.

Patch by: NeHuang

[kamaub]

Updating patch with author's credits.

[kamaub]

Adding a combination flag to more explicitly set the bits needed to produce
General Dynamic TLS model relocations.

[kamaub]

Addressing clang format suggestion.

[stefanp]

Bunch of nits but overall the idea is fine. I only had one real concern with respect to the setup of InReg and you can find that in the comments.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

535

nit:
That comment is confusing a couple of things.
The reason we have to do all of this special handling is because we don't want:

__tls_get_addr(x@tlsgd)@notoc

We want:

__tls_get_addr@notoc(x@tlsgd)

Maybe:

The variant kind VK_PPC_NOTOC needs to be handled as a special case because we do not want the assembly to print out the @notoc at the end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look like __tls_get_addr@notoc(x@tlsgd).

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

493

nit:
Can you add an assert above to make sure that this MI needs to have at least 3 operands?

499

Can we just set whatever is in the else condition as the default for Kind and Opcode?
I think this may be more of a style thing but I like having defaults for variables since that way it is harder for future code to accidentally end up with a situation where someone adds an else if and forgets to define one of them.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

342

nit:
Line too long?

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

82

I'm a little worried about this setup.
In the case where IsTLSGDPCREL == true we end up with InReg not being assigned a register.
However, in that case we still do this:

const Register OrigRegs[] = {OutReg, InReg, GPR3};
// Some more code here...
LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);

Is this a safe thing to do?
Perhaps in that scenario it would be better to only have

const Register OrigRegs[] = {OutReg, GPR3};

llvm/test/CodeGen/PowerPC/pcrel-tls-general-dynamic.ll

8

nit:
Start using mcpu=pwr10 instead of future.

10

nit:
Add a little description of the test here.

llvm/test/MC/PowerPC/pcrel-tls-general-dynamic-address-load-reloc.s

23

nit:
Try to avoid using C++ mangled names. They are harder to read.
I would say rename this function and the function in the test below to describe what the function does.
eg. GDAddrLoad or GDGetAddr

[kamaub]

• Rebasing branch to more recent version of master.
• Adding asserts to ensure values are always what they are expected to be.
• Code formating and comments added.
• Conditional logic for register operands rearranged to avoid potential bugs in PPCTLSDynamicCall.cpp.

[kamaub]

• Renaming test functions names as per review comments.

[stefanp]

I think the tests can be cleaned up a little but otherwise this LGTM.

llvm/test/MC/PowerPC/pcrel-tls-general-dynamic-address-load-reloc.s

41

This is something I've learned relatively recently but you can get rid of a lot of the "extras" that compiling from C code produces. For example you can reduce most of that assembly to:

GeneralDynamicAddrLoad:
	mflr 0
	std 0, 16(1)
	stdu 1, -32(1)
	paddi 3, 0, x@got@tlsgd@pcrel, 1
	bl __tls_get_addr@notoc(x@tlsgd)
	addi 1, 1, 32
	ld 0, 16(1)
	mtlr 0
	blr

And if you want to just look at the TLS relocation (which is what you are testing) you can even remove the stack setup and teardown and have the whole test be just:

# READOBJ:        0x0 R_PPC64_GOT_TLSGD_PCREL34 x 0x0
# READOBJ-NEXT:   0x8 R_PPC64_TLSGD x 0x0
# READOBJ-NEXT:   0x8 R_PPC64_REL24_NOTOC __tls_get_addr 0x0

GeneralDynamicAddrLoad:
	paddi 3, 0, x@got@tlsgd@pcrel, 1
	bl __tls_get_addr@notoc(x@tlsgd)
	blr

llvm/test/MC/PowerPC/pcrel-tls-general-dynamic-value-load-reloc.s

25

Same thing for this test. You can remove a lot of the extra lines and just keep what you are testing.

[kamaub]

Addressing review comments and updating test cases:

• rebasing the patch on to a more recent master and fixed merge conflicts
• changed test cases to remove unnecessary bloat and update run lines.

[kamaub]

Rebasing patch on D85448 and editing test cases to use enablement option.

llvm/include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_TPREL16_HIGH
 #undef R_PPC64_TPREL16_HIGHA
 #undef R_PPC64_DTPREL16_HIGH
 #undef R_PPC64_DTPREL16_HIGHA
 #undef R_PPC64_REL24_NOTOC
 #undef R_PPC64_PCREL_OPT
 #undef R_PPC64_PCREL34
 #undef R_PPC64_GOT_PCREL34
+#undef R_PPC64_GOT_TLSGD_PCREL34
 #undef R_PPC64_IRELATIVE
 #undef R_PPC64_REL16
 #undef R_PPC64_REL16_LO
 #undef R_PPC64_REL16_HI
 #undef R_PPC64_REL16_HA
 
 ELF_RELOC(R_PPC64_NONE,                 0)
 ELF_RELOC(R_PPC64_ADDR32,               1)

 ELF_RELOC(R_PPC64_TPREL16_HIGH,         112)
 ELF_RELOC(R_PPC64_TPREL16_HIGHA,        113)
 ELF_RELOC(R_PPC64_DTPREL16_HIGH,        114)
 ELF_RELOC(R_PPC64_DTPREL16_HIGHA,       115)
 ELF_RELOC(R_PPC64_REL24_NOTOC,          116)
 ELF_RELOC(R_PPC64_PCREL_OPT,            123)
 ELF_RELOC(R_PPC64_PCREL34,              132)
 ELF_RELOC(R_PPC64_GOT_PCREL34,          133)
+ELF_RELOC(R_PPC64_GOT_TLSGD_PCREL34,    148)
 ELF_RELOC(R_PPC64_IRELATIVE,            248)
 ELF_RELOC(R_PPC64_REL16,                249)
 ELF_RELOC(R_PPC64_REL16_LO,             250)
 ELF_RELOC(R_PPC64_REL16_HI,             251)
 ELF_RELOC(R_PPC64_REL16_HA,             252)

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_TLSGD_HI,    // symbol@got@tlsgd@h
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
+    VK_PPC_GOT_TLSGD_PCREL, // symbol@got@tlsgd@pcrel
     VK_PPC_TLSLD,           // symbol@tlsld
     VK_PPC_LOCAL,           // symbol@local
     VK_PPC_NOTOC,           // symbol@notoc
     VK_PPC_PCREL_OPT,       // .reloc expr, R_PPC64_PCREL_OPT, expr
 
     VK_COFF_IMGREL32, // symbol@imgrel (image-relative)
 
     VK_Hexagon_LO16,

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
+  case VK_PPC_GOT_TLSGD_PCREL:
+    return "got@tlsgd@pcrel";
   case VK_PPC_TLSLD: return "tlsld";
   case VK_PPC_LOCAL: return "local";
   case VK_PPC_NOTOC: return "notoc";
   case VK_PPC_PCREL_OPT: return "<<invalid>>";
   case VK_COFF_IMGREL32: return "IMGREL";
   case VK_Hexagon_LO16: return "LO16";
   case VK_Hexagon_HI16: return "HI16";
   case VK_Hexagon_GPREL: return "GPREL";
return StringSwitch<VariantKind>(Name.lower())
     .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO)
     .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
     .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
     .Case("got@tlsld", VK_PPC_GOT_TLSLD)
     .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
     .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
     .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
     .Case("got@pcrel", VK_PPC_GOT_PCREL)
+    .Case("got@tlsgd@pcrel", VK_PPC_GOT_TLSGD_PCREL)
     .Case("notoc", VK_PPC_NOTOC)
     .Case("gdgot", VK_Hexagon_GD_GOT)
     .Case("gdplt", VK_Hexagon_GD_PLT)
     .Case("iegot", VK_Hexagon_IE_GOT)
     .Case("ie", VK_Hexagon_IE)
     .Case("ldgot", VK_Hexagon_LD_GOT)
     .Case("ldplt", VK_Hexagon_LD_PLT)
     .Case("none", VK_ARM_NONE)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

case PPC::fixup_ppc_pcrel34:
       default:
         llvm_unreachable("Unsupported Modifier for fixup_ppc_pcrel34");
       case MCSymbolRefExpr::VK_PCREL:
         Type = ELF::R_PPC64_PCREL34;
         break;
       case MCSymbolRefExpr::VK_PPC_GOT_PCREL:
         Type = ELF::R_PPC64_GOT_PCREL34;
         break;
+      case MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL:
+        Type = ELF::R_PPC64_GOT_TLSGD_PCREL34;
+        break;
       }
       break;
     case FK_Data_4:
     case FK_PCRel_4:
       Type = ELF::R_PPC_REL32;
       break;
     case FK_Data_8:
     case FK_PCRel_8:

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
   const MCConstantExpr *ConstExp = nullptr;
   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
   } else
     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
 
   O << RefExp->getSymbol().getName();
+  // The variant kind VK_PPC_NOTOC needs to be handled as a special case
+  // because we do not want the assembly to print out the @notoc at the
+  // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
+  // like __tls_get_addr@notoc(x@tlsgd).
+  if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
+    O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
   O << '(';
   printOperand(MI, OpNo+1, O);
   O << ')';
-  if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
+  if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
+      RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC)
     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
   if (ConstExp != nullptr)
     O << '+' << ConstExp->getValue();
 }
 
 /// showRegistersWithPercentPrefix - Check if this register name should be
 /// printed with a percentage symbol as prefix.
 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
   return new PPCMCCodeEmitter(MCII, Ctx);
 }
 
 unsigned PPCMCCodeEmitter::
 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
                     SmallVectorImpl<MCFixup> &Fixups,
                     const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
-  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
 
+  if (MO.isReg() || MO.isImm())
+    return getMachineOpValue(MI, MO, Fixups, STI);
   // Add a fixup for the branch target.
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   ((MI.getOpcode() == PPC::BL8_NOTOC)
+                                   ((MI.getOpcode() == PPC::BL8_NOTOC ||
+                                     MI.getOpcode() == PPC::BL8_NOTOC_TLS)
                                         ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
                                         : (MCFixupKind)PPC::fixup_ppc_br24)));
   return 0;
 }
 
 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
   default:
     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
   case MCExpr::SymbolRef: {
     // Relocation alone.
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
     (void)SRE;
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
-            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
-           "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
+            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
+            SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL) &&
+           "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
+           "VK_PPC_GOT_TLSGD_PCREL");
     // Generate the fixup for the relocation.
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
     // Put zero in the location of the immediate. The linker will fill in the
     // correct value based on the relocation.
     return 0;
   }

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// via the GOT. For example when combined with the MO_PCREL_FLAG it should
     /// produce the relocation @got@pcrel. Fixup is VK_PPC_GOT_PCREL.
     MO_GOT_FLAG = 8,
 
     // MO_PCREL_OPT_FLAG - If this bit is set the operand is part of a
     // PC Relative linker optimization.
     MO_PCREL_OPT_FLAG = 16,
 
+    /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
+    /// TLS General Dynamic model.
+    MO_TLSGD_FLAG = 32,
+
+    /// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
+    /// they should produce the relocation @got@tlsgd@pcrel.
+    /// Fix up is VK_PPC_GOT_TLSGD_PCREL
+    MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
+
     /// The next are not flags but distinct values.
     MO_ACCESS_MASK = 0xf00,
 
     /// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
     MO_LO = 1 << 8,
     MO_HA = 2 << 8,
 
     MO_TPREL_LO = 4 << 8,

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 
 /// EmitTlsCall -- Given a GETtls[ld]ADDR[32] instruction, print a
 /// call to __tls_get_addr to the current output stream.
 void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
                                 MCSymbolRefExpr::VariantKind VK) {
   StringRef Name = "__tls_get_addr";
   MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(Name);
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
+  unsigned Opcode = PPC::BL8_NOP_TLS;
+
+  assert(MI->getNumOperands() >= 3 && "Expecting at least 3 operands from MI");
+  if (MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG) {
+    Kind = MCSymbolRefExpr::VK_PPC_NOTOC;
+    Opcode = PPC::BL8_NOTOC_TLS;
+  }
   const Module *M = MF->getFunction().getParent();
 
   assert(MI->getOperand(0).isReg() &&
          ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
           (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
          "GETtls[ld]ADDR[32] must define GPR3");
   assert(MI->getOperand(1).isReg() &&
          ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
           (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
          "GETtls[ld]ADDR[32] must read GPR3");
if (Kind == MCSymbolRefExpr::VK_PLT && Subtarget->isSecurePlt() &&
       M->getPICLevel() == PICLevel::BigPIC)
     TlsRef = MCBinaryExpr::createAdd(
         TlsRef, MCConstantExpr::create(32768, OutContext), OutContext);
   const MachineOperand &MO = MI->getOperand(2);
   const GlobalValue *GValue = MO.getGlobal();
   MCSymbol *MOSymbol = getSymbol(GValue);
   const MCExpr *SymVar = MCSymbolRefExpr::create(MOSymbol, VK, OutContext);
   EmitToStreamer(*OutStreamer,
-                 MCInstBuilder(Subtarget->isPPC64() ?
-                               PPC::BL8_NOP_TLS : PPC::BL_TLS)
+                 MCInstBuilder(Subtarget->isPPC64() ? Opcode : PPC::BL_TLS)
                      .addExpr(TlsRef)
                      .addExpr(SymVar));
 }
 
 /// Map a machine operand for a TOC pseudo-machine instruction to its
 /// corresponding MCSymbol.
 static MCSymbol *getMCSymbolForTOCPseudoMO(const MachineOperand &MO,
                                            AsmPrinter &AP) {
   switch (MO.getType()) {
   case MachineOperand::MO_GlobalAddress:

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// lower (IDX=1) half of v4f32 to v2f64.
     FP_EXTEND_HALF,
 
     /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
     /// either through an add like PADDI or through a PC Relative load like
     /// PLD.
     MAT_PCREL_ADDR,
 
+    /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for
+    /// TLS global address when using dynamic access models. This can be done
+    /// through an add like PADDI.
+    TLS_DYNAMIC_MAT_PCREL_ADDR,
+
     // Constrained conversion from floating point to int
     STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
     STRICT_FCTIWZ,
     STRICT_FCTIDUZ,
     STRICT_FCTIWUZ,
 
     /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
     /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::VABSD:           return "PPCISD::VABSD";
   case PPCISD::BUILD_FP128:     return "PPCISD::BUILD_FP128";
   case PPCISD::BUILD_SPE64:     return "PPCISD::BUILD_SPE64";
   case PPCISD::EXTRACT_SPE:     return "PPCISD::EXTRACT_SPE";
   case PPCISD::EXTSWSLI:        return "PPCISD::EXTSWSLI";
   case PPCISD::LD_VSX_LH:       return "PPCISD::LD_VSX_LH";
   case PPCISD::FP_EXTEND_HALF:  return "PPCISD::FP_EXTEND_HALF";
   case PPCISD::MAT_PCREL_ADDR:  return "PPCISD::MAT_PCREL_ADDR";
+  case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
+    return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
   case PPCISD::LD_SPLAT:        return "PPCISD::LD_SPLAT";
   case PPCISD::FNMSUB:          return "PPCISD::FNMSUB";
   case PPCISD::STRICT_FCTIDZ:
     return "PPCISD::STRICT_FCTIDZ";
   case PPCISD::STRICT_FCTIWZ:
     return "PPCISD::STRICT_FCTIWZ";
   case PPCISD::STRICT_FCTIDUZ:
     return "PPCISD::STRICT_FCTIDUZ";
if (is64bit) {
         GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
     }
     SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
                                    PtrVT, TGA, GOTPtr);
     return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
   }
 
   if (Model == TLSModel::GeneralDynamic) {
+    if (Subtarget.isUsingPCRelativeCalls()) {
+      SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
+                                               PPCII::MO_GOT_TLSGD_PCREL_FLAG);
+      return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
+    }
+
     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
     SDValue GOTPtr;
     if (is64bit) {
       setUsesTOCBasePtr(DAG);
       SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
       GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
                                    GOTReg, TGA);
     } else {

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

let Uses = [RM], isCodeGenOnly = 1 in {
     let Predicates = [PCRelativeMemops] in {
       // BL8_NOTOC means that the caller does not use the TOC pointer and if
       // it does use R2 then it is just a caller saved register. Therefore it is
       // safe to emit only the bl and not the nop for this instruction. The
       // linker will not try to restore R2 after the call.
       def BL8_NOTOC : IForm<18, 0, 1, (outs),
                             (ins calltarget:$func),
                             "bl $func", IIC_BrB, []>;
+      def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs),
+                                (ins tlscall:$func),
+                                "bl $func", IIC_BrB, []>;
     }
   }
   let Uses = [CTR8, RM] in {
     let isPredicable = 1 in
       def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
                                 "bctrl", IIC_BrB, [(PPCbctrl)]>,
                    Requires<[In64BitMode]>;
 

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 ArrayRef<std::pair<unsigned, const char *>>
 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
   using namespace PPCII;
   static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
       {MO_GOT_FLAG, "ppc-got"},
-      {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"}};
+      {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
+      {MO_TLSGD_FLAG, "ppc-tlsgd"},
+      {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas
 // the FP ones have the advantage of lower latency and higher throughput. So
 // what we are after is using the faster instructions in low register pressure
 // situations and using the larger register file in high register pressure

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def SDTDynOp  : SDTypeProfile<1, 2, []>;
 def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
 def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
 def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
 def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>;
 
 // PC Relative Specific Nodes
 def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>;
+def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR",
+                                    SDTIntUnaryOp, []>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.
 //
 
 // A floating point immediate that is not a positive zero and can be converted
 // to a single precision floating point non-denormal immediate without loss of
 // information.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
               (PPCmatpcreladdr pcreladdr:$dst), 8),
             (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
 
   // If the PPCmatpcreladdr node is not caught by any other pattern it should be
   // caught here and turned into a paddi instruction to materialize the address.
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
+  // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize
+  // tls global address with paddi instruction.
+  def : Pat<(PPCtlsdynamatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
 let Predicates = [PrefixInstrs] in {
   def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
                                      (ins i32imm:$IMM32),
                                      "xxspltiw $XT, $IMM32", IIC_VecGeneral,
                                      []>;
   def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   }
 
   if (MO.getTargetFlags() == PPCII::MO_PLT)
     RefKind = MCSymbolRefExpr::VK_PLT;
   else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
     RefKind = MCSymbolRefExpr::VK_PCREL;
   else if (MO.getTargetFlags() == (PPCII::MO_PCREL_FLAG | PPCII::MO_GOT_FLAG))
     RefKind = MCSymbolRefExpr::VK_PPC_GOT_PCREL;
+  else if (MO.getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG)
+    RefKind = MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL;
 
   const MachineInstr *MI = MO.getParent();
   const MachineFunction *MF = MI->getMF();
   const Module *M = MF->getFunction().getParent();
   const PPCSubtarget *Subtarget = &(MF->getSubtarget<PPCSubtarget>());
   const TargetMachine &TM = Printer.TM;
 
   unsigned MIOpcode = MI->getOpcode();

llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp

struct PPCTLSDynamicCall : public MachineFunctionPass {
     const PPCInstrInfo *TII;
     LiveIntervals *LIS;
 
 protected:
     bool processBlock(MachineBasicBlock &MBB) {
       bool Changed = false;
       bool NeedFence = true;
       bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
+      bool IsTLSGDPCREL = false;
 
       for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
            I != IE;) {
         MachineInstr &MI = *I;
+        IsTLSGDPCREL = isTLSGDPCREL(MI);
 
         if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
             MI.getOpcode() != PPC::ADDItlsldLADDR &&
             MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
-            MI.getOpcode() != PPC::ADDItlsldLADDR32) {
-
+            MI.getOpcode() != PPC::ADDItlsldLADDR32 && !IsTLSGDPCREL) {
           // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
           // as scheduling fences, we skip creating fences if we already
           // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
           // which causes verification error with -verify-machineinstrs.
           if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
             NeedFence = false;
           else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
             NeedFence = true;
 
           ++I;
           continue;
         }
 
         LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n    " << MI);
 
         Register OutReg = MI.getOperand(0).getReg();
-        Register InReg = MI.getOperand(1).getReg();
-        DebugLoc DL = MI.getDebugLoc();
+        Register InReg = PPC::NoRegister;
         Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
-        unsigned Opc1, Opc2;
-        const Register OrigRegs[] = {OutReg, InReg, GPR3};
+        SmallVector<Register, 3> OrigRegs = {OutReg, GPR3};
+        if (!IsTLSGDPCREL) {
+          InReg = MI.getOperand(1).getReg();
+          OrigRegs.push_back(InReg);
+        }
+        DebugLoc DL = MI.getDebugLoc();
 
+        unsigned Opc1, Opc2;
         switch (MI.getOpcode()) {
         default:
           llvm_unreachable("Opcode inconsistency error");
         case PPC::ADDItlsgdLADDR:
           Opc1 = PPC::ADDItlsgdL;
           Opc2 = PPC::GETtlsADDR;
           break;
         case PPC::ADDItlsldLADDR:
           Opc1 = PPC::ADDItlsldL;
           Opc2 = PPC::GETtlsldADDR;
           break;
         case PPC::ADDItlsgdLADDR32:
           Opc1 = PPC::ADDItlsgdL32;
           Opc2 = PPC::GETtlsADDR32;
           break;
         case PPC::ADDItlsldLADDR32:
           Opc1 = PPC::ADDItlsldL32;
           Opc2 = PPC::GETtlsldADDR32;
           break;
+        case PPC::PADDI8pc:
+          assert(IsTLSGDPCREL && "Expecting General Dynamic PCRel");
+          Opc1 = PPC::PADDI8pc;
+          Opc2 = PPC::GETtlsADDR;
         }
 
         // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
         // as scheduling fence to avoid it is scheduled before
         // mflr in the prologue and the address in LR is clobbered (PR25839).
         // We don't really need to save data to the stack - the clobbered
         // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
         // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
                                                               .addImm(0);
 
+        MachineInstr *Addi;
+        if (IsTLSGDPCREL) {
+          Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
+        } else {
           // Expand into two ops built prior to the existing instruction.
-        MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
-          .addReg(InReg);
+          assert(InReg != PPC::NoRegister && "Operand must be a register");
+          Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
+        }
+
         Addi->addOperand(MI.getOperand(2));
 
         // The ADDItls* instruction is the first instruction in the
         // repair range.
         MachineBasicBlock::iterator First = I;
         --First;
 
         MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
                               .addReg(GPR3));
+        if (IsTLSGDPCREL)
+          Call->addOperand(MI.getOperand(2));
+        else
           Call->addOperand(MI.getOperand(3));
 
         if (NeedFence)
           BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
 
         BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
           .addReg(GPR3);
 
         // The COPY is the last instruction in the repair range.
         MachineBasicBlock::iterator Last = I;
         --Last;
 
         // Move past the original instruction and remove it.
         ++I;
         MI.removeFromParent();
 
         // Repair the live intervals.
         LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
         Changed = true;
       }
 
       return Changed;
     }
 
 public:
+  bool isTLSGDPCREL(const MachineInstr &MI) {
+    return (MI.getOpcode() == PPC::PADDI8pc) &&
+           (MI.getOperand(2).getTargetFlags() ==
+            PPCII::MO_GOT_TLSGD_PCREL_FLAG);
+  }
     bool runOnMachineFunction(MachineFunction &MF) override {
       TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
       LIS = &getAnalysis<LiveIntervals>();
 
       bool Changed = false;
 
       for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
         MachineBasicBlock &B = *I++;

llvm/test/CodeGen/PowerPC/pcrel-tls-general-dynamic.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   --relocation-model=pic -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN:   -enable-ppc-pcrel-tls < %s | FileCheck %s --check-prefix=CHECK-S
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   --relocation-model=pic -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN:   -enable-ppc-pcrel-tls --filetype=obj < %s | \
+; RUN:   llvm-objdump --mcpu=pwr10 -dr - | FileCheck %s --check-prefix=CHECK-O
+
+; These test cases are to ensure that when using pc relative memory operations
+; ABI correct code and relocations are produced for General Dynamic TLS Model.
+
+@x = external thread_local global i32, align 4
+
+define nonnull i32* @GeneralDynamicAddressLoad() {
+  ; CHECK-S-LABEL: GeneralDynamicAddressLoad:
+  ; CHECK-S:         paddi r3, 0, x@got@tlsgd@pcrel, 1
+  ; CHECK-S-NEXT:    bl __tls_get_addr@notoc(x@tlsgd)
+  ; CHECK-S-NEXT:    addi r1, r1, 32
+  ; CHECK-S-NEXT:    ld r0, 16(r1)
+  ; CHECK-S-NEXT:    mtlr r0
+  ; CHECK-S-NEXT:    blr
+  ; CHECK-O-LABEL: <GeneralDynamicAddressLoad>:
+  ; CHECK-O:         c: 00 00 10 06 00 00 60 38       paddi 3, 0, 0, 1
+  ; CHECK-O-NEXT:    000000000000000c:  R_PPC64_GOT_TLSGD_PCREL34    x
+  ; CHECK-O-NEXT:    14: 01 00 00 48                   bl 0x14
+  ; CHECK-O-NEXT:    0000000000000014:  R_PPC64_TLSGD        x
+  ; CHECK-O-NEXT:    0000000000000014:  R_PPC64_REL24_NOTOC  __tls_get_addr
+  entry:
+    ret i32* @x
+}
+
+define i32 @GeneralDynamicValueLoad() {
+  ; CHECK-S-LABEL: GeneralDynamicValueLoad:
+  ; CHECK-S:         paddi r3, 0, x@got@tlsgd@pcrel, 1
+  ; CHECK-S-NEXT:    bl __tls_get_addr@notoc(x@tlsgd)
+  ; CHECK-S-NEXT:    lwz r3, 0(r3)
+  ; CHECK-S-NEXT:    addi r1, r1, 32
+  ; CHECK-S-NEXT:    ld r0, 16(r1)
+  ; CHECK-S-NEXT:    mtlr r0
+  ; CHECK-S-NEXT:    blr
+  ; CHECK-O-LABEL: <GeneralDynamicValueLoad>:
+  ; CHECK-O:         4c: 00 00 10 06 00 00 60 38       paddi 3, 0, 0, 1
+  ; CHECK-O-NEXT:    000000000000004c:  R_PPC64_GOT_TLSGD_PCREL34    x
+  ; CHECK-O-NEXT:    54: 01 00 00 48                   bl 0x54
+  ; CHECK-O-NEXT:    0000000000000054:  R_PPC64_TLSGD        x
+  ; CHECK-O-NEXT:    0000000000000054:  R_PPC64_REL24_NOTOC  __tls_get_addr
+  ; CHECK-O-NEXT:    58: 00 00 63 80                   lwz 3, 0(3)
+  entry:
+    %0 = load i32, i32* @x, align 4
+    ret i32 %0
+}

llvm/test/MC/PowerPC/pcrel-tls-general-dynamic-address-load-reloc.s

+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s 2>&1 | \
+# RUN: FileCheck %s -check-prefix=MC
+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=READOBJ
+
+# This test checks that on Power PC we can correctly convert @got@tlsgd@pcrel
+# x@tlsgd and __tls_get_addr@notoc into R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_TLSGD
+# and R_PPC64_REL24_NOTOC for general dynamic relocations with address loaded
+
+# MC-NOT:    error: invalid variant
+
+# READOBJ:        0xC R_PPC64_GOT_TLSGD_PCREL34 x 0x0
+# READOBJ-NEXT:   0x14 R_PPC64_TLSGD x 0x0
+# READOBJ-NEXT:   0x14 R_PPC64_REL24_NOTOC __tls_get_addr 0x0
+
+GeneralDynamicAddrLoad:                 # @GeneralDynamicAddrLoad
+  mflr 0
+  std 0, 16(1)
+  stdu 1, -32(1)
+  paddi 3, 0, x@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsgd)
+  addi 1, 1, 32
+  ld 0, 16(1)
+  mtlr 0
+  blr

llvm/test/MC/PowerPC/pcrel-tls-general-dynamic-value-load-reloc.s

+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s 2>&1 | \
+# RUN: FileCheck %s -check-prefix=MC
+# RUN: llvm-mc -triple=powerpc64le-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=READOBJ
+
+# This test checks that on Power PC we can correctly convert @got@tlsgd@pcrel
+# x@tlsgd and __tls_get_addr@notoc into R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_TLSGD
+# and R_PPC64_REL24_NOTOC for general dynamic relocations with value loaded
+
+# MC-NOT:    error: invalid variant
+
+# READOBJ:        0xC R_PPC64_GOT_TLSGD_PCREL34 x 0x0
+# READOBJ-NEXT:   0x14 R_PPC64_TLSGD x 0x0
+# READOBJ-NEXT:   0x14 R_PPC64_REL24_NOTOC __tls_get_addr 0x0
+
+GeneralDynamicValueLoad:                # @GeneralDynamicValueLoad
+  mflr 0
+  std 0, 16(1)
+  stdu 1, -32(1)
+  paddi 3, 0, x@got@tlsgd@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsgd)
+  lwz 3, 0(3)
+  addi 1, 1, 32
+  ld 0, 16(1)
+  mtlr 0
+  blr