[PowerPC] Add support for R_PPC64_GOT_TPREL_PCREL34 used in TLS Initial Exec

[stefanp]

Summary

Add Thread Local Storage Initial Exec support to LLD.

This patch adds the computation for the relocations as well as the relaxation from Initial Exec to Local Exec.

Initial Exec:

pld r9, x@got@tprel@pcrel
add r9, r9, x@tls@pcrel

or

pld r9, x@got@tprel@pcrel
lbzx r10, r9, x@tls@pcrel

Note that @tls@pcrel is actually encoded as R_PPC64_TLS with a one byte displacement.

For the above examples relaxing Intitial Exec to Local Exec:

paddi r9, r9, x@tprel
nop

or

paddi r9, r13, x@tprel
lbz r10, 0(r9)

[NeHuang]

lld/ELF/Arch/PPC64.cpp

866

I am not sure if the relocation we have here will be either 4 byte aligned or offset by one byte. Seems all the code here is based on the relocation is offset by one byte. Do we need to add an error if the offset is not offset by 1 byte?

1270

Can we combine these 3 relocation cases with R_PPC64_PCREL34?

lld/test/ELF/Inputs/ppc64-tls-vardef.s

2

We can either use llvm-mc --defsym AUX=1 or extract to merge the variable definitions in ppc64-tls-pcrel-ie.s

[MaskRay]

lld/ELF/Arch/PPC64.cpp

842

In some recent code we add const whenever appropriate

845

Remove this trivial variable. Just inline its use

852

The variable can be removed.

lld/test/ELF/ppc64-tls-pcrel-ie.s

67

You can move instruction dump immediate above their related .section

Labels need to end with :

[stefanp]

Removed a couple of variables that could be inlined.
Added an error in case the offset from the 4 byte alignment is 2 or 3.
Moved checks in the test case.

[nemanjai]

Please mention the relevant sections of the ABI in the description (i.e. where it mentions the 1-byte offset). Other than that and the inline nits, LGTM. Please give @MaskRay some time to have another look before committing.

lld/ELF/Arch/PPC64.cpp

863

s/form/from

865

We have three calls to read32(loc - 1). I think that is a valid reason to have a temporary var.

869

Elaborate slightly. Why can it be turned into a nop? Presumably because the address computed by the pld points to the actual symbol now. Also, I imagine can should really be must.

[MaskRay]

Seems that this require a dependent patch to land first. I can only get around to it after llvm-mc can assemble the special form R_PPC64_TLS. Requested changes so that I will not forget it.

lld/ELF/Arch/PPC64.cpp

843

pld is used only once and can be inlined

851

locAstInt % 4 == 0

861

locAsInt % 4 == 1

870

https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements

Add braces to both then and else

875

Consider errorOrWarn whenever possible.

880

How is this conveyed in the ABI document (I don't have a copy)?

Is it: r_offset has to be 0 or 1 modulo 4?

Note that bufLoc is buffer address plus r_offset. bufLoc can be aligned while r_offset isn't.

lld/test/ELF/ppc64-tls-pcrel-ie.s

11

If a linked shared object is used to link another file, the shared object needs to specify --soname=t or another fixed string. Otherwise the DT_SONAME field of the other file is dependent on the full path of %t2.so, which can vary on different test machines.

[MaskRay]

lld/test/ELF/ppc64-tls-pcrel-ie.s

10

Consider split-file

[stefanp]

Fixed formatting and comments in a few places.
Added --soname to the test file.

lld/ELF/Arch/PPC64.cpp

866

You are correct. I should add an error here for the cases where the offset is 2 or 3 bytes offset.

880

From the ABI:
Section 3.7.3.3. Initial Exec TLS Model
Here is a paragraph from that section:

Note that both the x@tls and x@tls@pcrel assembly forms are annotated with R_PPC64_TLS
relocations. To distinguish between the two, the second of these has a field value displaced by one
byte from the beginning of the instruction.

So the idea is that R_PPC64_TLS is either aligned with the beginning of the instruction or it is off by 1 byte. On PowerPC all of the instructions are either 4 or 8 bytes so all instructions are at least 4 byte aligned. Therefore, if this relocation is 4 byte aligned it will match the beginning of an instruction.

1270

We can.
However, I don't think that this patch is the right place to do that. This is really just unrelated code cleanup. I would prefer to do it after in an NFC patch.

lld/test/ELF/Inputs/ppc64-tls-vardef.s

2

I was actually planning to use this in another test in a later patch that requires a similar setup. As a result I think I prefer to use a separate file for now.

lld/test/ELF/ppc64-tls-pcrel-ie.s

10

Sorry, I'm not sure what you mean.
Do you want me to split the SHARE and STATIC parts of this test into two tests?

[stefanp]

Updated the patch to use the NOP constant.

[stefanp]

@MaskRay
FYI: All of the dependent patches have landed so you should now be able to just apply this patch on top of trunk.

[MaskRay]

lld/ELF/Arch/PPC64.cpp

882

errorOrWarn

lld/test/ELF/Inputs/ppc64-tls-vardef.s

4

You can delete .size and move this snippet to the main file with RUN: split-file

lld/test/ELF/ppc64-tls-pcrel-ie.s

24

You can omit for lld as the whole directory is testing lld.

25

Suggest: IE and LE instead of SHARED and STATIC.

It is normally incorrect to use IE for -shared. It is for very narrow cases where dlopen is not considered and the TLS size is small.

93

Please remove unneeded instructions like add and clrldi across the file

[stefanp]

Updated error to errorOrWarn.
Merged the two test files.
Removed extra assembly from test case.

lld/ELF/Arch/PPC64.cpp

882

Sorry...
I keep missing these.

[MaskRay]

lld/test/ELF/ppc64-tls-pcrel-ie.s

10

Since you are using split-file, you can make the linker script a fragment, e.g. linkerscript/noload.s

17

.got content should be tested as well. See riscv-tls-ie.s

[stefanp]

Added the linker script to the test file.
Added a check for the GOT.

[MaskRay]

Looks great!

lld/ELF/Arch/PPC64.cpp

case R_PPC64_GOT_TPREL16_HA:
     break;
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS: {
     uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10
     write32(loc - offset, 0x3C0D0000 | regNo);          // addis RegNo, r13
     relocateNoSym(loc, R_PPC64_TPREL16_HA, val);
     break;
   }
+  case R_PPC64_GOT_TPREL_PCREL34: {
+    const uint64_t pld = readPrefixedInstruction(loc);
+    const uint64_t pldRT = pld & 0x0000000003e00000;
+    // paddi RT(from pld), r13, symbol@tprel, 0
+    writePrefixedInstruction(loc, 0x06000000380d0000 | pldRT);
+    relocateNoSym(loc, R_PPC64_TPREL34, val);
+    break;
+  }
   case R_PPC64_TLS: {
+    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
+    if ((locAsInt % 4) == 0) {
       uint32_t primaryOp = getPrimaryOpCode(read32(loc));
       if (primaryOp != 31)
         error("unrecognized instruction for IE to LE R_PPC64_TLS");
       uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30
       uint32_t dFormOp = getPPCDFormOp(secondaryOp);
       if (dFormOp == 0)
         error("unrecognized instruction for IE to LE R_PPC64_TLS");
       write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF)));
       relocateNoSym(loc + offset, R_PPC64_TPREL16_LO, val);
+    } else if ((locAsInt % 4) == 1) {
+      // If the offset is not 4 byte aligned then we have a PCRel type reloc.
+      // This version of the relocation is offset by one byte form the
+      // instruction it references.
+      uint32_t primaryOp = getPrimaryOpCode(read32(loc - 1));
+      if (primaryOp != 31)
+        error("unrecognized instruction for IE to LE R_PPC64_TLS");
+      uint32_t secondaryOp = (read32(loc - 1) & 0x000007FE) >> 1; // bits 21-30
+      // The add is a special case and can be turned into a nop.
+      if (secondaryOp == 266)
+        write32(loc - 1, 0x60000000);
+      else {
+        uint32_t dFormOp = getPPCDFormOp(secondaryOp);
+        if (dFormOp == 0)
+          error("unrecognized instruction for IE to LE R_PPC64_TLS");
+        write32(loc - 1, ((dFormOp << 26) | (read32(loc - 1) & 0x03FF0000)));
+      }
+    }
+    else
+      error("R_PPC64_TLS must be either 4 byte aligned or one byte offset "
+            "from 4 byte aligned");
     break;
   }
   default:
     llvm_unreachable("unknown relocation for IE to LE");
     break;
   }
 }
 
 RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_GOT16_LO_DS:
     return R_GOT_OFF;
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
     return R_GOTREL;
   case R_PPC64_GOT_PCREL34:
+  case R_PPC64_GOT_TPREL_PCREL34:
   case R_PPC64_PCREL_OPT:
     return R_GOT_PC;
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_LO_DS:
     return config->tocOptimize ? R_PPC64_RELAX_TOC : R_GOTREL;
   case R_PPC64_TOC:
     return R_PPC64_TOCBASE;
   case R_PPC64_REL14:
case R_PPC64_PCREL34: {
     checkInt(loc, val, 34, rel);
 
     uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
     writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |
                              (val & si1Mask));
     break;
   }
   case R_PPC64_GOT_PCREL34:
+  case R_PPC64_GOT_TPREL_PCREL34:
   case R_PPC64_TPREL34: {
     const uint64_t si0Mask = 0x00000003ffff0000;
     const uint64_t si1Mask = 0x000000000000ffff;
     const uint64_t fullMask = 0x0003ffff0000ffff;
     checkInt(loc, val, 34, rel);
 
     uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
     writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |

lld/test/ELF/Inputs/ppc64-tls-vardef.s

+## Thread Local Storage variable definitions.
+.section .tbss,"awT",@nobits
+.globl  x
+x:
+  .long 0
+  .size x, 4
+
+.globl  y
+y:
+  .long 0
+  .size y, 4

lld/test/ELF/ppc64-tls-pcrel-ie.s

+# REQUIRES: ppc
+# RUN: echo 'SECTIONS { \
+# RUN:   .text_addr 0x1001000 : { *(.text_addr) } \
+# RUN:   .text_val 0x1002000 : { *(.text_val) } \
+# RUN:   .text_twoval 0x1003000 : { *(.text_twoval) } \
+# RUN:   .text_incrval 0x1004000 : { *(.text_incrval) } \
+# RUN:   }' > %t.script
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %p/Inputs/ppc64-tls-vardef.s -o %t-defs.o
+# RUN: ld.lld --shared %t-defs.o -o %t-defs.so
+# RUN: ld.lld -T %t.script %t.o %t-defs.so -o %t-shared
+# RUN: ld.lld -T %t.script %t.o %t-defs.o -o %t-static
+
+# RUN: llvm-readelf -r %t-shared | FileCheck %s --check-prefix=SHARE-RELOC
+# RUN: llvm-readelf -s %t-shared | FileCheck %s --check-prefix=SHARE-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-shared | FileCheck %s --check-prefix=SHARE
+
+# RUN: llvm-readelf -r %t-static | FileCheck %s --check-prefix=STATIC-RELOC
+# RUN: llvm-readelf -s %t-static | FileCheck %s --check-prefix=STATIC-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-static | FileCheck %s --check-prefix=STATIC
+
+## This test checks the Initial Exec PC Relative TLS implementation for lld.
+## The SHARE version checks that the relocations are generated correctly.
+## The STATIC version checks that the Initial Exec to Local Exec relaxation is
+## done correctly.
+
+# SHARE-RELOC: Relocation section '.rela.dyn' at offset 0x100e8 contains 2 entries:
+# SHARE-RELOC: 00000000010040e0  0000000100000049 R_PPC64_TPREL64        0000000000000000 x + 0
+# SHARE-RELOC: 00000000010040e8  0000000200000049 R_PPC64_TPREL64        0000000000000000 y + 0
+
+# SHARE-SYM:   Symbol table '.dynsym' contains 3 entries:
+# SHARE-SYM:   1: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND x
+# SHARE-SYM:   2: 0000000000000000     0 TLS     GLOBAL DEFAULT   UND y
+
+# STATIC-RELOC: There are no relocations in this file.
+
+# STATIC-SYM: Symbol table '.symtab' contains 7 entries:
+# STATIC-SYM: 5: 0000000000000000     4 TLS     GLOBAL DEFAULT     6 x
+# STATIC-SYM: 6: 0000000000000004     4 TLS     GLOBAL DEFAULT     6 y
+
+# SHARE-LABEL: <IEAddr>:
+# SHARE-NEXT:    pld 3, 12512(0), 1
+# SHARE-NEXT:    add 3, 3, 13
+# SHARE-NEXT:    blr
+# STATIC-LABEL: <IEAddr>:
+# STATIC-NEXT:    paddi 3, 13, -28672, 0
+# STATIC-NEXT:    nop
+# STATIC-NEXT:    blr
+.section .text_addr, "ax", %progbits
+IEAddr:
+  pld 3, x@got@tprel@pcrel(0), 1
+  add 3, 3, x@tls@pcrel
+  blr
+
+# SHARE-LABEL: <IEVal>:
+# SHARE-NEXT:    pld 3, 8416(0), 1
+# SHARE-NEXT:    lwzx 3, 3, 13
+# SHARE-NEXT:    blr
+# STATIC-LABEL: <IEVal>:
+# STATIC-NEXT:    paddi 3, 13, -28672, 0
+# STATIC-NEXT:    lwz 3, 0(3)
+# STATIC-NEXT:    blr
+.section .text_val, "ax", %progbits
+IEVal:
+  pld 3, x@got@tprel@pcrel(0), 1
+  lwzx 3, 3, x@tls@pcrel
+  blr
+
+# SHARE-LABEL: <IETwoVal>:
+# SHARE-NEXT:    pld 3, 4320(0), 1
+# SHARE-NEXT:    pld 4, 4320(0), 1
+# SHARE-NEXT:    lwzx 3, 3, 13
+# SHARE-NEXT:    lwzx 4, 4, 13
+# SHARE-NEXT:    add 3, 4, 3
+# SHARE-NEXT:    clrldi 3, 3, 32
+# SHARE-NEXT:    blr
+# STATIC-LABEL: <IETwoVal>:
+# STATIC-NEXT:    paddi 3, 13, -28672, 0
+# STATIC-NEXT:    paddi 4, 13, -28668, 0
+# STATIC-NEXT:    lwz 3, 0(3)
+# STATIC-NEXT:    lwz 4, 0(4)
+# STATIC-NEXT:    add 3, 4, 3
+# STATIC-NEXT:    clrldi 3, 3, 32
+# STATIC-NEXT:    blr
+.section .text_twoval, "ax", %progbits
+IETwoVal:
+  pld 3, x@got@tprel@pcrel(0), 1
+  pld 4, y@got@tprel@pcrel(0), 1
+  lwzx 3, 3, x@tls@pcrel
+  lwzx 4, 4, y@tls@pcrel
+  add 3, 4, 3
+  clrldi  3, 3, 32
+  blr
+
+# SHARE-LABEL: <IEIncrementVal>:
+# SHARE-NEXT:    pld 4, 232(0), 1
+# SHARE-NEXT:    lwzx 3, 4, 13
+# SHARE-NEXT:    addi 5, 3, 1
+# SHARE-NEXT:    clrldi 3, 5, 32
+# SHARE-NEXT:    stwx 5, 4, 13
+# SHARE-NEXT:    blr
+# STATIC-LABEL: <IEIncrementVal>:
+# STATIC-NEXT:    paddi 4, 13, -28668, 0
+# STATIC-NEXT:    lwz 3, 0(4)
+# STATIC-NEXT:    addi 5, 3, 1
+# STATIC-NEXT:    clrldi 3, 5, 32
+# STATIC-NEXT:    stw 5, 0(4)
+# STATIC-NEXT:    blr
+.section .text_incrval, "ax", %progbits
+IEIncrementVal:
+  pld 4, y@got@tprel@pcrel(0), 1
+  lwzx 3, 4, y@tls@pcrel
+  addi 5, 3, 1
+  clrldi  3, 5, 32
+  stwx 5, 4, y@tls@pcrel
+  blr