[IR] Make nosync, nofree and willreturn default for intrinsics.

[sstefan1]

Summary

D70365 will allow us to make attributes default. This
is a follow up to actually make nosync, nofree and will return
default.

[jdoerfert]

Cool! the test effect shows how important this can be! I am unsure about the effect on the intrinsic definition but I guess it's not the worst. See below.

llvm/include/llvm/IR/Intrinsics.td

401

Can we define a variable with value 1 to replace the trailing 1 here?
Like: DisableDefaultAttributes.
At least we should have a comment.

We could also have a new IntrinsicClass that opts out, or one that opts in?

class DefaultIntrinsic<list<LLVMType> ret_types,
                list<LLVMType> param_types = [],
                list<IntrinsicProperty> intr_properties = [],
                string name = "",
                list<SDNodeProperty> sd_properties = []
                > : Intrinsic<ret_types, param_types, ..., /* disable_default_attributes */ 1> {}

WDYT?

[sstefan1]

llvm/include/llvm/IR/Intrinsics.td

401

I had few other things in mind, but having a new Intrinsic class looks cleanest. Also it doesn't affect the parent patch.

Do others have any opinions/objections?

[jdoerfert]

llvm/include/llvm/IR/Intrinsics.td

401

No objections. And any solution that makes it clean and easy to opt-out is fine with me.

[sstefan1]

Add DefaultIntrinsic class with default attributes disabled.

[jdoerfert]

llvm/include/llvm/IR/Intrinsics.td

401

These should be default intrinsics now?

[sstefan1]

update gc intrinsics to DefaultIntrinsic

llvm/include/llvm/IR/Intrinsics.td

401

Yes, forgot to update them.

[sstefan1]

Ping.

What should be the next step here? There was no response on the RFC update.

[arsenm]

llvm/include/llvm/IR/Intrinsics.td

31–32

Probably should group all the default attributes together

[sstefan1]

group default properties together

[sstefan1]

Its been more than a month now. Are there any additional concern about this?

[sstefan1]

Rebase

[sstefan1]

Adding @rjmccall as a reviewer as I'm unsure about some coroutine changes that appeared after rebase.

I've updated the coro tests with update_test_checks.py for simplicity. I think rest of the tests could be updated with the script as well, but I can always update them by hand if that is the preferred way.

[sstefan1]

precommit (local) coro test changes with update_test_checks

[jdoerfert]

something with the coro tests and "print" is wrong.

[efriedma]

We probably shouldn't be messing with the attributes on llvm.coro.* intrinsics. The rules for transforms around coroutine intrinsics aren't completely settled (see also https://reviews.llvm.org/D87817), but at least some of them can run arbitrary code.

[sstefan1]

In D86021#2301868, @efriedma wrote:

We probably shouldn't be messing with the attributes on llvm.coro.* intrinsics. The rules for transforms around coroutine intrinsics aren't completely settled (see also https://reviews.llvm.org/D87817), but at least some of them can run arbitrary code.

I agree. Nothing was added to llvm.coro.* intrinsics. Changes to coro tests appeared after the rebase without touching coro intrinsics. I'm trying to find out what caused those changes. Any coroutine person willing to look into it as well would be appreciated.

[sstefan1]

Actually coro intrinsics had default attributes, completelly missed that. Sorry for the confusion.
I'll update the patch shortly.

[sstefan1]

Opt-out of default attributes for llvm.coro.* intrinsics.

[jdoerfert]

I looked over all intrinsics again, 3 times I think we should opt-out. The tests look good. I'll send another reminder email because people need to update their target intrinsics as we move over.

LGTM with the nits below

llvm/include/llvm/IR/Intrinsics.td

360

Add a comment here describing the difference to the class above.

983

Opt out for these 2

1169

Opt out for these 3

1240

Make this Default too.

[nikic]

I find the naming here confusing: Looking at this patch my expectation was that DefaultIntrinsic is used for intrinsics with default attributes, based on the name. Took me a while to understand it's actually the other way around. Shouldn't the Intrinsic <-> DefaultIntrinsic naming be inverted?

[jdoerfert]

In D86021#2303405, @nikic wrote:

I find the naming here confusing: Looking at this patch my expectation was that DefaultIntrinsic is used for intrinsics with default attributes, based on the name. Took me a while to understand it's actually the other way around. Shouldn't the Intrinsic <-> DefaultIntrinsic naming be inverted?

Possible, that will make it "opt-in" for existing intrinsics again. I'm fine with either. Alternative names for this scheme:

DefaultIntrinsic -> ExplicitAttrIntrinsic?
DefaultIntrinsic -> ConservativeIntrinsic?

[sstefan1]

In D86021#2303405, @nikic wrote:

I find the naming here confusing: Looking at this patch my expectation was that DefaultIntrinsic is used for intrinsics with default attributes, based on the name. Took me a while to understand it's actually the other way around. Shouldn't the Intrinsic <-> DefaultIntrinsic naming be inverted?

I agree that it is not perfect. TBH that is one of the reasons for coro intrinsics confusion. I think there would always be some level of confusion between the two. Does OptOutIntrinsic sound better?

[sstefan1]

update clang tests

[sstefan1]

opt-out of few more intrinsics
add comment for DefaultIntrinsic class

[sstefan1]

@nikic do you have a preference on any of the suggested names?

[sstefan1]

Switch to opt-in approach. Intrinsic class now has the same meaning as bofore.
To get default attributes we now use DefaultAttrsIntrinsic.

[jdoerfert]

LGTM. We can change the name later if we need to.
This is now "opt-in" and (IIRC) we addressed all the known issues.

llvm/include/llvm/IR/Intrinsics.td

360

Nit, = 0

Also, remove disable_default_attributes from the template args and pass 0 right away. No need to overwrite it by a user, they have Intrinsic for that.

[sstefan1]

Commited in rGfbfb1c790982.

Forgot to add the revision link.

clang/test/CodeGen/builtin-sqrt.c

 // RUN: %clang_cc1 -fmath-errno -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s --check-prefix=HAS_ERRNO
 // RUN: %clang_cc1              -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck %s --check-prefix=NO_ERRNO
 
 float foo(float X) {
   // HAS_ERRNO: call float @sqrtf(float
   // NO_ERRNO: call float @llvm.sqrt.f32(float
   return __builtin_sqrtf(X);
 }
 
 // HAS_ERRNO: declare float @sqrtf(float) [[ATTR:#[0-9]+]]
 // HAS_ERRNO-NOT: attributes [[ATTR]] = {{{.*}} readnone
 
 // NO_ERRNO: declare float @llvm.sqrt.f32(float) [[ATTR:#[0-9]+]]
-// NO_ERRNO: attributes [[ATTR]] = { nounwind readnone {{.*}}}
+// NO_ERRNO: attributes [[ATTR]] = { nofree nosync nounwind readnone {{.*}}}
 

clang/test/CodeGen/libcalls.c

 // CHECK-NO: declare x86_fp80 @llvm.log.f80(x86_fp80) [[NUW_RNI]]
 // CHECK-NO: declare float @llvm.log.f32(float) [[NUW_RNI]]
 // CHECK-YES-NOT: declare double @log(double) [[NUW_RN]]
 // CHECK-YES-NOT: declare x86_fp80 @logl(x86_fp80) [[NUW_RN]]
 // CHECK-YES-NOT: declare float @logf(float) [[NUW_RN]]
 }
 
 // CHECK-NO-DAG: attributes [[NUW_RN]] = { nounwind readnone{{.*}} }
-// CHECK-NO-DAG: attributes [[NUW_RNI]] = { nounwind readnone speculatable willreturn }
+// CHECK-NO-DAG: attributes [[NUW_RNI]] = { nofree nosync nounwind readnone speculatable willreturn }

llvm/include/llvm/IR/Intrinsics.td

 
 // Intr*Mem - Memory properties.  If no property is set, the worst case
 // is assumed (it may read and write any memory it can get access to and it may
 // have other side effects).
 
 // IntrNoMem - The intrinsic does not access memory or have any other side
 // effects.  It may be CSE'd deleted if dead, etc.
 def IntrNoMem : IntrinsicProperty;
 
-// IntrNoSync - Threads executing the intrinsic will not synchronize using
-// memory or other means.
-def IntrNoSync : IntrinsicProperty;
-
 // IntrReadMem - This intrinsic only reads from memory. It does not write to
 // memory and has no other side effects. Therefore, it cannot be moved across
 // potentially aliasing stores. However, it can be reordered otherwise and can
 // be deleted if dead.
 def IntrReadMem : IntrinsicProperty;
 
 // IntrWriteMem - This intrinsic only writes to memory, but does not read from
 // memory, and has no other side effects. This means dead stores before calls
 // to this intrinsics may be removed.

 // ReadNone - The specified argument pointer is not dereferenced by the
 // intrinsic.
 class ReadNone<AttrIndex idx> : IntrinsicProperty {
   int ArgNo = idx.Value;
 }
 
 def IntrNoReturn : IntrinsicProperty;
 
-def IntrNoFree : IntrinsicProperty;
+// IntrNoSync - Threads executing the intrinsic will not synchronize using
+// memory or other means. Applied by default.
+def IntrNoSync : IntrinsicProperty<1>;
 
-def IntrWillReturn : IntrinsicProperty;
+// Applied by default.
+def IntrNoFree : IntrinsicProperty<1>;
+
+// Applied by default.
+def IntrWillReturn : IntrinsicProperty<1>;
 
 // IntrCold - Calls to this intrinsic are cold.
 // Parallels the cold attribute on LLVM IR functions.
 def IntrCold : IntrinsicProperty;
 
 // IntrNoduplicate - Calls to this intrinsic cannot be duplicated.
 // Parallels the noduplicate attribute on LLVM IR functions.
 def IntrNoDuplicate : IntrinsicProperty;

 //    intrinsic.
 //  * Properties can be set to describe the behavior of the intrinsic.
 //
 class Intrinsic<list<LLVMType> ret_types,
                 list<LLVMType> param_types = [],
                 list<IntrinsicProperty> intr_properties = [],
                 string name = "",
                 list<SDNodeProperty> sd_properties = [],
-                bit disable_default_attributes = 0> : SDPatternOperator {
+                bit disable_default_attributes = 1> : SDPatternOperator {
   string LLVMName = name;
   string TargetPrefix = "";   // Set to a prefix for target-specific intrinsics.
   list<LLVMType> RetTypes = ret_types;
   list<LLVMType> ParamTypes = param_types;
   list<IntrinsicProperty> IntrProperties = intr_properties;
   let Properties = sd_properties;
 
   // Disable applying IntrinsicProperties that are marked default with
   // IntrinsicProperty<1>
   bit DisableDefaultAttributes = disable_default_attributes;
 
   bit isTarget = 0;
 }
 
+// Intrinisc without default attributes (disable_default_attributes = 1).
+class DefaultAttrsIntrinsic<list<LLVMType> ret_types,
+                list<LLVMType> param_types = [],
+                list<IntrinsicProperty> intr_properties = [],
+                string name = "",
+                list<SDNodeProperty> sd_properties = [],
+                bit disable_default_attributes = 0>
+                : Intrinsic<ret_types, param_types,
+                            intr_properties, name,
+                            sd_properties, disable_default_attributes> {}
+
 /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this
 /// specifies the name of the builtin.  This provides automatic CBE and CFE
 /// support.
 class GCCBuiltin<string name> {
   string GCCBuiltinName = name;
 }
 
 class MSBuiltin<string name> {
   string MSBuiltinName = name;
 }
 
 
 //===--------------- Variable Argument Handling Intrinsics ----------------===//
 //
 
-def int_vastart : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_start">;
-def int_vacopy  : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
+def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [], "llvm.va_start">;
+def int_vacopy  : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [],
                             "llvm.va_copy">;
-def int_vaend   : Intrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
+def int_vaend   : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [], "llvm.va_end">;
 
 //===------------------- Garbage Collection Intrinsics --------------------===//
 //
 def int_gcroot  : Intrinsic<[],
                             [llvm_ptrptr_ty, llvm_ptr_ty]>;
 def int_gcread  : Intrinsic<[llvm_ptr_ty],
                             [llvm_ptr_ty, llvm_ptrptr_ty],
                             [IntrReadMem, IntrArgMemOnly]>;
 def int_gcwrite : Intrinsic<[],
                             [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
                             [IntrArgMemOnly, NoCapture<ArgIndex<1>>,
                              NoCapture<ArgIndex<2>>]>;
 
 //===------------------- ObjC ARC runtime Intrinsics --------------------===//
 //
 // Note these are to support the Objective-C ARC optimizer which wants to
 // eliminate retain and releases where possible.
 
 def int_objc_autorelease                    : Intrinsic<[llvm_ptr_ty],
                                                         [llvm_ptr_ty]>;
def int_objc_arc_annotation_bottomup_bbstart  : Intrinsic<[],
                                                            llvm_ptrptr_ty]>;
 def int_objc_arc_annotation_bottomup_bbend  : Intrinsic<[],
                                                         [llvm_ptrptr_ty,
                                                          llvm_ptrptr_ty]>;
 
 
 //===--------------------- Code Generator Intrinsics ----------------------===//
 //
-def int_returnaddress : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty],
+def int_returnaddress : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_i32_ty],
                                   [IntrNoMem, ImmArg<ArgIndex<0>>]>;
-def int_addressofreturnaddress : Intrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
-def int_frameaddress : Intrinsic<[llvm_anyptr_ty], [llvm_i32_ty],
+def int_addressofreturnaddress : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
+def int_frameaddress : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_i32_ty],
                                  [IntrNoMem, ImmArg<ArgIndex<0>>]>;
-def int_sponentry  : Intrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
+def int_sponentry  : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>;
 def int_read_register  : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],
                                    [IntrReadMem], "llvm.read_register">;
 def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty],
                                    [], "llvm.write_register">;
 def int_read_volatile_register  : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty],
                                             [IntrHasSideEffects],
                                              "llvm.read_volatile_register">;
 
 // Gets the address of the local variable area. This is typically a copy of the
 // stack, frame, or base pointer depending on the type of prologue.
-def int_localaddress : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
+def int_localaddress : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
 
 // Escapes local variables to allow access from other functions.
-def int_localescape : Intrinsic<[], [llvm_vararg_ty]>;
+def int_localescape : DefaultAttrsIntrinsic<[], [llvm_vararg_ty]>;
 
 // Given a function and the localaddress of a parent frame, returns a pointer
 // to an escaped allocation indicated by the index.
-def int_localrecover : Intrinsic<[llvm_ptr_ty],
+def int_localrecover : DefaultAttrsIntrinsic<[llvm_ptr_ty],
                                  [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
                                  [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 
 // Given the frame pointer passed into an SEH filter function, returns a
 // pointer to the local variable area suitable for use with llvm.localrecover.
-def int_eh_recoverfp : Intrinsic<[llvm_ptr_ty],
+def int_eh_recoverfp : DefaultAttrsIntrinsic<[llvm_ptr_ty],
                                  [llvm_ptr_ty, llvm_ptr_ty],
                                  [IntrNoMem]>;
 
 // Note: we treat stacksave/stackrestore as writemem because we don't otherwise
 // model their dependencies on allocas.
-def int_stacksave     : Intrinsic<[llvm_ptr_ty]>,
+def int_stacksave     : DefaultAttrsIntrinsic<[llvm_ptr_ty]>,
                         GCCBuiltin<"__builtin_stack_save">;
-def int_stackrestore  : Intrinsic<[], [llvm_ptr_ty]>,
+def int_stackrestore  : DefaultAttrsIntrinsic<[], [llvm_ptr_ty]>,
                         GCCBuiltin<"__builtin_stack_restore">;
 
-def int_get_dynamic_area_offset : Intrinsic<[llvm_anyint_ty]>;
+def int_get_dynamic_area_offset : DefaultAttrsIntrinsic<[llvm_anyint_ty]>;
 
-def int_thread_pointer : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>,
+def int_thread_pointer : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>,
                          GCCBuiltin<"__builtin_thread_pointer">;
 
 // IntrInaccessibleMemOrArgMemOnly is a little more pessimistic than strictly
 // necessary for prefetch, however it does conveniently prevent the prefetch
 // from being reordered overly much with respect to nearby access to the same
 // memory while not impeding optimization.
 def int_prefetch
-    : Intrinsic<[], [ llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ],
+    : DefaultAttrsIntrinsic<[], [ llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ],
                 [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
                  ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
                  ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
-def int_pcmarker      : Intrinsic<[], [llvm_i32_ty]>;
+def int_pcmarker      : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>;
 
-def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
+def int_readcyclecounter : DefaultAttrsIntrinsic<[llvm_i64_ty]>;
 
 // The assume intrinsic is marked as arbitrarily writing so that proper
 // control dependencies will be maintained.
-def int_assume        : Intrinsic<[], [llvm_i1_ty], [IntrWillReturn,
+def int_assume        : DefaultAttrsIntrinsic<[], [llvm_i1_ty], [IntrWillReturn,
                                                      NoUndef<ArgIndex<0>>]>;
 
 // Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
 // guard to the correct place on the stack frame.
-def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
-def int_stackguard : Intrinsic<[llvm_ptr_ty], [], []>;
+def int_stackprotector : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
+def int_stackguard : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], []>;
 
 // A counter increment for instrumentation based profiling.
 def int_instrprof_increment : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_i64_ty,
-                                         llvm_i32_ty, llvm_i32_ty],
-                                        []>;
+                                         llvm_i32_ty, llvm_i32_ty]>;
 
 // A counter increment with step for instrumentation based profiling.
 def int_instrprof_increment_step : Intrinsic<[],
                                         [llvm_ptr_ty, llvm_i64_ty,
-                                         llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
-                                        []>;
+                                         llvm_i32_ty, llvm_i32_ty, llvm_i64_ty]>;
 
 // A call to profile runtime for value profiling of target expressions
 // through instrumentation based profiling.
 def int_instrprof_value_profile : Intrinsic<[],
                                             [llvm_ptr_ty, llvm_i64_ty,
                                              llvm_i64_ty, llvm_i32_ty,
-                                             llvm_i32_ty],
-                                            []>;
+                                             llvm_i32_ty]>;
 
-def int_call_preallocated_setup : Intrinsic<[llvm_token_ty], [llvm_i32_ty]>;
-def int_call_preallocated_arg : Intrinsic<[llvm_ptr_ty], [llvm_token_ty, llvm_i32_ty]>;
-def int_call_preallocated_teardown : Intrinsic<[], [llvm_token_ty]>;
+def int_call_preallocated_setup : DefaultAttrsIntrinsic<[llvm_token_ty], [llvm_i32_ty]>;
+def int_call_preallocated_arg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_token_ty, llvm_i32_ty]>;
+def int_call_preallocated_teardown : DefaultAttrsIntrinsic<[], [llvm_token_ty]>;
 
 //===------------------- Standard C Library Intrinsics --------------------===//
 //
 
-def int_memcpy  : Intrinsic<[],
+def int_memcpy  : DefaultAttrsIntrinsic<[],
                             [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                              llvm_i1_ty],
                             [IntrArgMemOnly, IntrWillReturn,
                              NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
                              NoAlias<ArgIndex<0>>, NoAlias<ArgIndex<1>>,
                              WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>,
                              ImmArg<ArgIndex<3>>]>;
 
 // Memcpy semantic that is guaranteed to be inlined.
 // In particular this means that the generated code is not allowed to call any
 // external function.
 // The third argument (specifying the size) must be a constant.
 def int_memcpy_inline
-    : Intrinsic<[],
+    : DefaultAttrsIntrinsic<[],
       [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i1_ty],
       [IntrArgMemOnly, IntrWillReturn,
        NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
        NoAlias<ArgIndex<0>>, NoAlias<ArgIndex<1>>,
        WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>,
        ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
 
-def int_memmove : Intrinsic<[],
+def int_memmove : DefaultAttrsIntrinsic<[],
                             [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
                              llvm_i1_ty],
                             [IntrArgMemOnly, IntrWillReturn,
                              NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>,
                              ReadOnly<ArgIndex<1>>, ImmArg<ArgIndex<3>>]>;
-def int_memset  : Intrinsic<[],
+def int_memset  : DefaultAttrsIntrinsic<[],
                             [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,
                              llvm_i1_ty],
                             [IntrWriteMem, IntrArgMemOnly, IntrWillReturn,
                              NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>,
                              ImmArg<ArgIndex<3>>]>;
 
 // FIXME: Add version of these floating point intrinsics which allow non-default
 // rounding modes and FP exception handling.
 
 let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
-  def int_fma  : Intrinsic<[llvm_anyfloat_ty],
+  def int_fma  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                            [LLVMMatchType<0>, LLVMMatchType<0>,
                             LLVMMatchType<0>]>;
-  def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],
+  def int_fmuladd : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>,
                                LLVMMatchType<0>]>;
 
   // These functions do not read memory, but are sensitive to the
   // rounding mode. LLVM purposely does not model changes to the FP
   // environment so they can be treated as readnone.
-  def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
-  def int_sin  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_cos  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_pow  : Intrinsic<[llvm_anyfloat_ty],
+  def int_sqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_powi : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
+  def int_sin  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_cos  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_pow  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                            [LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_log  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_exp  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_copysign : Intrinsic<[llvm_anyfloat_ty],
+  def int_log  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_log10: DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_log2 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_exp  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_exp2 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_fabs : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_copysign : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                                [LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_ceil  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_trunc : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_rint  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_nearbyint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_round : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_roundeven    : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_canonicalize : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>],
+  def int_floor : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_ceil  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_trunc : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_rint  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_nearbyint : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_round : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_roundeven    : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
+  def int_canonicalize : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>],
                                    [IntrNoMem]>;
 
-  def int_lround : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
-  def int_llround : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
-  def int_lrint : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
-  def int_llrint : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_lround : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_llround : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_lrint : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
+  def int_llrint : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty]>;
 }
 
-def int_minnum : Intrinsic<[llvm_anyfloat_ty],
+def int_minnum : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]
 >;
-def int_maxnum : Intrinsic<[llvm_anyfloat_ty],
+def int_maxnum : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]
 >;
-def int_minimum : Intrinsic<[llvm_anyfloat_ty],
+def int_minimum : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]
 >;
-def int_maximum : Intrinsic<[llvm_anyfloat_ty],
+def int_maximum : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>],
   [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]
 >;
 
 // Internal interface for object size checking
-def int_objectsize : Intrinsic<[llvm_anyint_ty],
+def int_objectsize : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                [llvm_anyptr_ty, llvm_i1_ty,
                                 llvm_i1_ty, llvm_i1_ty],
                                [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>,
                                 ImmArg<ArgIndex<3>>]>,
                                GCCBuiltin<"__builtin_object_size">;
 
 //===--------------- Access to Floating Point Environment -----------------===//
 //
 
 let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in {
-  def int_flt_rounds    : Intrinsic<[llvm_i32_ty], []>;
+  def int_flt_rounds    : DefaultAttrsIntrinsic<[llvm_i32_ty], []>;
 }
 
 //===--------------- Constrained Floating Point Intrinsics ----------------===//
 //
 
 let IntrProperties = [IntrInaccessibleMemOnly, IntrWillReturn] in {
-  def int_experimental_constrained_fadd : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fadd : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_fsub : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fsub : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_fmul : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fmul : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_fdiv : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fdiv : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_frem : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_frem : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fma : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fma : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fmuladd : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fmuladd : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ LLVMMatchType<0>,
                                                          LLVMMatchType<0>,
                                                          LLVMMatchType<0>,
                                                          llvm_metadata_ty,
                                                          llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fptosi : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_fptosi : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                     [ llvm_anyfloat_ty,
                                                       llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fptoui : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_fptoui : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                     [ llvm_anyfloat_ty,
                                                       llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_sitofp : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_sitofp : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ llvm_anyint_ty,
                                                          llvm_metadata_ty,
                                                          llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_uitofp : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_uitofp : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ llvm_anyint_ty,
                                                          llvm_metadata_ty,
                                                          llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fptrunc : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fptrunc : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ llvm_anyfloat_ty,
                                                          llvm_metadata_ty,
                                                          llvm_metadata_ty ]>;
 
-  def int_experimental_constrained_fpext : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_fpext : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                      [ llvm_anyfloat_ty,
                                                        llvm_metadata_ty ]>;
 
   // These intrinsics are sensitive to the rounding mode so we need constrained
   // versions of each of them.  When strict rounding and exception control are
   // not required the non-constrained versions of these intrinsics should be
   // used.
-  def int_experimental_constrained_sqrt : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_sqrt : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_powi : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_powi : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_i32_ty,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_sin  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_sin  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_cos  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_cos  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_pow  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_pow  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_log  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_log  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_log10: Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_log10: DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_log2 : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_log2 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_exp  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_exp  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_exp2 : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_exp2 : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_rint  : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_rint  : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                      [ LLVMMatchType<0>,
                                                        llvm_metadata_ty,
                                                        llvm_metadata_ty ]>;
-  def int_experimental_constrained_nearbyint : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_nearbyint : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                          [ LLVMMatchType<0>,
                                                            llvm_metadata_ty,
                                                            llvm_metadata_ty ]>;
-  def int_experimental_constrained_lrint : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_lrint : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                      [ llvm_anyfloat_ty,
                                                        llvm_metadata_ty,
                                                        llvm_metadata_ty ]>;
-  def int_experimental_constrained_llrint : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_llrint : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                       [ llvm_anyfloat_ty,
                                                         llvm_metadata_ty,
                                                         llvm_metadata_ty ]>;
-  def int_experimental_constrained_maxnum : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_maxnum : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                       [ LLVMMatchType<0>,
                                                         LLVMMatchType<0>,
                                                         llvm_metadata_ty ]>;
-  def int_experimental_constrained_minnum : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_minnum : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                       [ LLVMMatchType<0>,
                                                         LLVMMatchType<0>,
                                                         llvm_metadata_ty ]>;
-  def int_experimental_constrained_maximum : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_maximum : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ LLVMMatchType<0>,
                                                          LLVMMatchType<0>,
                                                          llvm_metadata_ty ]>;
-  def int_experimental_constrained_minimum : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_minimum : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                        [ LLVMMatchType<0>,
                                                          LLVMMatchType<0>,
                                                          llvm_metadata_ty ]>;
-  def int_experimental_constrained_ceil : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_ceil : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                     [ LLVMMatchType<0>,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_floor : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_floor : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                      [ LLVMMatchType<0>,
                                                        llvm_metadata_ty ]>;
-  def int_experimental_constrained_lround : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_lround : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                       [ llvm_anyfloat_ty,
                                                         llvm_metadata_ty ]>;
-  def int_experimental_constrained_llround : Intrinsic<[ llvm_anyint_ty ],
+  def int_experimental_constrained_llround : DefaultAttrsIntrinsic<[ llvm_anyint_ty ],
                                                        [ llvm_anyfloat_ty,
                                                          llvm_metadata_ty ]>;
-  def int_experimental_constrained_round : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_round : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                      [ LLVMMatchType<0>,
                                                       llvm_metadata_ty ]>;
-  def int_experimental_constrained_roundeven : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_roundeven : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                          [ LLVMMatchType<0>,
                                                            llvm_metadata_ty ]>;
-  def int_experimental_constrained_trunc : Intrinsic<[ llvm_anyfloat_ty ],
+  def int_experimental_constrained_trunc : DefaultAttrsIntrinsic<[ llvm_anyfloat_ty ],
                                                      [ LLVMMatchType<0>,
                                                        llvm_metadata_ty ]>;
 
   // Constrained floating-point comparison (quiet and signaling variants).
   // Third operand is the predicate represented as a metadata string.
   def int_experimental_constrained_fcmp
-      : Intrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
+      : DefaultAttrsIntrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
                   [ llvm_anyfloat_ty, LLVMMatchType<0>,
                     llvm_metadata_ty, llvm_metadata_ty ]>;
   def int_experimental_constrained_fcmps
-      : Intrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
+      : DefaultAttrsIntrinsic<[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
                   [ llvm_anyfloat_ty, LLVMMatchType<0>,
                     llvm_metadata_ty, llvm_metadata_ty ]>;
 }
 // FIXME: Consider maybe adding intrinsics for sitofp, uitofp.
 
 //===------------------------- Expect Intrinsics --------------------------===//
 //
-def int_expect : Intrinsic<[llvm_anyint_ty],
+def int_expect : DefaultAttrsIntrinsic<[llvm_anyint_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrWillReturn]>;
 
-def int_expect_with_probability : Intrinsic<[llvm_anyint_ty],
+def int_expect_with_probability : DefaultAttrsIntrinsic<[llvm_anyint_ty],
   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_double_ty],
   [IntrNoMem, IntrWillReturn]>;
 
 //===-------------------- Bit Manipulation Intrinsics ---------------------===//
 //
 
 // None of these intrinsics accesses memory at all.
 let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
-  def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
-  def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
-  def int_bitreverse : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
-  def int_fshl : Intrinsic<[llvm_anyint_ty],
+  def int_bswap: DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
+  def int_ctpop: DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
+  def int_bitreverse : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
+  def int_fshl : DefaultAttrsIntrinsic<[llvm_anyint_ty],
       [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_fshr : Intrinsic<[llvm_anyint_ty],
+  def int_fshr : DefaultAttrsIntrinsic<[llvm_anyint_ty],
       [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>]>;
 }
 
 let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                       ImmArg<ArgIndex<1>>] in {
-  def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
-  def int_cttz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
+  def int_ctlz : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
+  def int_cttz : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
 }
 
 //===------------------------ Debugger Intrinsics -------------------------===//
 //
 
 // None of these intrinsics accesses memory at all...but that doesn't
 // mean the optimizers can change them aggressively.  Special handling
 // needed in a few places. These synthetic intrinsics have no
 // side-effects and just mark information about their operands.
 let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
-  def int_dbg_declare      : Intrinsic<[],
+  def int_dbg_declare      : DefaultAttrsIntrinsic<[],
                                        [llvm_metadata_ty,
                                         llvm_metadata_ty,
                                         llvm_metadata_ty]>;
-  def int_dbg_value        : Intrinsic<[],
+  def int_dbg_value        : DefaultAttrsIntrinsic<[],
                                        [llvm_metadata_ty,
                                         llvm_metadata_ty,
                                         llvm_metadata_ty]>;
-  def int_dbg_addr         : Intrinsic<[],
+  def int_dbg_addr         : DefaultAttrsIntrinsic<[],
                                        [llvm_metadata_ty,
                                         llvm_metadata_ty,
                                         llvm_metadata_ty]>;
-  def int_dbg_label        : Intrinsic<[],
+  def int_dbg_label        : DefaultAttrsIntrinsic<[],
                                        [llvm_metadata_ty]>;
 }
 
 //===------------------ Exception Handling Intrinsics----------------------===//
 //
 
 // The result of eh.typeid.for depends on the enclosing function, but inside a
 // given function it is 'const' and may be CSE'd etc.

 // __builtin_unwind_init is an undocumented GCC intrinsic that causes all
 // callee-saved registers to be saved and restored (regardless of whether they
 // are used) in the calling function. It is used by libgcc_eh.
 def int_eh_unwind_init: Intrinsic<[]>,
                         GCCBuiltin<"__builtin_unwind_init">;
 
 def int_eh_dwarf_cfa  : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
 
-let IntrProperties = [IntrNoMem] in {
-  def int_eh_sjlj_lsda             : Intrinsic<[llvm_ptr_ty]>;
-  def int_eh_sjlj_callsite         : Intrinsic<[], [llvm_i32_ty]>;
-}
+def int_eh_sjlj_lsda             : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
+def int_eh_sjlj_callsite         : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
+
 def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;
 def int_eh_sjlj_setjmp          : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
 def int_eh_sjlj_longjmp         : Intrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>;
 def int_eh_sjlj_setup_dispatch  : Intrinsic<[], []>;
 
 //===---------------- Generic Variable Attribute Intrinsics----------------===//
 //
-def int_var_annotation : Intrinsic<[],
+def int_var_annotation : DefaultAttrsIntrinsic<[],
                                    [llvm_ptr_ty, llvm_ptr_ty,
                                     llvm_ptr_ty, llvm_i32_ty],
                                    [IntrWillReturn], "llvm.var.annotation">;
-def int_ptr_annotation : Intrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],
+def int_ptr_annotation : DefaultAttrsIntrinsic<[LLVMAnyPointerType<llvm_anyint_ty>],
                                    [LLVMMatchType<0>, llvm_ptr_ty, llvm_ptr_ty,
                                     llvm_i32_ty],
                                    [IntrWillReturn], "llvm.ptr.annotation">;
-def int_annotation : Intrinsic<[llvm_anyint_ty],
+def int_annotation : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                [LLVMMatchType<0>, llvm_ptr_ty,
                                 llvm_ptr_ty, llvm_i32_ty],
                                [IntrWillReturn], "llvm.annotation">;
 
 // Annotates the current program point with metadata strings which are emitted
 // as CodeView debug info records. This is expensive, as it disables inlining
 // and is modelled as having side effects.
-def int_codeview_annotation : Intrinsic<[], [llvm_metadata_ty],
+def int_codeview_annotation : DefaultAttrsIntrinsic<[], [llvm_metadata_ty],
                                         [IntrInaccessibleMemOnly, IntrNoDuplicate, IntrWillReturn],
                                         "llvm.codeview.annotation">;
 
 //===------------------------ Trampoline Intrinsics -----------------------===//
 //
 def int_init_trampoline : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty],
                                     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>,
                                     GCCBuiltin<"__builtin_init_trampoline">;
 
 def int_adjust_trampoline : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty],
                                       [IntrReadMem, IntrArgMemOnly]>,
                                       GCCBuiltin<"__builtin_adjust_trampoline">;
 
 //===------------------------ Overflow Intrinsics -------------------------===//
 //
 
 // Expose the carry flag from add operations on two integrals.
 let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
-  def int_sadd_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_sadd_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_uadd_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_uadd_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
 
-  def int_ssub_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_ssub_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_usub_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_usub_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
 
-  def int_smul_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_smul_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
-  def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty,
+  def int_umul_with_overflow : DefaultAttrsIntrinsic<[llvm_anyint_ty,
                                           LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
                                          [LLVMMatchType<0>, LLVMMatchType<0>]>;
 }
 //===------------------------- Saturation Arithmetic Intrinsics ---------------------===//
 //
-def int_sadd_sat : Intrinsic<[llvm_anyint_ty],
+def int_sadd_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]>;
-def int_uadd_sat : Intrinsic<[llvm_anyint_ty],
+def int_uadd_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative]>;
-def int_ssub_sat : Intrinsic<[llvm_anyint_ty],
+def int_ssub_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_usub_sat : Intrinsic<[llvm_anyint_ty],
+def int_usub_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_sshl_sat : Intrinsic<[llvm_anyint_ty],
+def int_sshl_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_ushl_sat : Intrinsic<[llvm_anyint_ty],
+def int_ushl_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
 
 //===------------------------- Fixed Point Arithmetic Intrinsics ---------------------===//
 //
-def int_smul_fix : Intrinsic<[llvm_anyint_ty],
+def int_smul_fix : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                               Commutative, ImmArg<ArgIndex<2>>]>;
 
-def int_umul_fix : Intrinsic<[llvm_anyint_ty],
+def int_umul_fix : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                              [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                               Commutative, ImmArg<ArgIndex<2>>]>;
 
-def int_sdiv_fix : Intrinsic<[llvm_anyint_ty],
+def int_sdiv_fix : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                              [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 
-def int_udiv_fix : Intrinsic<[llvm_anyint_ty],
+def int_udiv_fix : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                              [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                              [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 
 //===------------------- Fixed Point Saturation Arithmetic Intrinsics ----------------===//
 //
-def int_smul_fix_sat : Intrinsic<[llvm_anyint_ty],
+def int_smul_fix_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                  [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                                  [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                                   Commutative, ImmArg<ArgIndex<2>>]>;
-def int_umul_fix_sat : Intrinsic<[llvm_anyint_ty],
+def int_umul_fix_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                  [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                                  [IntrNoMem, IntrSpeculatable, IntrWillReturn,
                                   Commutative, ImmArg<ArgIndex<2>>]>;
 
-def int_sdiv_fix_sat : Intrinsic<[llvm_anyint_ty],
+def int_sdiv_fix_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                  [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                                  [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 
-def int_udiv_fix_sat : Intrinsic<[llvm_anyint_ty],
+def int_udiv_fix_sat : DefaultAttrsIntrinsic<[llvm_anyint_ty],
                                  [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
                                  [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 
 //===------------------ Integer Min/Max/Abs Intrinsics --------------------===//
 //
-def int_abs : Intrinsic<
+def int_abs : DefaultAttrsIntrinsic<
     [llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty],
     [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
 
-def int_smax : Intrinsic<
+def int_smax : DefaultAttrsIntrinsic<
     [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
     [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_smin : Intrinsic<
+def int_smin : DefaultAttrsIntrinsic<
     [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
     [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_umax : Intrinsic<
+def int_umax : DefaultAttrsIntrinsic<
     [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
     [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-def int_umin : Intrinsic<
+def int_umin : DefaultAttrsIntrinsic<
     [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
     [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
 
 //===------------------------- Memory Use Markers -------------------------===//
 //
-def int_lifetime_start  : Intrinsic<[],
+def int_lifetime_start  : DefaultAttrsIntrinsic<[],
                                     [llvm_i64_ty, llvm_anyptr_ty],
                                     [IntrArgMemOnly, IntrWillReturn,
                                      NoCapture<ArgIndex<1>>,
                                      ImmArg<ArgIndex<0>>]>;
-def int_lifetime_end    : Intrinsic<[],
+def int_lifetime_end    : DefaultAttrsIntrinsic<[],
                                     [llvm_i64_ty, llvm_anyptr_ty],
                                     [IntrArgMemOnly, IntrWillReturn,
                                      NoCapture<ArgIndex<1>>,
                                      ImmArg<ArgIndex<0>>]>;
-def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
+def int_invariant_start : DefaultAttrsIntrinsic<[llvm_descriptor_ty],
                                     [llvm_i64_ty, llvm_anyptr_ty],
                                     [IntrArgMemOnly, IntrWillReturn,
                                      NoCapture<ArgIndex<1>>,
                                      ImmArg<ArgIndex<0>>]>;
-def int_invariant_end   : Intrinsic<[],
+def int_invariant_end   : DefaultAttrsIntrinsic<[],
                                     [llvm_descriptor_ty, llvm_i64_ty,
                                      llvm_anyptr_ty],
                                     [IntrArgMemOnly, IntrWillReturn,
                                      NoCapture<ArgIndex<2>>,
                                      ImmArg<ArgIndex<1>>]>;
 
 // launder.invariant.group can't be marked with 'readnone' (IntrNoMem),
 // because it would cause CSE of two barriers with the same argument.
 // Inaccessiblememonly says that the barrier doesn't read the argument,
 // but it changes state not accessible to this module. This way
 // we can DSE through the barrier because it doesn't read the value
 // after store. Although the barrier doesn't modify any memory it
 // can't be marked as readonly, because it would be possible to
 // CSE 2 barriers with store in between.
 // The argument also can't be marked with 'returned' attribute, because
 // it would remove barrier.
 // Note that it is still experimental, which means that its semantics
 // might change in the future.
-def int_launder_invariant_group : Intrinsic<[llvm_anyptr_ty],
+def int_launder_invariant_group : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                             [LLVMMatchType<0>],
                                             [IntrInaccessibleMemOnly, IntrSpeculatable, IntrWillReturn]>;
 
 
-def int_strip_invariant_group : Intrinsic<[llvm_anyptr_ty],
+def int_strip_invariant_group : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                           [LLVMMatchType<0>],
                                           [IntrSpeculatable, IntrNoMem, IntrWillReturn]>;
 
 //===------------------------ Stackmap Intrinsics -------------------------===//
 //
-def int_experimental_stackmap : Intrinsic<[],
+def int_experimental_stackmap : DefaultAttrsIntrinsic<[],
                                   [llvm_i64_ty, llvm_i32_ty, llvm_vararg_ty],
                                   [Throws]>;
-def int_experimental_patchpoint_void : Intrinsic<[],
+def int_experimental_patchpoint_void : DefaultAttrsIntrinsic<[],
                                                  [llvm_i64_ty, llvm_i32_ty,
                                                   llvm_ptr_ty, llvm_i32_ty,
                                                   llvm_vararg_ty],
                                                   [Throws]>;
-def int_experimental_patchpoint_i64 : Intrinsic<[llvm_i64_ty],
+def int_experimental_patchpoint_i64 : DefaultAttrsIntrinsic<[llvm_i64_ty],
                                                 [llvm_i64_ty, llvm_i32_ty,
                                                  llvm_ptr_ty, llvm_i32_ty,
                                                  llvm_vararg_ty],
                                                  [Throws]>;
 
 
 //===------------------------ Garbage Collection Intrinsics ---------------===//
 // These are documented in docs/Statepoint.rst
 
 def int_experimental_gc_statepoint : Intrinsic<[llvm_token_ty],
                                [llvm_i64_ty, llvm_i32_ty,
                                 llvm_anyptr_ty, llvm_i32_ty,
                                 llvm_i32_ty, llvm_vararg_ty],
                                [Throws, ImmArg<ArgIndex<0>>,
                                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>,
                                 ImmArg<ArgIndex<4>>]>;
 
 def int_experimental_gc_result   : Intrinsic<[llvm_any_ty], [llvm_token_ty],
                                              [IntrReadMem]>;
 def int_experimental_gc_relocate : Intrinsic<[llvm_any_ty],
                                              [llvm_token_ty, llvm_i32_ty,
                                               llvm_i32_ty],
                                              [IntrReadMem, ImmArg<ArgIndex<1>>,
                                               ImmArg<ArgIndex<2>>]>;
 
 //===------------------------ Coroutine Intrinsics ---------------===//
 // These are documented in docs/Coroutines.rst
 
 // Coroutine Structure Intrinsics.
 
 def int_coro_id : Intrinsic<[llvm_token_ty], [llvm_i32_ty, llvm_ptr_ty,
                              llvm_ptr_ty, llvm_ptr_ty],
def int_coro_subfn_addr : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i8_ty],
                                      ReadOnly<ArgIndex<0>>,
                                      NoCapture<ArgIndex<0>>]>;
 
 ///===-------------------------- Other Intrinsics --------------------------===//
 //
 def int_trap : Intrinsic<[], [], [IntrNoReturn, IntrCold]>,
                GCCBuiltin<"__builtin_trap">;
 def int_debugtrap : Intrinsic<[]>,
                     GCCBuiltin<"__builtin_debugtrap">;
 
 // Support for dynamic deoptimization (or de-specialization)
 def int_experimental_deoptimize : Intrinsic<[llvm_any_ty], [llvm_vararg_ty],
                                             [Throws]>;
 
 // Support for speculative runtime guards
-def int_experimental_guard : Intrinsic<[], [llvm_i1_ty, llvm_vararg_ty],
+def int_experimental_guard : DefaultAttrsIntrinsic<[], [llvm_i1_ty, llvm_vararg_ty],
                                        [Throws]>;
 
 // Supports widenable conditions for guards represented as explicit branches.
-def int_experimental_widenable_condition : Intrinsic<[llvm_i1_ty], [],
+def int_experimental_widenable_condition : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
         [IntrInaccessibleMemOnly, IntrWillReturn, IntrSpeculatable]>;
 
 // NOP: calls/invokes to this intrinsic are removed by codegen
-def int_donothing : Intrinsic<[], [], [IntrNoMem, IntrWillReturn]>;
+def int_donothing : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrWillReturn]>;
 
 // This instruction has no actual effect, though it is treated by the optimizer
 // has having opaque side effects. This may be inserted into loops to ensure
 // that they are not removed even if they turn out to be empty, for languages
 // which specify that infinite loops must be preserved.
-def int_sideeffect : Intrinsic<[], [], [IntrInaccessibleMemOnly, IntrWillReturn]>;
+def int_sideeffect : DefaultAttrsIntrinsic<[], [], [IntrInaccessibleMemOnly, IntrWillReturn]>;
 
 // Intrinsics to support half precision floating point format
 let IntrProperties = [IntrNoMem, IntrWillReturn] in {
-def int_convert_to_fp16   : Intrinsic<[llvm_i16_ty], [llvm_anyfloat_ty]>;
-def int_convert_from_fp16 : Intrinsic<[llvm_anyfloat_ty], [llvm_i16_ty]>;
+def int_convert_to_fp16   : DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_anyfloat_ty]>;
+def int_convert_from_fp16 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_i16_ty]>;
 }
 
 // Clear cache intrinsic, default to ignore (ie. emit nothing)
 // maps to void __clear_cache() on supporting platforms
 def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],
                                 [], "llvm.clear_cache">;
 
 // Intrinsic to detect whether its argument is a constant.
-def int_is_constant : Intrinsic<[llvm_i1_ty], [llvm_any_ty],
+def int_is_constant : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty],
                                 [IntrNoMem, IntrWillReturn, IntrConvergent],
                                 "llvm.is.constant">;
 
 // Intrinsic to mask out bits of a pointer.
-def int_ptrmask: Intrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>, llvm_anyint_ty],
+def int_ptrmask: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>, llvm_anyint_ty],
                            [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
 
 //===---------------- Vector Predication Intrinsics --------------===//
 
 // Binary operators
 let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
-  def int_vp_add : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_add : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                              [ LLVMMatchType<0>,
                                LLVMMatchType<0>,
                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                llvm_i32_ty]>;
-  def int_vp_sub : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_sub : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                              [ LLVMMatchType<0>,
                                LLVMMatchType<0>,
                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                llvm_i32_ty]>;
-  def int_vp_mul  : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_mul  : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_sdiv : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_sdiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_udiv : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_udiv : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_srem : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_srem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_urem : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_ashr : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_ashr : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_lshr : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_lshr : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                               [ LLVMMatchType<0>,
                                 LLVMMatchType<0>,
                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                 llvm_i32_ty]>;
-  def int_vp_shl : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_shl : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                              [ LLVMMatchType<0>,
                                LLVMMatchType<0>,
                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                llvm_i32_ty]>;
-  def int_vp_or : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_or : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                             [ LLVMMatchType<0>,
                               LLVMMatchType<0>,
                               LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                               llvm_i32_ty]>;
-  def int_vp_and : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_and : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                              [ LLVMMatchType<0>,
                                LLVMMatchType<0>,
                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                llvm_i32_ty]>;
-  def int_vp_xor : Intrinsic<[ llvm_anyvector_ty ],
+  def int_vp_xor : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
                              [ LLVMMatchType<0>,
                                LLVMMatchType<0>,
                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                llvm_i32_ty]>;
 
 }
 
 def int_get_active_lane_mask:
-  Intrinsic<[llvm_anyvector_ty],
+  DefaultAttrsIntrinsic<[llvm_anyvector_ty],
             [llvm_anyint_ty, LLVMMatchType<1>],
             [IntrNoMem, IntrNoSync, IntrWillReturn]>;
 
 //===-------------------------- Masked Intrinsics -------------------------===//
 //
 def int_masked_load:
-  Intrinsic<[llvm_anyvector_ty],
+  DefaultAttrsIntrinsic<[llvm_anyvector_ty],
             [LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,
              LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
             [IntrReadMem, IntrArgMemOnly, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
 
 def int_masked_store:
-  Intrinsic<[],
+  DefaultAttrsIntrinsic<[],
             [llvm_anyvector_ty, LLVMAnyPointerType<LLVMMatchType<0>>,
              llvm_i32_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
             [IntrWriteMem, IntrArgMemOnly, IntrWillReturn,
              ImmArg<ArgIndex<2>>]>;
 
 def int_masked_gather:
-  Intrinsic<[llvm_anyvector_ty],
+  DefaultAttrsIntrinsic<[llvm_anyvector_ty],
             [LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
              LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
             [IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
 
 def int_masked_scatter:
-  Intrinsic<[],
+  DefaultAttrsIntrinsic<[],
             [llvm_anyvector_ty, LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
              LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
             [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
 
 def int_masked_expandload:
-  Intrinsic<[llvm_anyvector_ty],
+  DefaultAttrsIntrinsic<[llvm_anyvector_ty],
             [LLVMPointerToElt<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
              LLVMMatchType<0>],
             [IntrReadMem, IntrWillReturn]>;
 
 def int_masked_compressstore:
-  Intrinsic<[],
+  DefaultAttrsIntrinsic<[],
             [llvm_anyvector_ty, LLVMPointerToElt<0>,
              LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
             [IntrWriteMem, IntrArgMemOnly, IntrWillReturn]>;
 
 // Test whether a pointer is associated with a type metadata identifier.
-def int_type_test : Intrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_metadata_ty],
+def int_type_test : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_metadata_ty],
                               [IntrNoMem, IntrWillReturn]>;
 
 // Safely loads a function pointer from a virtual table pointer using type metadata.
-def int_type_checked_load : Intrinsic<[llvm_ptr_ty, llvm_i1_ty],
+def int_type_checked_load : DefaultAttrsIntrinsic<[llvm_ptr_ty, llvm_i1_ty],
                                       [llvm_ptr_ty, llvm_i32_ty, llvm_metadata_ty],
                                       [IntrNoMem, IntrWillReturn]>;
 
 // Create a branch funnel that implements an indirect call to a limited set of
 // callees. This needs to be a musttail call.
-def int_icall_branch_funnel : Intrinsic<[], [llvm_vararg_ty], []>;
+def int_icall_branch_funnel : DefaultAttrsIntrinsic<[], [llvm_vararg_ty], []>;
 
-def int_load_relative: Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty],
+def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty],
                                  [IntrReadMem, IntrArgMemOnly]>;
 
 def int_hwasan_check_memaccess :
   Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
             [IntrInaccessibleMemOnly, ImmArg<ArgIndex<2>>]>;
 def int_hwasan_check_memaccess_shortgranules :
   Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
             [IntrInaccessibleMemOnly, ImmArg<ArgIndex<2>>]>;

 def int_memset_element_unordered_atomic
     : Intrinsic<[], [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty, llvm_i32_ty],
                 [IntrWriteMem, IntrArgMemOnly, IntrWillReturn,
                  NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>,
                  ImmArg<ArgIndex<3>>]>;
 
 //===------------------------ Reduction Intrinsics ------------------------===//
 //
-let IntrProperties = [IntrNoMem, IntrWillReturn] in {
+let IntrProperties = [IntrNoMem] in {
 
-  def int_vector_reduce_fadd : Intrinsic<[LLVMVectorElementType<0>],
+  def int_vector_reduce_fadd : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                          [LLVMVectorElementType<0>,
                                           llvm_anyvector_ty]>;
-  def int_vector_reduce_fmul : Intrinsic<[LLVMVectorElementType<0>],
+  def int_vector_reduce_fmul : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                          [LLVMVectorElementType<0>,
                                           llvm_anyvector_ty]>;
-  def int_vector_reduce_add : Intrinsic<[LLVMVectorElementType<0>],
+  def int_vector_reduce_add : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                        [llvm_anyvector_ty]>;
+  def int_vector_reduce_mul : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                        [llvm_anyvector_ty]>;
+  def int_vector_reduce_and : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                        [llvm_anyvector_ty]>;
+  def int_vector_reduce_or : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                       [llvm_anyvector_ty]>;
+  def int_vector_reduce_xor : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                        [llvm_anyvector_ty]>;
+  def int_vector_reduce_smax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_vector_reduce_smin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_vector_reduce_umax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_vector_reduce_umin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_vector_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_vector_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                         [llvm_anyvector_ty]>;
+  def int_experimental_vector_reduce_v2_fadd : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
+                                                         [LLVMMatchType<0>,
+                                                          llvm_anyvector_ty]>;
+  def int_experimental_vector_reduce_v2_fmul : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
+                                                         [LLVMMatchType<0>,
+                                                          llvm_anyvector_ty]>;
+  def int_experimental_vector_reduce_add : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                      [llvm_anyvector_ty]>;
-  def int_vector_reduce_mul : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_mul : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                      [llvm_anyvector_ty]>;
-  def int_vector_reduce_and : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_and : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                      [llvm_anyvector_ty]>;
-  def int_vector_reduce_or : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_or : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                     [llvm_anyvector_ty]>;
-  def int_vector_reduce_xor : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_xor : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                      [llvm_anyvector_ty]>;
-  def int_vector_reduce_smax : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_smax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
-  def int_vector_reduce_smin : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_smin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
-  def int_vector_reduce_umax : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_umax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
-  def int_vector_reduce_umin : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_umin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
-  def int_vector_reduce_fmax : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
-  def int_vector_reduce_fmin : Intrinsic<[LLVMVectorElementType<0>],
+  def int_experimental_vector_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
                                                       [llvm_anyvector_ty]>;
 }
 
 //===----- Matrix intrinsics ---------------------------------------------===//
 
 def int_matrix_transpose
-  : Intrinsic<[llvm_anyvector_ty],
+  : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
               [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
               [ IntrNoSync, IntrWillReturn, IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>,
                ImmArg<ArgIndex<2>>]>;
 
 def int_matrix_multiply
-  : Intrinsic<[llvm_anyvector_ty],
+  : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
               [llvm_anyvector_ty, llvm_anyvector_ty, llvm_i32_ty, llvm_i32_ty,
                llvm_i32_ty],
               [IntrNoSync, IntrWillReturn, IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>,
                ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
 
 def int_matrix_column_major_load
-  : Intrinsic<[llvm_anyvector_ty],
+  : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
               [LLVMPointerToElt<0>, llvm_i64_ty, llvm_i1_ty,
                llvm_i32_ty, llvm_i32_ty],
               [IntrNoSync, IntrWillReturn, IntrArgMemOnly, IntrReadMem,
                NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>,
                ImmArg<ArgIndex<4>>]>;
 
 def int_matrix_column_major_store
-  : Intrinsic<[],
+  : DefaultAttrsIntrinsic<[],
               [llvm_anyvector_ty, LLVMPointerToElt<0>,
                llvm_i64_ty, llvm_i1_ty, llvm_i32_ty, llvm_i32_ty],
               [IntrNoSync, IntrWillReturn, IntrArgMemOnly, IntrWriteMem,
                WriteOnly<ArgIndex<1>>, NoCapture<ArgIndex<1>>,
                ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
 
 //===---------- Intrinsics to control hardware supported loops ----------===//
 
 // Specify that the value given is the number of iterations that the next loop
 // will execute.
 def int_set_loop_iterations :
-  Intrinsic<[], [llvm_anyint_ty], [IntrNoDuplicate]>;
+  DefaultAttrsIntrinsic<[], [llvm_anyint_ty], [IntrNoDuplicate]>;
 
 // Specify that the value given is the number of iterations that the next loop
 // will execute. Also test that the given count is not zero, allowing it to
 // control entry to a 'while' loop.
 def int_test_set_loop_iterations :
-  Intrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>;
+  DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>;
 
 // Decrement loop counter by the given argument. Return false if the loop
 // should exit.
 def int_loop_decrement :
-  Intrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>;
+  DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>;
 
 // Decrement the first operand (the loop counter) by the second operand (the
 // maximum number of elements processed in an iteration). Return the remaining
 // number of iterations still to be executed. This is effectively a sub which
 // can be used with a phi, icmp and br to control the number of iterations
 // executed, as usual. Any optimisations are allowed to treat it is a sub, and
 // it's scevable, so it's the backends responsibility to handle cases where it
 // may be optimised.
 def int_loop_decrement_reg :
-  Intrinsic<[llvm_anyint_ty],
+  DefaultAttrsIntrinsic<[llvm_anyint_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoDuplicate]>;
 
 //===----- Intrinsics that are used to provide predicate information -----===//
 
-def int_ssa_copy : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>],
+def int_ssa_copy : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>],
                              [IntrNoMem, Returned<ArgIndex<0>>]>;
 
 //===------- Intrinsics that are used to preserve debug information -------===//
 
-def int_preserve_array_access_index : Intrinsic<[llvm_anyptr_ty],
+def int_preserve_array_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                                 [llvm_anyptr_ty, llvm_i32_ty,
                                                  llvm_i32_ty],
                                                 [IntrNoMem,
                                                  ImmArg<ArgIndex<1>>,
                                                  ImmArg<ArgIndex<2>>]>;
-def int_preserve_union_access_index : Intrinsic<[llvm_anyptr_ty],
+def int_preserve_union_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                                 [llvm_anyptr_ty, llvm_i32_ty],
                                                 [IntrNoMem,
                                                  ImmArg<ArgIndex<1>>]>;
-def int_preserve_struct_access_index : Intrinsic<[llvm_anyptr_ty],
+def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
                                                  [llvm_anyptr_ty, llvm_i32_ty,
                                                   llvm_i32_ty],
                                                  [IntrNoMem,
                                                   ImmArg<ArgIndex<1>>,
                                                   ImmArg<ArgIndex<2>>]>;
 
 //===---------- Intrinsics to query properties of scalable vectors --------===//
-def int_vscale : Intrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
+def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
 
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Target-specific intrinsics
 //===----------------------------------------------------------------------===//
 
 include "llvm/IR/IntrinsicsPowerPC.td"

llvm/test/Analysis/BasicAA/cs-cs.ll

 entry:
   %q = getelementptr i8, i8* %p, i64 16
   call void @a_readonly_func(i8* %p) #6 [ "unknown"() ]
   call void @an_inaccessiblememonly_func() #7 [ "unknown"() ]
   call void @an_inaccessibleorargmemonly_func(i8* %q) #8 [ "unknown"() ]
   call void @an_argmemonly_func(i8* %q) #9 [ "unknown"() ]
   ret void
 
-; CHECK: Just Ref:  Ptr: i8* %p        <->  call void @a_readonly_func(i8* %p) #8 [ "unknown"() ]
-; CHECK: Just Ref:  Ptr: i8* %q        <->  call void @a_readonly_func(i8* %p) #8 [ "unknown"() ]
-; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_inaccessiblememonly_func() #9 [ "unknown"() ]
-; CHECK: NoModRef:  Ptr: i8* %q        <->  call void @an_inaccessiblememonly_func() #9 [ "unknown"() ]
-; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ]
-; CHECK: Both ModRef (MustAlias):  Ptr: i8* %q     <->  call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ]
-; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ]
-; CHECK: Both ModRef (MustAlias):  Ptr: i8* %q     <->  call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ]
-; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ]
-; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ]
-; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ]
-; CHECK: Both ModRef:   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ]
-; CHECK: Both ModRef:   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ]
-; CHECK: NoModRef:   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ]
-; CHECK: Both ModRef:   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ]
-; CHECK: Both ModRef:   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ]
-; CHECK: Both ModRef (MustAlias):   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ]
-; CHECK: Both ModRef:   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #8 [ "unknown"() ]
-; CHECK: NoModRef:   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #9 [ "unknown"() ]
-; CHECK: Both ModRef (MustAlias):   call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ]
+; CHECK: Just Ref:  Ptr: i8* %p        <->  call void @a_readonly_func(i8* %p) #9 [ "unknown"() ]
+; CHECK: Just Ref:  Ptr: i8* %q        <->  call void @a_readonly_func(i8* %p) #9 [ "unknown"() ]
+; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_inaccessiblememonly_func() #10 [ "unknown"() ]
+; CHECK: NoModRef:  Ptr: i8* %q        <->  call void @an_inaccessiblememonly_func() #10 [ "unknown"() ]
+; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ]
+; CHECK: Both ModRef (MustAlias):  Ptr: i8* %q     <->  call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ]
+; CHECK: NoModRef:  Ptr: i8* %p        <->  call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ]
+; CHECK: Both ModRef (MustAlias):  Ptr: i8* %q     <->  call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ]
+; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ]
+; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ]
+; CHECK: Just Ref:   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ]
+; CHECK: Both ModRef:   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ]
+; CHECK: Both ModRef:   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ]
+; CHECK: NoModRef:   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ]
+; CHECK: Both ModRef:   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ]
+; CHECK: Both ModRef:   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ]
+; CHECK: Both ModRef (MustAlias):   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <->   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ]
+; CHECK: Both ModRef:   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <->   call void @a_readonly_func(i8* %p) #9 [ "unknown"() ]
+; CHECK: NoModRef:   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <->   call void @an_inaccessiblememonly_func() #10 [ "unknown"() ]
+; CHECK: Both ModRef (MustAlias):   call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <->   call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ]
 }
 
 
-; CHECK:      attributes #0 = { argmemonly nounwind willreturn writeonly }
-; CHECK-NEXT: attributes #1 = { argmemonly nounwind willreturn }
-; CHECK-NEXT: attributes #2 = { noinline nounwind readonly }
-; CHECK-NEXT: attributes #3 = { noinline nounwind writeonly }
-; CHECK-NEXT: attributes #4 = { nounwind ssp }
-; CHECK-NEXT: attributes #5 = { inaccessiblememonly nounwind }
-; CHECK-NEXT: attributes #6 = { inaccessiblemem_or_argmemonly nounwind }
-; CHECK-NEXT: attributes #7 = { argmemonly nounwind }
-; CHECK-NEXT: attributes #8 = { readonly }
-; CHECK-NEXT: attributes #9 = { inaccessiblememonly }
-; CHECK-NEXT: attributes #10 = { inaccessiblemem_or_argmemonly }
-; CHECK-NEXT: attributes #11 = { argmemonly }
+; CHECK:      attributes #0 = { argmemonly nofree nosync nounwind willreturn writeonly }
+; CHECK-NEXT: attributes #1 = { argmemonly nofree nosync nounwind willreturn }
+; CHECK-NEXT: attributes #2 = { argmemonly nounwind willreturn }
+; CHECK-NEXT: attributes #3 = { noinline nounwind readonly }
+; CHECK-NEXT: attributes #4 = { noinline nounwind writeonly }
+; CHECK-NEXT: attributes #5 = { nounwind ssp }
+; CHECK-NEXT: attributes #6 = { inaccessiblememonly nounwind }
+; CHECK-NEXT: attributes #7 = { inaccessiblemem_or_argmemonly nounwind }
+; CHECK-NEXT: attributes #8 = { argmemonly nounwind }
+; CHECK-NEXT: attributes #9 = { readonly }
+; CHECK-NEXT: attributes #10 = { inaccessiblememonly }
+; CHECK-NEXT: attributes #11 = { inaccessiblemem_or_argmemonly }
+; CHECK-NEXT: attributes #12 = { argmemonly }
 
 attributes #0 = { argmemonly nounwind }
 attributes #1 = { noinline nounwind readonly }
 attributes #2 = { noinline nounwind writeonly }
 attributes #3 = { nounwind ssp }
 attributes #4 = { inaccessiblememonly nounwind }
 attributes #5 = { inaccessiblemem_or_argmemonly nounwind }
 attributes #6 = { readonly }
 attributes #7 = { inaccessiblememonly }
 attributes #8 = { inaccessiblemem_or_argmemonly }
 attributes #9 = { argmemonly }

llvm/test/Analysis/BasicAA/intrinsics.ll

entry:
   %b = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %p, i32 16, <8 x i1> %m, <8 x i16> %pt) nounwind
   %c = add <8 x i16> %a, %b
   ret <8 x i16> %c
 }
 
 declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>) nounwind readonly
 declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind
 
-; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn }
-; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly }
+; CHECK: attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn }
+; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }
 ; CHECK: attributes [[ATTR]] = { nounwind }

llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll

 ; isn't necessarily invalid.
 
 ; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) #4 {
 define void @test2_yes(i8* %p, i8* %q, i64 %n) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i1 false), !tbaa !1
   ret void
 }
 
-; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #3 {
+; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #5 {
 define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i1 false), !tbaa !2
   ret void
 }
 
 ; Similar to the others, va_arg only accesses memory through its operand.
 
 ; CHECK: define i32 @test3_yes(i8* nocapture %p) #0 {
 define i32 @test3_yes(i8* %p) nounwind {
   %t = va_arg i8* %p, i32, !tbaa !1
   ret i32 %t
 }
 
-; CHECK: define i32 @test3_no(i8* nocapture %p) #5 {
+; CHECK: define i32 @test3_no(i8* nocapture %p) #6 {
 define i32 @test3_no(i8* %p) nounwind {
   %t = va_arg i8* %p, i32, !tbaa !2
   ret i32 %t
 }
 
 declare void @callee(i32* %p) nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1) nounwind
 
 ; CHECK: attributes #0 = { norecurse nounwind readnone }
 ; CHECK: attributes #1 = { nofree norecurse nounwind writeonly }
 ; CHECK: attributes #2 = { nounwind readonly }
 ; CHECK: attributes #3 = { nounwind }
 ; CHECK: attributes #4 = { nounwind readnone }
-; CHECK: attributes #5 = { nofree norecurse nounwind }
-; CHECK: attributes #6 = { argmemonly nounwind willreturn }
+; CHECK: attributes #5 = { nofree nounwind }
+; CHECK: attributes #6 = { nofree norecurse nounwind }
+; CHECK: attributes #7 = { argmemonly nofree nosync nounwind willreturn }
 
 ; Root note.
 !0 = !{ }
 
 ; Invariant memory.
 !1 = !{!3, !3, i64 0, i1 1 }
 ; Not invariant memory.
 !2 = !{!3, !3, i64 0, i1 0 }
 !3 = !{ !"foo", !0 }

llvm/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll

entry:
   %b = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %p, i32 16, <8 x i1> %m, <8 x i16> %pt) nounwind, !tbaa !2
   %c = add <8 x i16> %a, %b
   ret <8 x i16> %c
 }
 
 declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>) nounwind readonly
 declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind
 
-; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn }
-; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly }
+; CHECK: attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn }
+; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }
 ; CHECK: attributes [[NUW]] = { nounwind }
 
 !0 = !{!"tbaa root"}
 !1 = !{!3, !3, i64 0}
 !2 = !{!4, !4, i64 0}
 !3 = !{!"A", !0}
 !4 = !{!"B", !0}

llvm/test/Bindings/llvm-c/debug_info.ll

 ; RUN: llvm-c-test --test-dibuilder | FileCheck %s
 
 ; CHECK: ; ModuleID = 'debuginfo.c'
 ; CHECK-NEXT: source_filename = "debuginfo.c"
 
 ; CHECK:      define i64 @foo(i64 %0, i64 %1, <10 x i64> %2) !dbg !31 {
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   call void @llvm.dbg.declare(metadata i64 0, metadata !38, metadata !DIExpression()), !dbg !43
 ; CHECK-NEXT:   call void @llvm.dbg.declare(metadata i64 0, metadata !39, metadata !DIExpression()), !dbg !43
 ; CHECK-NEXT:   call void @llvm.dbg.declare(metadata i64 0, metadata !40, metadata !DIExpression()), !dbg !43
 ; CHECK:      vars:                                             ; No predecessors!
 ; CHECK-NEXT:   call void @llvm.dbg.value(metadata i64 0, metadata !41, metadata !DIExpression(DW_OP_constu, 0, DW_OP_stack_value)), !dbg !44
 ; CHECK-NEXT: }
 
-; CHECK:      ; Function Attrs: nounwind readnone speculatable
+; CHECK:      ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
 ; CHECK-NEXT: declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
 
-; CHECK:      ; Function Attrs: nounwind readnone speculatable
+; CHECK:      ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
 ; CHECK-NEXT: declare void @llvm.dbg.value(metadata, metadata, metadata) #0
 
-; CHECK:      attributes #0 = { nounwind readnone speculatable willreturn }
+; CHECK:      attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }
 
 ; CHECK:      !llvm.dbg.cu = !{!0}
 ; CHECK-NEXT: !FooType = !{!28}
 ; CHECK-NEXT: !EnumTest = !{!3}
 
 ; CHECK:      !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "llvm-c-test", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !11, imports: !19, macros: !23, splitDebugInlining: false, sysroot: "/")
 ; CHECK-NEXT: !1 = !DIFile(filename: "debuginfo.c", directory: ".")
 ; CHECK-NEXT: !2 = !{!3}

llvm/test/Bitcode/compatibility-3.6.ll

 ; CHECK: attributes #21 = { sanitize_address }
 ; CHECK: attributes #22 = { sanitize_memory }
 ; CHECK: attributes #23 = { sanitize_thread }
 ; CHECK: attributes #24 = { ssp }
 ; CHECK: attributes #25 = { sspreq }
 ; CHECK: attributes #26 = { sspstrong }
 ; CHECK: attributes #27 = { uwtable }
 ; CHECK: attributes #28 = { "cpu"="cortex-a8" }
-; CHECK: attributes #29 = { nounwind readnone willreturn }
-; CHECK: attributes #30 = { argmemonly nounwind readonly }
-; CHECK: attributes #31 = { argmemonly nounwind }
-; CHECK: attributes #32 = { nounwind readnone }
+; CHECK: attributes #29 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #30 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #31 = { argmemonly nounwind readonly }
+; CHECK: attributes #32 = { argmemonly nounwind }
 ; CHECK: attributes #33 = { nounwind readonly }
-; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #35 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-3.7.ll

 ; CHECK: attributes #24 = { sanitize_memory }
 ; CHECK: attributes #25 = { sanitize_thread }
 ; CHECK: attributes #26 = { ssp }
 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
-; CHECK: attributes #32 = { nounwind readnone willreturn }
-; CHECK: attributes #33 = { argmemonly nounwind readonly }
-; CHECK: attributes #34 = { argmemonly nounwind }
-; CHECK: attributes #35 = { nounwind readnone }
+; CHECK: attributes #32 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #33 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #34 = { argmemonly nounwind readonly }
+; CHECK: attributes #35 = { argmemonly nounwind }
 ; CHECK: attributes #36 = { nounwind readonly }
-; CHECK: attributes #37 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #37 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #38 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-3.8.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
-; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #41 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-3.9.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
 ; CHECK: attributes #40 = { writeonly }
-; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #42 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-4.0.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
 ; CHECK: attributes #40 = { writeonly }
-; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #42 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-5.0.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync  nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
 ; CHECK: attributes #40 = { writeonly }
 ; CHECK: attributes #41 = { speculatable }
-; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #43 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility-6.0.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
 ; CHECK: attributes #40 = { writeonly }
 ; CHECK: attributes #41 = { speculatable }
-; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #43 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags
 !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 ; CHECK: !llvm.module.flags = !{!0, !1, !2, !4, !5, !6}
 

llvm/test/Bitcode/compatibility.ll

 ; CHECK: attributes #27 = { sspreq }
 ; CHECK: attributes #28 = { sspstrong }
 ; CHECK: attributes #29 = { "thunk" }
 ; CHECK: attributes #30 = { uwtable }
 ; CHECK: attributes #31 = { "cpu"="cortex-a8" }
 ; CHECK: attributes #32 = { norecurse }
 ; CHECK: attributes #33 = { inaccessiblememonly }
 ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly }
-; CHECK: attributes #35 = { nounwind readnone willreturn }
-; CHECK: attributes #36 = { argmemonly nounwind readonly }
-; CHECK: attributes #37 = { argmemonly nounwind }
-; CHECK: attributes #38 = { nounwind readnone }
+; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn }
+; CHECK: attributes #36 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #37 = { argmemonly nounwind readonly }
+; CHECK: attributes #38 = { argmemonly nounwind }
 ; CHECK: attributes #39 = { nounwind readonly }
-; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nounwind willreturn }
+; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #41 = { writeonly }
 ; CHECK: attributes #42 = { speculatable }
 ; CHECK: attributes #43 = { strictfp }
 ; CHECK: attributes #44 = { builtin }
 
 ;; Metadata
 
 ; Metadata -- Module flags

llvm/test/Bitcode/upgrade-invariant-group-barrier.ll

 ; RUN: opt -S < %s | FileCheck %s
 
 ; The intrinsic firstly only took i8*, then it was made polimorphic, then
 ; it was renamed to launder.invariant.group
 define void @test(i8* %p1, i16* %p16) {
 ; CHECK-LABEL: @test
 ; CHECK: %p2 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
 ; CHECK: %p3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %p1)
 ; CHECK: %p4 = call i16* @llvm.launder.invariant.group.p0i16(i16* %p16)
   %p2 = call i8* @llvm.invariant.group.barrier(i8* %p1)
   %p3 = call i8* @llvm.invariant.group.barrier.p0i8(i8* %p1)
   %p4 = call i16* @llvm.invariant.group.barrier.p0i16(i16* %p16)
   ret void
 }
 
-; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable
+; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn
 ; CHECK: declare i8* @llvm.launder.invariant.group.p0i8(i8*)
-; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable
+; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn
 ; CHECK: declare i16* @llvm.launder.invariant.group.p0i16(i16*)
 declare i8* @llvm.invariant.group.barrier(i8*)
 declare i8* @llvm.invariant.group.barrier.p0i8(i8*)
 declare i16* @llvm.invariant.group.barrier.p0i16(i16*)

llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

define amdgpu_kernel void @store_constant_cast_group_gv_gep_to_flat_to_group() #1 {
   ret void
 }
 
 ; HSA: @ret_constant_cast_group_gv_gep_to_flat_to_group() #2
 define i32 addrspace(3)* @ret_constant_cast_group_gv_gep_to_flat_to_group() #1 {
   ret i32 addrspace(3)* addrspacecast (i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) to i32 addrspace(3)*)
 }
 
-; HSA: attributes #0 = { argmemonly nounwind willreturn }
+; HSA: attributes #0 = { argmemonly nofree nosync nounwind willreturn }
 ; HSA: attributes #1 = { nounwind }
 ; HSA: attributes #2 = { nounwind "amdgpu-queue-ptr" }
 
 attributes #0 = { argmemonly nounwind }
 attributes #1 = { nounwind }

llvm/test/Feature/intrinsics.ll

 ; CHECK: declare void @llvm.trap() #1
 declare void @llvm.trap()
 
 define void @trap() {
   call void @llvm.trap()
   ret void
 }
 
-; CHECK: attributes #0 = { nounwind readnone speculatable willreturn }
+; CHECK: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }
 ; CHECK: attributes #1 = { cold noreturn nounwind }

llvm/test/Instrumentation/MemorySanitizer/attributes.ll

 }
 
 ; CHECK-NOT: readnone
 ; CHECK-NOT: readonly
 ; CHECK-NOT: writeonly
 ; CHECK-NOT: argmemonly
 ; CHECK-NOT: speculatable
 
-; CHECK: Function Attrs: nounwind readnone willreturn
+; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn
 ; CHECK-NEXT: declare void @llvm.donothing

llvm/test/Other/invariant.group.ll

; CHECK: call void @useBool(i1 %r2)
 
   ret void
 }
 
 declare void @use(i8* readonly)
 declare void @useBool(i1)
 
 declare void @clobber(i8*)
-; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable willreturn{{$}}
+; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn{{$}}
 ; CHECK-NEXT: declare i8* @llvm.launder.invariant.group.p0i8(i8*)
 declare i8* @llvm.launder.invariant.group.p0i8(i8*)
 
-; CHECK: Function Attrs: nounwind readnone speculatable willreturn{{$}}
+; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn{{$}}
 ; CHECK-NEXT: declare i8* @llvm.strip.invariant.group.p0i8(i8*)
 declare i8* @llvm.strip.invariant.group.p0i8(i8*)
 
 
 !0 = !{}

llvm/test/Reduce/remove-attributes-from-intrinsics.ll

; CHECK-ALL: ret i32 %r
 
   %r = call "arg0" "arg1" i32 @llvm.uadd.sat.i32(i32 "arg2" "arg3" %a, i32 %a) "arg4" "arg5"
   ret i32 %r
 }
 
 ; CHECK-ALL: declare i32 @llvm.uadd.sat.i32(i32, i32) #0
 declare i32 @llvm.uadd.sat.i32(i32, i32) #0
 
-; CHECK-ALL: attributes #0 = { nounwind readnone speculatable willreturn }
+; CHECK-ALL: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }
 
 ; CHECK-INTERESTINGNESS: attributes #1 = {
 ; CHECK-INTERESTINGNESS-SAME: "arg4"
 
 ; CHECK-FINAL: attributes #1 = { "arg4" }
 
 ; CHECK-ALL-NOT: attributes #
 
 attributes #0 = { "arg6" "arg7" }

llvm/test/TableGen/intrin-side-effects.td

 
 class IntrinsicProperty<bit is_default = 0> {
   bit IsDefault = is_default;
 }
 
 def IntrNoMem : IntrinsicProperty;
 def IntrHasSideEffects : IntrinsicProperty;
 
-
 class Intrinsic<list<LLVMType> ret_types,
                 list<LLVMType> param_types = [],
                 list<IntrinsicProperty> intr_properties = [],
                 string name = "",
-                list<SDNodeProperty> sd_properties = []> : SDPatternOperator {
+                list<SDNodeProperty> sd_properties = [],
+                bit disable_default_attributes = 0> : SDPatternOperator {
   string LLVMName = name;
   string TargetPrefix = "";
   list<LLVMType> RetTypes = ret_types;
   list<LLVMType> ParamTypes = param_types;
   list<IntrinsicProperty> IntrProperties = intr_properties;
   let Properties = sd_properties;
   bit DisableDefaultAttributes = 1;
 
 
   bit isTarget = 0;
+  bit DisableDefaultAttributes = disable_default_attributes;
 }
 
 // ... this intrinsic.
 def int_random_gen   : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrHasSideEffects]>;
 
 // CHECK: 1, // llvm.random.gen
 // CHECK: case 1:
 // CHECK-NEXT: Atts[] = {Attribute::NoUnwind}

llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll

 ;
 bb:
   %tmp = load <4 x i64>, <4 x i64>* %arg1
   store <4 x i64> %tmp, <4 x i64>* %arg
   ret void
 }
 
 define void @no_promote(<4 x i64>* %arg) #1 {
-; IS__TUNIT_OPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@no_promote
-; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__TUNIT_OPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@no_promote
-; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]]
-; IS__TUNIT_NPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__TUNIT_NPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@no_promote
-; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__CGSCC_OPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@no_promote
-; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]]
-; IS__CGSCC_NPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__CGSCC_NPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <4 x i64>, align 32
   %tmp2 = alloca <4 x i64>, align 32
   %tmp3 = bitcast <4 x i64>* %tmp to i8*

 ;
 bb:
   %tmp = load <4 x i64>, <4 x i64>* %arg1
   store <4 x i64> %tmp, <4 x i64>* %arg
   ret void
 }
 
 define void @promote(<4 x i64>* %arg) #0 {
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@promote
-; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR2:#.*]] {
+; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__TUNIT_OPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@promote
-; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR2:#.*]] {
+; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32
-; IS__TUNIT_NPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR5]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR4]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__TUNIT_NPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@promote
-; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR2:#.*]] {
+; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__CGSCC_OPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@promote
-; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR2:#.*]] {
+; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32
-; IS__CGSCC_NPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR5]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR4]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32
 ; IS__CGSCC_NPM-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <4 x i64>, align 32
   %tmp2 = alloca <4 x i64>, align 32
   %tmp3 = bitcast <4 x i64>* %tmp to i8*

llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll

 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* %arg) #0 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12:#.*]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7:#.*]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12:#.*]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7:#.*]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12:#.*]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7:#.*]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12:#.*]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7:#.*]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should promote
 define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #1 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1:#.*]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR2:#.*]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR1:#.*]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg) #1 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3:#.*]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3:#.*]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should promote
 define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #1 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR2]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR1]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* %arg) #0 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*

 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* %arg) #1 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should not promote
 define internal fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #1 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg) #2 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR2:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR2:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR2:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR2:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should not promote
 define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #2 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR5:#.*]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR5:#.*]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* %arg) #1 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should promote
 define internal fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #3 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR6:#.*]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR3:#.*]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR6:#.*]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR3:#.*]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* %arg) #4 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR7:#.*]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR4:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR7:#.*]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR4:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR7:#.*]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR7:#.*]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*
   call void @llvm.memset.p0i8.i64(i8* align 32 %tmp3, i8 0, i64 32, i1 false)
   call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* %tmp2, <8 x i64>* %tmp)
   %tmp4 = load <8 x i64>, <8 x i64>* %tmp2, align 32
   store <8 x i64> %tmp4, <8 x i64>* %arg, align 2
   ret void
 }
 
 ; This should promote
 define internal fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #4 {
 ;
 ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR8:#.*]] {
+; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR4:#.*]] {
 ; IS________OPM-NEXT:  bb:
 ; IS________OPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64
 ; IS________OPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR8:#.*]] {
+; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR4:#.*]] {
 ; IS________NPM-NEXT:  bb:
 ; IS________NPM-NEXT:    [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1_PRIV]], align 64
 ; IS________NPM-NEXT:    store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64
 ; IS________NPM-NEXT:    ret void
 ;
 bb:
   %tmp = load <8 x i64>, <8 x i64>* %arg1
   store <8 x i64> %tmp, <8 x i64>* %arg
   ret void
 }
 
 define void @avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* %arg) #3 {
 ;
-; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR9:#.*]] {
+; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR3:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  bb:
 ; IS__TUNIT_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__TUNIT_OPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
-; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR9:#.*]] {
+; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR3:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  bb:
 ; IS__TUNIT_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__TUNIT_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__TUNIT_NPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__TUNIT_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR9:#.*]] {
+; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
-; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_OPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
-; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR9:#.*]] {
+; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  bb:
 ; IS__CGSCC_NPM-NEXT:    [[TMP:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP2:%.*]] = alloca <8 x i64>, align 32
 ; IS__CGSCC_NPM-NEXT:    [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]]
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64
-; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]]
+; IS__CGSCC_NPM-NEXT:    call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_NPM-NEXT:    [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64
 ; IS__CGSCC_NPM-NEXT:    store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 bb:
   %tmp = alloca <8 x i64>, align 32
   %tmp2 = alloca <8 x i64>, align 32
   %tmp3 = bitcast <8 x i64>* %tmp to i8*

llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes
 ; In PR41658, argpromotion put an inalloca in a position that per the
 ; calling convention is passed in a register. This test verifies that
 ; we don't do that anymore. It also verifies that the combination of
 ; globalopt and argpromotion is able to optimize the call safely.
 ;
-; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM
-; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM
+; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM
+; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM
 ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM
 ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM
 
 target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
 target triple = "i386-pc-windows-msvc19.11.0"
 
 %struct.a = type { i8 }
 

 
 ; This is here to ensure @internalfun is live.
 define void @exportedfun(%struct.a* %a) {
 ; CHECK-LABEL: define {{[^@]+}}@exportedfun
 ; CHECK-SAME: (%struct.a* nocapture nofree readnone [[A:%.*]]) {
 ; CHECK-NEXT:    [[INALLOCA_SAVE:%.*]] = tail call i8* @llvm.stacksave()
 ; CHECK-NEXT:    [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4
 ; CHECK-NEXT:    call x86_thiscallcc void @internalfun(%struct.a* noalias nocapture nofree readnone undef, <{ [[STRUCT_A]] }>* inalloca noundef nonnull align 4 dereferenceable(1) [[ARGMEM]])
-; CHECK-NEXT:    call void @llvm.stackrestore(i8* [[INALLOCA_SAVE]])
+; CHECK-NEXT:    call void @llvm.stackrestore(i8* nofree [[INALLOCA_SAVE]])
 ; CHECK-NEXT:    ret void
 ;
   %inalloca.save = tail call i8* @llvm.stacksave()
   %argmem = alloca inalloca <{ %struct.a }>, align 4
   call x86_thiscallcc void @internalfun(%struct.a* %a, <{ %struct.a }>* inalloca %argmem)
   call void @llvm.stackrestore(i8* %inalloca.save)
   ret void
 }
 
 declare x86_thiscallcc %struct.a* @copy_ctor(%struct.a* returned, %struct.a* dereferenceable(1))
 declare void @ext(<{ %struct.a }>* inalloca)
 declare i8* @llvm.stacksave()
 declare void @llvm.stackrestore(i8*)

llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll

 ; IS__CGSCC____-NEXT:    ret void
 ;
   %tmp = alloca %fun_t
   store %fun_t @bar, %fun_t* %tmp
   ret void
 }
 
 define internal void @bar(%p_t %p)  {
-; CHECK: Function Attrs: nosync nounwind readnone willreturn
-; CHECK-LABEL: define {{[^@]+}}@bar
-; CHECK-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR1:#.*]] {
-; CHECK-NEXT:    call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR3:#.*]], [[DBG5:!dbg !.*]]
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@bar
+; IS__TUNIT____-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR0]] {
+; IS__TUNIT____-NEXT:    call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR2:#.*]], [[DBG5:!dbg !.*]]
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@bar
+; IS__CGSCC____-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC____-NEXT:    call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR3:#.*]], [[DBG5:!dbg !.*]]
+; IS__CGSCC____-NEXT:    ret void
 ;
   call void @llvm.dbg.value(metadata %p_t %p, metadata !4, metadata !5), !dbg !6
   ret void
 }
 
 declare void @llvm.dbg.value(metadata, metadata, metadata)
 
 !llvm.dbg.cu = !{!0}

llvm/test/Transforms/Attributor/dereferenceable-1.ll

 }
 
 define void @call_fill_range(i32* nocapture %p, i64* nocapture readonly %range) {
 ; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@call_fill_range
 ; IS__TUNIT_OPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR4:#.*]] {
 ; IS__TUNIT_OPM-NEXT:  entry:
 ; IS__TUNIT_OPM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]]
-; IS__TUNIT_OPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]]
-; IS__TUNIT_OPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]]
+; IS__TUNIT_OPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]]
+; IS__TUNIT_OPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]]
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@call_fill_range
 ; IS__TUNIT_NPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR3:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  entry:
 ; IS__TUNIT_NPM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]]
-; IS__TUNIT_NPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]]
-; IS__TUNIT_NPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]]
+; IS__TUNIT_NPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]]
+; IS__TUNIT_NPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]]
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@call_fill_range
 ; IS__CGSCC_OPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR4:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  entry:
 ; IS__CGSCC_OPM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]]
-; IS__CGSCC_OPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]]
-; IS__CGSCC_OPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]]
+; IS__CGSCC_OPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR7:#.*]]
+; IS__CGSCC_OPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
 ; IS__CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_fill_range
 ; IS__CGSCC_NPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR3:#.*]] {
 ; IS__CGSCC_NPM-NEXT:  entry:
 ; IS__CGSCC_NPM-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]]
-; IS__CGSCC_NPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]]
-; IS__CGSCC_NPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]]
+; IS__CGSCC_NPM-NEXT:    tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]]
+; IS__CGSCC_NPM-NEXT:    tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]]
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
 entry:
   %0 = load i64, i64* %range, align 8, !range !0
   tail call void @fill_range_inbounds(i32* %p, i64 %0)
   tail call void @fill_range_not_inbounds(i32* %p, i64 %0)
   ret void
 }

 ; IS__TUNIT_OPM-NEXT:    br label [[IF_END8]]
 ; IS__TUNIT_OPM:       if.else3:
 ; IS__TUNIT_OPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 0
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TOBOOL4]], label [[IF_ELSE6:%.*]], label [[IF_THEN5:%.*]]
 ; IS__TUNIT_OPM:       if.then5:
 ; IS__TUNIT_OPM-NEXT:    store i32 3, i32* [[PTR]], align 4
 ; IS__TUNIT_OPM-NEXT:    br label [[IF_END8]]
 ; IS__TUNIT_OPM:       if.else6:
-; IS__TUNIT_OPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR5]]
+; IS__TUNIT_OPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR6]]
 ; IS__TUNIT_OPM-NEXT:    br label [[IF_END8]]
 ; IS__TUNIT_OPM:       if.end8:
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS________NPM: Function Attrs: argmemonly nofree nosync nounwind writeonly
 ; IS________NPM-LABEL: define {{[^@]+}}@rec-branch-2
 ; IS________NPM-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32* nocapture nofree writeonly [[PTR:%.*]]) [[ATTR4:#.*]] {
 ; IS________NPM-NEXT:  entry:

 ; IS________NPM-NEXT:    br label [[IF_END8]]
 ; IS________NPM:       if.else3:
 ; IS________NPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 0
 ; IS________NPM-NEXT:    br i1 [[TOBOOL4]], label [[IF_ELSE6:%.*]], label [[IF_THEN5:%.*]]
 ; IS________NPM:       if.then5:
 ; IS________NPM-NEXT:    store i32 3, i32* [[PTR]], align 4
 ; IS________NPM-NEXT:    br label [[IF_END8]]
 ; IS________NPM:       if.else6:
-; IS________NPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR6:#.*]]
+; IS________NPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR7:#.*]]
 ; IS________NPM-NEXT:    br label [[IF_END8]]
 ; IS________NPM:       if.end8:
 ; IS________NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind writeonly
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@rec-branch-2
 ; IS__CGSCC_OPM-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32* nocapture nofree writeonly [[PTR:%.*]]) [[ATTR5:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  entry:

 ; IS__CGSCC_OPM-NEXT:    br label [[IF_END8]]
 ; IS__CGSCC_OPM:       if.else3:
 ; IS__CGSCC_OPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 0
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL4]], label [[IF_ELSE6:%.*]], label [[IF_THEN5:%.*]]
 ; IS__CGSCC_OPM:       if.then5:
 ; IS__CGSCC_OPM-NEXT:    store i32 3, i32* [[PTR]], align 4
 ; IS__CGSCC_OPM-NEXT:    br label [[IF_END8]]
 ; IS__CGSCC_OPM:       if.else6:
-; IS__CGSCC_OPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR7:#.*]]
+; IS__CGSCC_OPM-NEXT:    tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR8:#.*]]
 ; IS__CGSCC_OPM-NEXT:    br label [[IF_END8]]
 ; IS__CGSCC_OPM:       if.end8:
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
 entry:
   %tobool = icmp eq i32 %a, 0
   br i1 %tobool, label %if.else3, label %if.then
 

 ; ATTRIBUTOR-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; ATTRIBUTOR-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]])
 ; ATTRIBUTOR-NEXT:    call void @llvm.assume(i1 true) #6 [ "nonnull"(i8* undef), "dereferenceable"(i8* undef, i64 1), "dereferenceable"(i8* undef, i64 2), "dereferenceable"(i8* undef, i64 101), "dereferenceable_or_null"(i8* undef, i64 31), "dereferenceable_or_null"(i8* undef, i64 42) ]
 ; ATTRIBUTOR-NEXT:    call void @unknown()
 ; ATTRIBUTOR-NEXT:    ret void
 ;
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; IS__TUNIT_OPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) {
-; IS__TUNIT_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR6:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
+; IS__TUNIT_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR7:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
 ; IS__TUNIT_OPM-NEXT:    call void @unknown()
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; IS________NPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) {
-; IS________NPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR7:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
+; IS________NPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR8:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
 ; IS________NPM-NEXT:    call void @unknown()
 ; IS________NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) {
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR8:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR9:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
 ; IS__CGSCC_OPM-NEXT:    call void @unknown()
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
   call void @llvm.assume(i1 true) [ "nonnull"(i8* %arg3), "dereferenceable"(i8* %arg1, i64 1), "dereferenceable"(i8* %arg1, i64 2), "dereferenceable"(i8* %arg1, i64 101), "dereferenceable_or_null"(i8* %arg2, i64 31), "dereferenceable_or_null"(i8* %arg4, i64 42)]
   call void @unknown()
   ret void
 }
 define void @nonnull_assume_neg(i8* %arg1, i8* %arg2, i8* %arg3) {

 ; ATTRIBUTOR-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(42) [[ARG4]])
 ; ATTRIBUTOR-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]])
 ; ATTRIBUTOR-NEXT:    call void @unknown()
 ; ATTRIBUTOR-NEXT:    ret void
 ;
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@nonnull_assume_call
 ; IS__TUNIT_OPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
 ; IS__TUNIT_OPM-NEXT:    call void @unknown()
-; IS__TUNIT_OPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR7:#.*]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR7]]
+; IS__TUNIT_OPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR8:#.*]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]]
 ; IS__TUNIT_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR7]]
-; IS__TUNIT_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR7]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]]
+; IS__TUNIT_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]]
 ; IS__TUNIT_OPM-NEXT:    call void @unknown()
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_assume_call
 ; IS________NPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
 ; IS________NPM-NEXT:    call void @unknown()
-; IS________NPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR8:#.*]]
-; IS________NPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]]
+; IS________NPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR9:#.*]]
+; IS________NPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]]
 ; IS________NPM-NEXT:    call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]]
-; IS________NPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]]
+; IS________NPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]]
 ; IS________NPM-NEXT:    call void @unknown()
 ; IS________NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_call
 ; IS__CGSCC_OPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
 ; IS__CGSCC_OPM-NEXT:    call void @unknown()
-; IS__CGSCC_OPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR9:#.*]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]]
+; IS__CGSCC_OPM-NEXT:    [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR10:#.*]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR10]]
 ; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]]
-; IS__CGSCC_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR10]]
+; IS__CGSCC_OPM-NEXT:    call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR10]]
 ; IS__CGSCC_OPM-NEXT:    call void @unknown()
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
   call void @unknown()
   %p = call i32* @unkown_ptr()
   call void @unknown_use32(i32* %p)
   call void @unknown_use8(i8* %arg4)
   call void @unknown_use8(i8* %arg3)

llvm/test/Transforms/Attributor/heap_to_stack.ll

;
   tail call void @free(i8* %1)
   ret i32 %3
 }
 
 define i32 @test_lifetime() {
 ; IS________OPM-LABEL: define {{[^@]+}}@test_lifetime() {
 ; IS________OPM-NEXT:    [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 noundef 4)
 ; IS________OPM-NEXT:    tail call void @no_sync_func(i8* noalias nocapture nofree [[TMP1]])
-; IS________OPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nonnull align 4 dereferenceable(4) [[TMP1]])
+; IS________OPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nofree nonnull align 4 dereferenceable(4) [[TMP1]])
 ; IS________OPM-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
 ; IS________OPM-NEXT:    store i32 10, i32* [[TMP2]], align 4
 ; IS________OPM-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
 ; IS________OPM-NEXT:    tail call void @free(i8* noalias nocapture nonnull align 4 dereferenceable(4) [[TMP1]])
 ; IS________OPM-NEXT:    ret i32 [[TMP3]]
 ;
 ; IS________NPM-LABEL: define {{[^@]+}}@test_lifetime() {
 ; IS________NPM-NEXT:    [[TMP1:%.*]] = alloca i8, i64 4, align 1
 ; IS________NPM-NEXT:    tail call void @no_sync_func(i8* noalias nocapture nofree [[TMP1]])
-; IS________NPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nonnull align 4 dereferenceable(4) [[TMP1]])
+; IS________NPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nofree nonnull align 4 dereferenceable(4) [[TMP1]])
 ; IS________NPM-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
 ; IS________NPM-NEXT:    store i32 10, i32* [[TMP2]], align 4
 ; IS________NPM-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
 ; IS________NPM-NEXT:    ret i32 [[TMP3]]
 ;
   %1 = tail call noalias i8* @malloc(i64 4)
   tail call void @no_sync_func(i8* %1)
   call void @llvm.lifetime.start.p0i8(i64 4, i8* %1)

llvm/test/Transforms/Attributor/liveness.ll

; <label>:5:                                      ; preds = %1, %3
   ret i8* %6
 }
 
 declare void @sink() nofree nosync nounwind willreturn
 define void @test_unreachable() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree noreturn nosync nounwind
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test_unreachable
 ; NOT_CGSCC_NPM-SAME: () [[ATTR0:#.*]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15:#.*]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14:#.*]]
 ; NOT_CGSCC_NPM-NEXT:    call void @test_unreachable() [[ATTR0]]
 ; NOT_CGSCC_NPM-NEXT:    unreachable
 ;
 ; IS__CGSCC____: Function Attrs: nofree noreturn nosync nounwind
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@test_unreachable
 ; IS__CGSCC____-SAME: () [[ATTR0:#.*]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16:#.*]]
 ; IS__CGSCC____-NEXT:    call void @test_unreachable() [[ATTR0]]
;
   call void @dead_e1()
   ret void
 }
 
 define internal void @non_dead_a0() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a0
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a0
 ; IS__CGSCC____-SAME: () [[ATTR13:#.*]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a1() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a1
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a1
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a2() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a2
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a2
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a3() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a3
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a3
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a4() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a4
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a4
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a5() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a5
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a5
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a6() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a6
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a6
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a7() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a7
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a7
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a8() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a8
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a8
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a9() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a9
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a9
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a10() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a10
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a10
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a11() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a11
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a11
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a12() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a12
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a12
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a13() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a13
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a13
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a14() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a14
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a14
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_a15() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a15
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a15
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b0() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b0
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b0
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b1() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b1
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b1
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b2() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b2
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b2
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b3() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b3
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b3
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b4() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b4
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b4
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b5() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b5
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b5
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b6() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b6
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b6
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b7() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b7
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b7
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b8() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b8
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b8
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b9() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b9
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b9
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b10() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b10
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b10
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b11() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b11
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b11
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b12() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b12
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b12
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b13() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b13
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b13
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b14() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b14
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b14
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_b15() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b15
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b15
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c0() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c0
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c0
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c1() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c1
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c1
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c2() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c2
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c2
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c3() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c3
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c3
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c4() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c4
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c4
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c5() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c5
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c5
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c6() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c6
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c6
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c7() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c7
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c7
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c8() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c8
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c8
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c9() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c9
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c9
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c10() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c10
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c10
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c11() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c11
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c11
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c12() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c12
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c12
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c13() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c13
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c13
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c14() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c14
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c14
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_c15() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c15
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c15
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d0() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d0
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d0
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d1() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d1
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d1
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d2() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d2
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d2
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d3() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d3
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d3
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d4() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d4
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d4
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d5() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d5
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d5
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d6() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d6
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d6
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d7() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d7
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d7
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d8() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d8
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d8
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d9() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d9
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d9
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d10() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d10
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d10
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d11() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d11
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d11
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d12() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d12
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d12
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d13() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d13
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d13
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d14() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d14
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d14
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @sink()
   ret void
 }
 define internal void @non_dead_d15() {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d15
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d15
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;

 live_with_dead_entry:
   ret void
 }
 
 define internal void @useless_arg_sink(i32* %a) {
 ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@useless_arg_sink
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@useless_arg_sink
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:    call void @sink() [[ATTR16]]
 ; IS__CGSCC____-NEXT:    ret void
 ;

 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@switch_default
 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] {
 ; NOT_CGSCC_NPM-NEXT:  entry:
 ; NOT_CGSCC_NPM-NEXT:    switch i64 0, label [[SW_DEFAULT:%.*]] [
 ; NOT_CGSCC_NPM-NEXT:    i64 3, label [[RETURN:%.*]]
 ; NOT_CGSCC_NPM-NEXT:    i64 10, label [[RETURN]]
 ; NOT_CGSCC_NPM-NEXT:    ]
 ; NOT_CGSCC_NPM:       sw.default:
-; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR15]]
+; NOT_CGSCC_NPM-NEXT:    call void @sink() [[ATTR14]]
 ; NOT_CGSCC_NPM-NEXT:    ret i32 undef
 ; NOT_CGSCC_NPM:       return:
 ; NOT_CGSCC_NPM-NEXT:    unreachable
 ;
 ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@switch_default
 ; IS__CGSCC____-SAME: () [[ATTR13]] {
 ; IS__CGSCC____-NEXT:  entry:

 }
 
 
 ; Verify we do not choke on the GEP in the unreachable block.
 
 @p = global i8 0
 
 define void @bad_gep() {
-; NOT_CGSCC_NPM: Function Attrs: nounwind readnone willreturn
+; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@bad_gep
-; NOT_CGSCC_NPM-SAME: () [[ATTR13:#.*]] {
+; NOT_CGSCC_NPM-SAME: () [[ATTR12]] {
 ; NOT_CGSCC_NPM-NEXT:  entry:
 ; NOT_CGSCC_NPM-NEXT:    [[N:%.*]] = alloca i8, align 1
 ; NOT_CGSCC_NPM-NEXT:    [[M:%.*]] = alloca i8, align 1
-; NOT_CGSCC_NPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR16:#.*]]
+; NOT_CGSCC_NPM-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR15:#.*]]
 ; NOT_CGSCC_NPM-NEXT:    br label [[EXIT:%.*]]
 ; NOT_CGSCC_NPM:       while.body:
 ; NOT_CGSCC_NPM-NEXT:    unreachable
 ; NOT_CGSCC_NPM:       if.then:
 ; NOT_CGSCC_NPM-NEXT:    unreachable
 ; NOT_CGSCC_NPM:       if.end:
 ; NOT_CGSCC_NPM-NEXT:    unreachable
 ; NOT_CGSCC_NPM:       exit:
-; NOT_CGSCC_NPM-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR16]]
+; NOT_CGSCC_NPM-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR15]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
-; IS__CGSCC____: Function Attrs: nounwind readnone willreturn
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@bad_gep
 ; IS__CGSCC____-SAME: () [[ATTR14:#.*]] {
 ; IS__CGSCC____-NEXT:  entry:
 ; IS__CGSCC____-NEXT:    [[N:%.*]] = alloca i8, align 1
 ; IS__CGSCC____-NEXT:    [[M:%.*]] = alloca i8, align 1
-; IS__CGSCC____-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR17:#.*]]
+; IS__CGSCC____-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR17:#.*]]
 ; IS__CGSCC____-NEXT:    br label [[EXIT:%.*]]
 ; IS__CGSCC____:       while.body:
 ; IS__CGSCC____-NEXT:    unreachable
 ; IS__CGSCC____:       if.then:
 ; IS__CGSCC____-NEXT:    unreachable
 ; IS__CGSCC____:       if.end:
 ; IS__CGSCC____-NEXT:    unreachable
 ; IS__CGSCC____:       exit:
-; IS__CGSCC____-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR17]]
+; IS__CGSCC____-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR17]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
 entry:
   %n = alloca i8
   %m = alloca i8
   call void @llvm.lifetime.start.p0i8(i64 1, i8* %n)
   br label %exit
 

llvm/test/Transforms/Attributor/noalias.ll

 
 ; Function Attrs: nounwind optsize
 define internal fastcc double @strtox(i8* %s, i8** %p, i32 %prec) unnamed_addr {
 ; CHECK-LABEL: define {{[^@]+}}@strtox
 ; CHECK-SAME: (i8* noalias [[S:%.*]]) unnamed_addr {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[F:%.*]] = alloca [[STRUCT__IO_FILE:%.*]], align 8
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast %struct._IO_FILE* [[F]] to i8*
-; CHECK-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture noundef nonnull align 8 dereferenceable(240) [[TMP0]]) [[ATTR10:#.*]]
+; CHECK-NEXT:    call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) [[ATTR10:#.*]]
 ; CHECK-NEXT:    [[CALL:%.*]] = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull align 8 dereferenceable(240) [[F]], i8* [[S]])
 ; CHECK-NEXT:    call void @__shlim(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i64 noundef 0)
 ; CHECK-NEXT:    [[CALL1:%.*]] = call double @__floatscan(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i32 noundef 1, i32 noundef 1)
-; CHECK-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture noundef nonnull align 8 dereferenceable(240) [[TMP0]])
+; CHECK-NEXT:    call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]])
 ; CHECK-NEXT:    ret double [[CALL1]]
 ;
 entry:
   %f = alloca %struct._IO_FILE, align 8
   %0 = bitcast %struct._IO_FILE* %f to i8*
   call void @llvm.lifetime.start.p0i8(i64 144, i8* nonnull %0)
   %call = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull %f, i8* %s)
   call void @__shlim(%struct._IO_FILE* nonnull %f, i64 0)

llvm/test/Transforms/Attributor/nocapture-1.ll

;
   %lookup = getelementptr [2 x i1], [2 x i1]* @lookup_table, i32 0, i32 %bit
   ret i1* %lookup
 }
 
 define i1 @c7(i32* %q, i32 %bitno) {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@c7
 ; IS__TUNIT____-SAME: (i32* nofree readonly [[Q:%.*]], i32 [[BITNO:%.*]]) [[ATTR2]] {
-; IS__TUNIT____-NEXT:    [[PTR:%.*]] = call i1* @lookup_bit(i32* noalias nofree readnone [[Q]], i32 [[BITNO]]) [[ATTR16:#.*]]
+; IS__TUNIT____-NEXT:    [[PTR:%.*]] = call i1* @lookup_bit(i32* noalias nofree readnone [[Q]], i32 [[BITNO]]) [[ATTR14:#.*]]
 ; IS__TUNIT____-NEXT:    [[VAL:%.*]] = load i1, i1* [[PTR]], align 1
 ; IS__TUNIT____-NEXT:    ret i1 [[VAL]]
 ;
 ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readonly willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@c7
 ; IS__CGSCC____-SAME: (i32* nofree readonly [[Q:%.*]], i32 [[BITNO:%.*]]) [[ATTR2]] {
 ; IS__CGSCC____-NEXT:    [[PTR:%.*]] = call i1* @lookup_bit(i32* noalias nofree readnone [[Q]], i32 [[BITNO]]) [[ATTR17:#.*]]
 ; IS__CGSCC____-NEXT:    [[VAL:%.*]] = load i1, i1* [[PTR]], align 1

 ; IS__TUNIT____-LABEL: define {{[^@]+}}@nc2
 ; IS__TUNIT____-SAME: (i32* nocapture nofree [[P:%.*]], i32* nofree [[Q:%.*]]) [[ATTR5]] {
 ; IS__TUNIT____-NEXT:    [[TMP1:%.*]] = call i32 @nc1(i32* nofree [[Q]], i32* nocapture nofree [[P]], i1 noundef false) [[ATTR5]]
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@nc2
 ; IS__CGSCC____-SAME: (i32* nocapture nofree [[P:%.*]], i32* nofree [[Q:%.*]]) [[ATTR5]] {
-; IS__CGSCC____-NEXT:    [[TMP1:%.*]] = call i32 @nc1(i32* nofree [[Q]], i32* nocapture nofree [[P]], i1 noundef false) [[ATTR10:#.*]]
+; IS__CGSCC____-NEXT:    [[TMP1:%.*]] = call i32 @nc1(i32* nofree [[Q]], i32* nocapture nofree [[P]], i1 noundef false) [[ATTR18:#.*]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   %1 = call i32 @nc1(i32* %q, i32* %p, i1 0)    ; <i32> [#uses=0]
   ret void
 }
 
 
 define void @nc3(void ()* %p) {
 ; CHECK-LABEL: define {{[^@]+}}@nc3
 ; CHECK-SAME: (void ()* nocapture nofree nonnull [[P:%.*]]) {
 ; CHECK-NEXT:    call void [[P]]()
 ; CHECK-NEXT:    ret void
 ;
   call void %p()
   ret void
 }
 
 ; The following test is tricky because improvements to AAIsDead can cause the call to be removed.
 ; FIXME: readonly and nocapture missing on the pointer.
 declare void @external(i8* readonly) nounwind argmemonly
 define void @nc4(i8* %p) {
-; CHECK: Function Attrs: argmemonly nounwind
-; CHECK-LABEL: define {{[^@]+}}@nc4
-; CHECK-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] {
-; CHECK-NEXT:    call void @external(i8* readonly [[P]]) [[ATTR13:#.*]]
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: argmemonly nounwind
+; IS__TUNIT____-LABEL: define {{[^@]+}}@nc4
+; IS__TUNIT____-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] {
+; IS__TUNIT____-NEXT:    call void @external(i8* readonly [[P]]) [[ATTR11:#.*]]
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nounwind
+; IS__CGSCC____-LABEL: define {{[^@]+}}@nc4
+; IS__CGSCC____-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] {
+; IS__CGSCC____-NEXT:    call void @external(i8* readonly [[P]]) [[ATTR13:#.*]]
+; IS__CGSCC____-NEXT:    ret void
 ;
   call void @external(i8* %p)
   ret void
 }
 
 define void @nc5(void (i8*)* %f, i8* %p) {
 ; CHECK-LABEL: define {{[^@]+}}@nc5
 ; CHECK-SAME: (void (i8*)* nocapture nofree nonnull [[F:%.*]], i8* nocapture [[P:%.*]]) {

 ;
 entry:
   %gep = getelementptr i32, i32* %x, i64 1
   store volatile i32 0, i32* %gep, align 4
   ret void
 }
 
 define void @nocaptureLaunder(i8* %p) {
-; CHECK: Function Attrs: nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@nocaptureLaunder
-; CHECK-SAME: (i8* nocapture [[P:%.*]]) [[ATTR10:#.*]] {
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P]]) [[ATTR17:#.*]]
-; CHECK-NEXT:    store i8 42, i8* [[B]], align 1
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@nocaptureLaunder
+; IS__TUNIT____-SAME: (i8* nocapture nofree [[P:%.*]]) [[ATTR5]] {
+; IS__TUNIT____-NEXT:  entry:
+; IS__TUNIT____-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR15:#.*]]
+; IS__TUNIT____-NEXT:    store i8 42, i8* [[B]], align 1
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@nocaptureLaunder
+; IS__CGSCC____-SAME: (i8* nocapture nofree [[P:%.*]]) [[ATTR10:#.*]] {
+; IS__CGSCC____-NEXT:  entry:
+; IS__CGSCC____-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR17]]
+; IS__CGSCC____-NEXT:    store i8 42, i8* [[B]], align 1
+; IS__CGSCC____-NEXT:    ret void
 ;
 entry:
   %b = call i8* @llvm.launder.invariant.group.p0i8(i8* %p)
   store i8 42, i8* %b
   ret void
 }
 
 @g2 = global i8* null
 define void @captureLaunder(i8* %p) {
-; CHECK: Function Attrs: nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@captureLaunder
-; CHECK-SAME: (i8* [[P:%.*]]) [[ATTR10]] {
-; CHECK-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P]]) [[ATTR17]]
-; CHECK-NEXT:    store i8* [[B]], i8** @g2, align 8
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@captureLaunder
+; IS__TUNIT____-SAME: (i8* nofree [[P:%.*]]) [[ATTR5]] {
+; IS__TUNIT____-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR15]]
+; IS__TUNIT____-NEXT:    store i8* [[B]], i8** @g2, align 8
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@captureLaunder
+; IS__CGSCC____-SAME: (i8* nofree [[P:%.*]]) [[ATTR10]] {
+; IS__CGSCC____-NEXT:    [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR17]]
+; IS__CGSCC____-NEXT:    store i8* [[B]], i8** @g2, align 8
+; IS__CGSCC____-NEXT:    ret void
 ;
   %b = call i8* @llvm.launder.invariant.group.p0i8(i8* %p)
   store i8* %b, i8** @g2
   ret void
 }
 
 define void @nocaptureStrip(i8* %p) {
-; CHECK: Function Attrs: nosync nounwind willreturn writeonly
-; CHECK-LABEL: define {{[^@]+}}@nocaptureStrip
-; CHECK-SAME: (i8* nocapture writeonly [[P:%.*]]) [[ATTR11:#.*]] {
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias readnone [[P]]) [[ATTR17]]
-; CHECK-NEXT:    store i8 42, i8* [[B]], align 1
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@nocaptureStrip
+; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[P:%.*]]) [[ATTR1]] {
+; IS__TUNIT____-NEXT:  entry:
+; IS__TUNIT____-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR15]]
+; IS__TUNIT____-NEXT:    store i8 42, i8* [[B]], align 1
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@nocaptureStrip
+; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[P:%.*]]) [[ATTR11:#.*]] {
+; IS__CGSCC____-NEXT:  entry:
+; IS__CGSCC____-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR17]]
+; IS__CGSCC____-NEXT:    store i8 42, i8* [[B]], align 1
+; IS__CGSCC____-NEXT:    ret void
 ;
 entry:
   %b = call i8* @llvm.strip.invariant.group.p0i8(i8* %p)
   store i8 42, i8* %b
   ret void
 }
 
 @g3 = global i8* null
 define void @captureStrip(i8* %p) {
-; CHECK: Function Attrs: nosync nounwind willreturn writeonly
-; CHECK-LABEL: define {{[^@]+}}@captureStrip
-; CHECK-SAME: (i8* writeonly [[P:%.*]]) [[ATTR11]] {
-; CHECK-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias readnone [[P]]) [[ATTR17]]
-; CHECK-NEXT:    store i8* [[B]], i8** @g3, align 8
-; CHECK-NEXT:    ret void
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@captureStrip
+; IS__TUNIT____-SAME: (i8* nofree writeonly [[P:%.*]]) [[ATTR1]] {
+; IS__TUNIT____-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR15]]
+; IS__TUNIT____-NEXT:    store i8* [[B]], i8** @g3, align 8
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@captureStrip
+; IS__CGSCC____-SAME: (i8* nofree writeonly [[P:%.*]]) [[ATTR11]] {
+; IS__CGSCC____-NEXT:    [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR17]]
+; IS__CGSCC____-NEXT:    store i8* [[B]], i8** @g3, align 8
+; IS__CGSCC____-NEXT:    ret void
 ;
   %b = call i8* @llvm.strip.invariant.group.p0i8(i8* %p)
   store i8* %b, i8** @g3
   ret void
 }
 
 define i1 @captureICmp(i32* %x) {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
;
   %1 = bitcast i32* %x to i8*
   %2 = icmp eq i8* %1, null
   ret i1 %2
 }
 
 define i1 @captureDereferenceableOrNullICmp(i32* dereferenceable_or_null(4) %x) null_pointer_is_valid {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind null_pointer_is_valid readnone willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@captureDereferenceableOrNullICmp
-; IS__TUNIT____-SAME: (i32* nofree readnone dereferenceable_or_null(4) [[X:%.*]]) [[ATTR12:#.*]] {
+; IS__TUNIT____-SAME: (i32* nofree readnone dereferenceable_or_null(4) [[X:%.*]]) [[ATTR10:#.*]] {
 ; IS__TUNIT____-NEXT:    [[TMP1:%.*]] = bitcast i32* [[X]] to i8*
 ; IS__TUNIT____-NEXT:    [[TMP2:%.*]] = icmp eq i8* [[TMP1]], null
 ; IS__TUNIT____-NEXT:    ret i1 [[TMP2]]
 ;
 ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@captureDereferenceableOrNullICmp
 ; IS__CGSCC____-SAME: (i32* nofree readnone dereferenceable_or_null(4) [[X:%.*]]) [[ATTR12:#.*]] {
 ; IS__CGSCC____-NEXT:    [[TMP1:%.*]] = bitcast i32* [[X]] to i8*

 declare i8* @maybe_returned_ptr(i8* readonly %ptr) readonly nounwind
 declare i8 @maybe_returned_val(i8* %ptr) readonly nounwind
 declare void @val_use(i8 %ptr) readonly nounwind
 
 ; FIXME: Both pointers should be nocapture
 define void @ptr_uses(i8* %ptr, i8* %wptr) {
 ; CHECK: Function Attrs: nounwind
 ; CHECK-LABEL: define {{[^@]+}}@ptr_uses
-; CHECK-SAME: (i8* [[PTR:%.*]], i8* nocapture nonnull writeonly dereferenceable(1) [[WPTR:%.*]]) [[ATTR13]] {
+; CHECK-SAME: (i8* [[PTR:%.*]], i8* nocapture nonnull writeonly dereferenceable(1) [[WPTR:%.*]]) [[ATTR13:#.*]] {
 ; CHECK-NEXT:    store i8 0, i8* [[WPTR]], align 1
 ; CHECK-NEXT:    ret void
 ;
   %call_ptr = call i8* @maybe_returned_ptr(i8* %ptr)
   %call_val = call i8 @maybe_returned_val(i8* %call_ptr)
   call void @val_use(i8 %call_val)
   store i8 0, i8* %wptr
   ret void
 }
 
 declare i8* @llvm.launder.invariant.group.p0i8(i8*)
 declare i8* @llvm.strip.invariant.group.p0i8(i8*)

llvm/test/Transforms/Attributor/nofree.ll

;
   tail call void @maybe_free()
   tail call void @nofree_function()
   ret void
 }
 
 
 ; TEST 10 (positive case)
 ; Call intrinsic function
-; CHECK: Function Attrs: nounwind readnone speculatable
+; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn
 ; CHECK-NEXT: declare float @llvm.floor.f32(float)
 declare float @llvm.floor.f32(float)
 
 define void @call_floor(float %a) #0 {
 ; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@call_floor
 ; IS__TUNIT____-SAME: (float [[A:%.*]]) [[ATTR3]] {
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@call_floor
 ; IS__CGSCC____-SAME: (float [[A:%.*]]) [[ATTR3]] {
 ; IS__CGSCC____-NEXT:    ret void
 ;
   tail call float @llvm.floor.f32(float %a)
   ret void
 }
 
-; FIXME: missing nofree
 define float @call_floor2(float %a) #0 {
-; CHECK: Function Attrs: noinline nosync nounwind readnone uwtable willreturn
-; CHECK-LABEL: define {{[^@]+}}@call_floor2
-; CHECK-SAME: (float [[A:%.*]]) [[ATTR7:#.*]] {
-; CHECK-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR11:#.*]]
-; CHECK-NEXT:    ret float [[C]]
+; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@call_floor2
+; IS__TUNIT____-SAME: (float [[A:%.*]]) [[ATTR3]] {
+; IS__TUNIT____-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR11:#.*]]
+; IS__TUNIT____-NEXT:    ret float [[C]]
+;
+; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@call_floor2
+; IS__CGSCC____-SAME: (float [[A:%.*]]) [[ATTR7:#.*]] {
+; IS__CGSCC____-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR12:#.*]]
+; IS__CGSCC____-NEXT:    ret float [[C]]
 ;
   %c = tail call float @llvm.floor.f32(float %a)
   ret float %c
 }
 
 ; TEST 11 (positive case)
 ; Check propagation.
 

 
 define void @nonnull_assume_pos(i8* %arg1, i8* %arg2, i8* %arg3, i8* %arg4) {
 ; ATTRIBUTOR-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; ATTRIBUTOR-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]])
 ; ATTRIBUTOR-NEXT:    call void @llvm.assume(i1 true) #11 [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
 ; ATTRIBUTOR-NEXT:    call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]])
 ; ATTRIBUTOR-NEXT:    ret void
 ;
-; CHECK-LABEL: define {{[^@]+}}@nonnull_assume_pos
-; CHECK-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
-; CHECK-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
-; CHECK-NEXT:    call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]])
-; CHECK-NEXT:    ret void
+; IS__TUNIT____-LABEL: define {{[^@]+}}@nonnull_assume_pos
+; IS__TUNIT____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
+; IS__TUNIT____-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
+; IS__TUNIT____-NEXT:    call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]])
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____-LABEL: define {{[^@]+}}@nonnull_assume_pos
+; IS__CGSCC____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) {
+; IS__CGSCC____-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
+; IS__CGSCC____-NEXT:    call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]])
+; IS__CGSCC____-NEXT:    ret void
 ;
   call void @llvm.assume(i1 true) ["nofree"(i8* %arg1), "nofree"(i8* %arg3)]
   call void @unknown(i8* %arg1, i8* %arg2, i8* %arg3, i8* %arg4)
   ret void
 }
 define void @nonnull_assume_neg(i8* %arg1, i8* %arg2, i8* %arg3, i8* %arg4) {
 ; ATTRIBUTOR-LABEL: define {{[^@]+}}@nonnull_assume_neg
 ; ATTRIBUTOR-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]])

llvm/test/Transforms/Attributor/nonnull.ll

 ; IS__CGSCC____-SAME: (i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[P:%.*]]) [[ATTR1:#.*]] {
 ; IS__CGSCC____-NEXT:    ret i8* [[P]]
 ;
   ret i8* %p
 }
 
 define i8* @test2A(i1 %c, i8* %ret) {
 ; ATTRIBUTOR: define nonnull i8* @test2A(i1 %c, i8* nofree nonnull readnone returned %ret)
-; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test2A
 ; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0:#.*]] {
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[C]], label [[A:%.*]], label [[B:%.*]]
 ; NOT_CGSCC_OPM:       A:
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11:#.*]] [ "nonnull"(i8* [[RET]]) ]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12:#.*]] [ "nonnull"(i8* [[RET]]) ]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ; NOT_CGSCC_OPM:       B:
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nonnull"(i8* [[RET]]) ]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[RET]]) ]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ;
-; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test2A
 ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0:#.*]] {
 ; IS__CGSCC_OPM-NEXT:    br i1 [[C]], label [[A:%.*]], label [[B:%.*]]
 ; IS__CGSCC_OPM:       A:
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12:#.*]] [ "nonnull"(i8* [[RET]]) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13:#.*]] [ "nonnull"(i8* [[RET]]) ]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ; IS__CGSCC_OPM:       B:
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[RET]]) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "nonnull"(i8* [[RET]]) ]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ;
   br i1 %c, label %A, label %B
 A:
   call void @llvm.assume(i1 true) [ "nonnull"(i8* %ret) ]
   ret i8* %ret
 B:
   call void @llvm.assume(i1 true) [ "nonnull"(i8* %ret) ]
   ret i8* %ret
 }
 
 define i8* @test2B(i1 %c, i8* %ret) {
 ; ATTRIBUTOR: define nonnull dereferenceable(4) i8* @test2B(i1 %c, i8* nofree nonnull readnone returned dereferenceable(4) %ret)
-; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test2B
 ; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0]] {
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[C]], label [[A:%.*]], label [[B:%.*]]
 ; NOT_CGSCC_OPM:       A:
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ; NOT_CGSCC_OPM:       B:
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ;
-; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test2B
 ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0]] {
 ; IS__CGSCC_OPM-NEXT:    br i1 [[C]], label [[A:%.*]], label [[B:%.*]]
 ; IS__CGSCC_OPM:       A:
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ; IS__CGSCC_OPM:       B:
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "dereferenceable"(i8* [[RET]], i32 4) ]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[RET]]
 ;
   br i1 %c, label %A, label %B
 A:
   call void @llvm.assume(i1 true) [ "dereferenceable"(i8* %ret, i32 4) ]
   ret i8* %ret
 B:
   call void @llvm.assume(i1 true) [ "dereferenceable"(i8* %ret, i32 4) ]

 ;
   %b = getelementptr inbounds i8, i8* %a, i64 %n
   ret i8* %b
 }
 
 ; ATTRIBUTOR_OPM: define i8* @test10
 ; ATTRIBUTOR_NPM: define nonnull i8* @test10
 define i8* @test10(i8* %a, i64 %n) {
-; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test10
 ; NOT_CGSCC_OPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) [[ATTR0]] {
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]]
 ; NOT_CGSCC_OPM-NEXT:    [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[B]]
 ;
-; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test10
 ; IS__CGSCC_OPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) [[ATTR0]] {
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13]]
 ; IS__CGSCC_OPM-NEXT:    [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[B]]
 ;
   %cmp = icmp ne i64 %n, 0
   call void @llvm.assume(i1 %cmp)
   %b = getelementptr inbounds i8, i8* %a, i64 %n
   ret i8* %b
 }

 ; NOT_CGSCC_OPM-NEXT:    [[TMP:%.*]] = icmp eq i32* [[ARG]], null
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP]], label [[BB9:%.*]], label [[BB1:%.*]]
 ; NOT_CGSCC_OPM:       bb1:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARG]], align 4
 ; NOT_CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]]
 ; NOT_CGSCC_OPM:       bb4:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1
-; NOT_CGSCC_OPM-NEXT:    [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR12:#.*]]
+; NOT_CGSCC_OPM-NEXT:    [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR13:#.*]]
 ; NOT_CGSCC_OPM-NEXT:    [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1
 ; NOT_CGSCC_OPM-NEXT:    br label [[BB9]]
 ; NOT_CGSCC_OPM:       bb6:
-; NOT_CGSCC_OPM-NEXT:    [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR12]]
+; NOT_CGSCC_OPM-NEXT:    [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]]
 ; NOT_CGSCC_OPM-NEXT:    ret i32* [[TMP7]]
 ; NOT_CGSCC_OPM:       bb9:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ]
 ; NOT_CGSCC_OPM-NEXT:    ret i32* [[TMP10]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f1
 ; IS__CGSCC_OPM-SAME: (i32* nofree readonly [[ARG:%.*]]) [[ATTR6:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
 ; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = icmp eq i32* [[ARG]], null
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TMP]], label [[BB9:%.*]], label [[BB1:%.*]]
 ; IS__CGSCC_OPM:       bb1:
 ; IS__CGSCC_OPM-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARG]], align 4
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]]
 ; IS__CGSCC_OPM:       bb4:
 ; IS__CGSCC_OPM-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1
-; IS__CGSCC_OPM-NEXT:    [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR13:#.*]]
+; IS__CGSCC_OPM-NEXT:    [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR14:#.*]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1
 ; IS__CGSCC_OPM-NEXT:    br label [[BB9]]
 ; IS__CGSCC_OPM:       bb6:
-; IS__CGSCC_OPM-NEXT:    [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]]
+; IS__CGSCC_OPM-NEXT:    [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR14]]
 ; IS__CGSCC_OPM-NEXT:    ret i32* [[TMP7]]
 ; IS__CGSCC_OPM:       bb9:
 ; IS__CGSCC_OPM-NEXT:    [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ]
 ; IS__CGSCC_OPM-NEXT:    ret i32* [[TMP10]]
 ;
 
 bb:
   %tmp = icmp eq i32* %arg, null
bb9:                                              ; preds = %bb4, %bb
   ret i32* %tmp10
 }
 
 define internal i32* @f2(i32* %arg) {
 ; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f2
 ; NOT_CGSCC_OPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR5]] {
 ; NOT_CGSCC_OPM-NEXT:  bb:
-; NOT_CGSCC_OPM-NEXT:    [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR12]]
+; NOT_CGSCC_OPM-NEXT:    [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]]
 ; NOT_CGSCC_OPM-NEXT:    ret i32* [[TMP]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2
 ; IS__CGSCC_OPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR6]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
-; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]]
+; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR14]]
 ; IS__CGSCC_OPM-NEXT:    ret i32* [[TMP]]
 ;
 bb:
   %tmp = tail call i32* @f1(i32* %arg)
   ret i32* %tmp
 }
 
 define dso_local noalias i32* @f3(i32* %arg) {
 ; FIXME: missing nonnull. It should be nonnull @f3(i32* nonnull readonly %arg)
 ; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f3
 ; NOT_CGSCC_OPM-SAME: (i32* nofree readonly [[ARG:%.*]]) [[ATTR5]] {
 ; NOT_CGSCC_OPM-NEXT:  bb:
-; NOT_CGSCC_OPM-NEXT:    [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR12]]
+; NOT_CGSCC_OPM-NEXT:    [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR13]]
 ; NOT_CGSCC_OPM-NEXT:    ret i32* [[TMP]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3
 ; IS__CGSCC_OPM-SAME: (i32* nofree readonly [[ARG:%.*]]) [[ATTR6]] {
 ; IS__CGSCC_OPM-NEXT:  bb:
-; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR13]]
+; IS__CGSCC_OPM-NEXT:    [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR14]]
 ; IS__CGSCC_OPM-NEXT:    ret i32* [[TMP]]
 ;
 bb:
 ; FIXME: missing nonnull. It should be @f1(i32* nonnull readonly %arg)
   %tmp = call i32* @f1(i32* %arg)
   ret i32* %tmp
 }
 

 declare void @fun3(i8*, i8*, i8*) #1
 ; TEST 16 simple path test
 ; if(..)
 ;   fun2(nonnull %a, nonnull %b)
 ; else
 ;   fun2(nonnull %a, %b)
 ; We can say that %a is nonnull but %b is not.
 define void @f16(i8* %a, i8 * %b, i8 %c) {
-; CHECK: Function Attrs: nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@f16
-; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR0:#.*]] {
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
-; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR0]]
-; CHECK-NEXT:    ret void
-; CHECK:       if.else:
-; CHECK-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR0]]
-; CHECK-NEXT:    ret void
+; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f16
+; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR6:#.*]] {
+; NOT_CGSCC_OPM-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
+; NOT_CGSCC_OPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; NOT_CGSCC_OPM:       if.then:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    ret void
+; NOT_CGSCC_OPM:       if.else:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    ret void
+;
+; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f16
+; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR7:#.*]] {
+; IS__CGSCC_OPM-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
+; IS__CGSCC_OPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; IS__CGSCC_OPM:       if.then:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    ret void
+; IS__CGSCC_OPM:       if.else:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    ret void
 ;
   %cmp = icmp eq i8 %c, 0
   br i1 %cmp, label %if.then, label %if.else
 if.then:
   tail call void @fun2(i8* nonnull %a, i8* nonnull %b)
   ret void
 if.else:
   tail call void @fun2(i8* nonnull %a, i8* %b)
   ret void
 }
 ; TEST 17 explore child BB test
 ; if(..)
 ;    ... (willreturn & nounwind)
 ; else
 ;    ... (willreturn & nounwind)
 ; fun1(nonnull %a)
 ; We can say that %a is nonnull
 define void @f17(i8* %a, i8 %c) {
-; CHECK: Function Attrs: nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@f17
-; CHECK-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR0]] {
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
-; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @fun0() [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT:%.*]]
-; CHECK:       if.else:
-; CHECK-NEXT:    tail call void @fun0() [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT]]
-; CHECK:       cont:
-; CHECK-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR0]]
-; CHECK-NEXT:    ret void
+; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f17
+; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR6]] {
+; NOT_CGSCC_OPM-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
+; NOT_CGSCC_OPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; NOT_CGSCC_OPM:       if.then:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT:%.*]]
+; NOT_CGSCC_OPM:       if.else:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT]]
+; NOT_CGSCC_OPM:       cont:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    ret void
+;
+; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f17
+; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR7]] {
+; IS__CGSCC_OPM-NEXT:    [[CMP:%.*]] = icmp eq i8 [[C]], 0
+; IS__CGSCC_OPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; IS__CGSCC_OPM:       if.then:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT:%.*]]
+; IS__CGSCC_OPM:       if.else:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT]]
+; IS__CGSCC_OPM:       cont:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    ret void
 ;
   %cmp = icmp eq i8 %c, 0
   br i1 %cmp, label %if.then, label %if.else
 if.then:
   tail call void @fun0()
   br label %cont
 if.else:
   tail call void @fun0()

 ;    ... (willreturn & nounwind)
 ; if(..)
 ;    ... (willreturn & nounwind)
 ; else
 ;    ... (willreturn & nounwind)
 ; fun1(nonnull %a)
 
 define void @f18(i8* %a, i8* %b, i8 %c) {
-; CHECK: Function Attrs: nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@f18
-; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR0]] {
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i8 [[C]], 0
-; CHECK-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    tail call void @fun0() [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT:%.*]]
-; CHECK:       if.else:
-; CHECK-NEXT:    tail call void @fun0() [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT]]
-; CHECK:       cont:
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i8 [[C]], 1
-; CHECK-NEXT:    br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]]
-; CHECK:       cont.then:
-; CHECK-NEXT:    tail call void @fun1(i8* nonnull [[B]]) [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT2:%.*]]
-; CHECK:       cont.else:
-; CHECK-NEXT:    tail call void @fun0() [[ATTR0]]
-; CHECK-NEXT:    br label [[CONT2]]
-; CHECK:       cont2:
-; CHECK-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR0]]
-; CHECK-NEXT:    ret void
+; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
+; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f18
+; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR6]] {
+; NOT_CGSCC_OPM-NEXT:    [[CMP1:%.*]] = icmp eq i8 [[C]], 0
+; NOT_CGSCC_OPM-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; NOT_CGSCC_OPM:       if.then:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT:%.*]]
+; NOT_CGSCC_OPM:       if.else:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT]]
+; NOT_CGSCC_OPM:       cont:
+; NOT_CGSCC_OPM-NEXT:    [[CMP2:%.*]] = icmp eq i8 [[C]], 1
+; NOT_CGSCC_OPM-NEXT:    br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]]
+; NOT_CGSCC_OPM:       cont.then:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[B]]) [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT2:%.*]]
+; NOT_CGSCC_OPM:       cont.else:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    br label [[CONT2]]
+; NOT_CGSCC_OPM:       cont2:
+; NOT_CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR6]]
+; NOT_CGSCC_OPM-NEXT:    ret void
+;
+; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
+; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f18
+; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR7]] {
+; IS__CGSCC_OPM-NEXT:    [[CMP1:%.*]] = icmp eq i8 [[C]], 0
+; IS__CGSCC_OPM-NEXT:    br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; IS__CGSCC_OPM:       if.then:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT:%.*]]
+; IS__CGSCC_OPM:       if.else:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT]]
+; IS__CGSCC_OPM:       cont:
+; IS__CGSCC_OPM-NEXT:    [[CMP2:%.*]] = icmp eq i8 [[C]], 1
+; IS__CGSCC_OPM-NEXT:    br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]]
+; IS__CGSCC_OPM:       cont.then:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[B]]) [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT2:%.*]]
+; IS__CGSCC_OPM:       cont.else:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun0() [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    br label [[CONT2]]
+; IS__CGSCC_OPM:       cont2:
+; IS__CGSCC_OPM-NEXT:    tail call void @fun1(i8* nonnull [[A]]) [[ATTR7]]
+; IS__CGSCC_OPM-NEXT:    ret void
 ;
   %cmp1 = icmp eq i8 %c, 0
   br i1 %cmp1, label %if.then, label %if.else
 if.then:
   tail call void @fun0()
   br label %cont
 if.else:
   tail call void @fun0()
;
   ret i8 %c
 }
 
 ; The nonnull callsite is guaranteed to execute, so the argument must be nonnull throughout the parent.
 
 define i8 @parent7(i8* %a) {
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@parent7
 ; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]]) {
-; NOT_CGSCC_OPM-NEXT:    [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR13:#.*]]
+; NOT_CGSCC_OPM-NEXT:    [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR14:#.*]]
 ; NOT_CGSCC_OPM-NEXT:    call void @use1nonnull(i8* nonnull [[A]])
 ; NOT_CGSCC_OPM-NEXT:    ret i8 [[RET]]
 ;
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@parent7
 ; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]]) {
-; IS__CGSCC_OPM-NEXT:    [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR14:#.*]]
+; IS__CGSCC_OPM-NEXT:    [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR15:#.*]]
 ; IS__CGSCC_OPM-NEXT:    call void @use1nonnull(i8* nonnull [[A]])
 ; IS__CGSCC_OPM-NEXT:    ret i8 [[RET]]
 ;
 
 
   %ret = call i8 @use1safecall(i8* %a)
   call void @use1nonnull(i8* %a)
   ret i8 %ret
;
   %q = getelementptr inbounds i32, i32* %p, i32 1
   ret i32* %q
 }
 
 define i32* @gep1_no_null_opt(i32* %p) #0 {
 ; Should't be able to derive nonnull based on gep.
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind null_pointer_is_valid readnone willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@gep1_no_null_opt
-; IS__TUNIT____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR7:#.*]] {
+; IS__TUNIT____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR8:#.*]] {
 ; IS__TUNIT____-NEXT:    [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1
 ; IS__TUNIT____-NEXT:    ret i32* [[Q]]
 ;
 ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@gep1_no_null_opt
-; IS__CGSCC____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR7:#.*]] {
+; IS__CGSCC____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR8:#.*]] {
 ; IS__CGSCC____-NEXT:    [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1
 ; IS__CGSCC____-NEXT:    ret i32* [[Q]]
 ;
   %q = getelementptr inbounds i32, i32* %p, i32 1
   ret i32* %q
 }
 
 define i32 addrspace(3)* @gep2(i32 addrspace(3)* %p) {

 ;
   call void @use_i32_ptr(i32* %a)
   ret void
 }
 ; Avoid nonnull as we do not touch naked functions
 define internal void @naked(i32* dereferenceable(4) %a) naked {
 ; CHECK: Function Attrs: naked
 ; CHECK-LABEL: define {{[^@]+}}@naked
-; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR8:#.*]] {
+; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR9:#.*]] {
 ; CHECK-NEXT:    call void @use_i32_ptr(i32* [[A]])
 ; CHECK-NEXT:    ret void
 ;
   call void @use_i32_ptr(i32* %a)
   ret void
 }
 ; Avoid nonnull as we do not touch optnone
 define internal void @optnone(i32* dereferenceable(4) %a) optnone noinline {
 ; CHECK: Function Attrs: noinline optnone
 ; CHECK-LABEL: define {{[^@]+}}@optnone
-; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR9:#.*]] {
+; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR10:#.*]] {
 ; CHECK-NEXT:    call void @use_i32_ptr(i32* [[A]])
 ; CHECK-NEXT:    ret void
 ;
   call void @use_i32_ptr(i32* %a)
   ret void
 }
 define void @make_live(i32* nonnull dereferenceable(8) %a) {
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@make_live

 ; IS__TUNIT_OPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ]
 ; IS__TUNIT_OPM-NEXT:    tail call void @h(i32* [[A]]) [[ATTR4]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; IS__TUNIT_OPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS________NPM: Function Attrs: nounwind willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1
-; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR0:#.*]] {
+; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR6:#.*]] {
 ; IS________NPM-NEXT:  en:
 ; IS________NPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; IS________NPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; IS________NPM:       ex:
-; IS________NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR0]]
+; IS________NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR6]]
 ; IS________NPM-NEXT:    ret i32 [[TMP5]]
 ; IS________NPM:       hd:
 ; IS________NPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ]
-; IS________NPM-NEXT:    tail call void @h(i32* [[A]]) [[ATTR0]]
+; IS________NPM-NEXT:    tail call void @h(i32* [[A]]) [[ATTR6]]
 ; IS________NPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; IS________NPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; IS________NPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nounwind
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1
 ; IS__CGSCC_OPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR5]] {
 ; IS__CGSCC_OPM-NEXT:  en:

 ; IS__TUNIT_OPM-NEXT:    br label [[HD2]]
 ; IS__TUNIT_OPM:       hd2:
 ; IS__TUNIT_OPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; IS__TUNIT_OPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS________NPM: Function Attrs: nounwind willreturn
 ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b
-; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] {
+; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] {
 ; IS________NPM-NEXT:  en:
 ; IS________NPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; IS________NPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; IS________NPM:       ex:
-; IS________NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR0]]
+; IS________NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR6]]
 ; IS________NPM-NEXT:    ret i32 [[TMP5]]
 ; IS________NPM:       hd:
 ; IS________NPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ]
-; IS________NPM-NEXT:    tail call void @h(i32* [[A]]) [[ATTR0]]
+; IS________NPM-NEXT:    tail call void @h(i32* [[A]]) [[ATTR6]]
 ; IS________NPM-NEXT:    br label [[HD2]]
 ; IS________NPM:       hd2:
 ; IS________NPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; IS________NPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; IS________NPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nounwind
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b
hd2:
   %tmp9 = icmp eq i32 %tmp8, %b
   br i1 %tmp9, label %ex, label %hd
 }
 
 define i32 @nonnull_exec_ctx_2(i32* %a, i32 %b) willreturn nounwind {
 ;
 ; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2
-; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] {
+; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] {
 ; NOT_CGSCC_OPM-NEXT:  en:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; NOT_CGSCC_OPM:       ex:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR4]]
 ; NOT_CGSCC_OPM-NEXT:    ret i32 [[TMP5]]
 ; NOT_CGSCC_OPM:       hd:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ]
 ; NOT_CGSCC_OPM-NEXT:    tail call void @h(i32* nonnull [[A]]) [[ATTR4]]
 ; NOT_CGSCC_OPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; NOT_CGSCC_OPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2
-; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] {
+; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR7]] {
 ; IS__CGSCC_OPM-NEXT:  en:
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; IS__CGSCC_OPM:       ex:
 ; IS__CGSCC_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR5]]
 ; IS__CGSCC_OPM-NEXT:    ret i32 [[TMP5]]
 ; IS__CGSCC_OPM:       hd:
 ; IS__CGSCC_OPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ]
hd:
   %tmp9 = icmp eq i32 %tmp8, %b
   br i1 %tmp9, label %ex, label %hd
 }
 
 define i32 @nonnull_exec_ctx_2b(i32* %a, i32 %b) willreturn nounwind {
 ;
 ; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b
-; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] {
+; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] {
 ; NOT_CGSCC_OPM-NEXT:  en:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; NOT_CGSCC_OPM:       ex:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR4]]
 ; NOT_CGSCC_OPM-NEXT:    ret i32 [[TMP5]]
 ; NOT_CGSCC_OPM:       hd:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ]
 ; NOT_CGSCC_OPM-NEXT:    tail call void @h(i32* nonnull [[A]]) [[ATTR4]]
 ; NOT_CGSCC_OPM-NEXT:    br label [[HD2]]
 ; NOT_CGSCC_OPM:       hd2:
 ; NOT_CGSCC_OPM-NEXT:    [[TMP8]] = add nuw i32 [[TMP7]], 1
 ; NOT_CGSCC_OPM-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]]
 ; NOT_CGSCC_OPM-NEXT:    br i1 [[TMP9]], label [[EX]], label [[HD]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b
-; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] {
+; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR7]] {
 ; IS__CGSCC_OPM-NEXT:  en:
 ; IS__CGSCC_OPM-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[B]], 0
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]]
 ; IS__CGSCC_OPM:       ex:
 ; IS__CGSCC_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR5]]
 ; IS__CGSCC_OPM-NEXT:    ret i32 [[TMP5]]
 ; IS__CGSCC_OPM:       hd:
 ; IS__CGSCC_OPM-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ]

 }
 
 declare i8* @strrchr(i8* %0, i32 %1) nofree nounwind readonly
 
 ; We should not mark the return of @strrchr as `nonnull`, it may well be NULL!
 define i8* @mybasename(i8* nofree readonly %str) {
 ; NOT_CGSCC_OPM: Function Attrs: nofree nounwind readonly
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@mybasename
-; NOT_CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR10:#.*]] {
-; NOT_CGSCC_OPM-NEXT:    [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR13]]
+; NOT_CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR11:#.*]] {
+; NOT_CGSCC_OPM-NEXT:    [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR14]]
 ; NOT_CGSCC_OPM-NEXT:    [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null
 ; NOT_CGSCC_OPM-NEXT:    [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1
 ; NOT_CGSCC_OPM-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]]
 ; NOT_CGSCC_OPM-NEXT:    ret i8* [[COND]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree nounwind readonly
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@mybasename
-; IS__CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR11:#.*]] {
-; IS__CGSCC_OPM-NEXT:    [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR14]]
+; IS__CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR12:#.*]] {
+; IS__CGSCC_OPM-NEXT:    [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR15]]
 ; IS__CGSCC_OPM-NEXT:    [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null
 ; IS__CGSCC_OPM-NEXT:    [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1
 ; IS__CGSCC_OPM-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]]
 ; IS__CGSCC_OPM-NEXT:    ret i8* [[COND]]
 ;
   %call = call i8* @strrchr(i8* %str, i32 47)
   %tobool = icmp ne i8* %call, null
   %add.ptr = getelementptr inbounds i8, i8* %call, i64 1
   %cond = select i1 %tobool, i8* %add.ptr, i8* %str
   ret i8* %cond
 }
 
 define void @nonnull_assume_pos(i8* %arg) {
 ; ATTRIBUTOR-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; ATTRIBUTOR-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]])
 ; ATTRIBUTOR-NEXT:    call void @llvm.assume(i1 true) #11 [ "nonnull"(i8* [[ARG]]) ]
 ; ATTRIBUTOR-NEXT:    call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]])
 ; ATTRIBUTOR-NEXT:    [[TMP1:%.*]] = call i8* @unknown()
 ; ATTRIBUTOR-NEXT:    ret void
 ;
 ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; NOT_CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) {
-; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nonnull"(i8* [[ARG]]) ]
+; NOT_CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[ARG]]) ]
 ; NOT_CGSCC_OPM-NEXT:    call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) [[ATTR4]]
 ; NOT_CGSCC_OPM-NEXT:    [[TMP1:%.*]] = call i8* @unknown()
 ; NOT_CGSCC_OPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos
 ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) {
-; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[ARG]]) ]
+; IS__CGSCC_OPM-NEXT:    call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "nonnull"(i8* [[ARG]]) ]
 ; IS__CGSCC_OPM-NEXT:    call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) [[ATTR5]]
 ; IS__CGSCC_OPM-NEXT:    [[TMP1:%.*]] = call i8* @unknown()
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
   call void @llvm.assume(i1 true) ["nonnull"(i8* %arg)]
   call void @use_i8_ptr(i8* %arg)
   call i8* @unknown()
   ret void

llvm/test/Transforms/Attributor/norecurse.ll

;
   ret i32 %a
 }
 
 ; CHECK: Function Attrs
 ; CHECK-NEXT: declare i32 @k()
 declare i32 @k() readnone
 
 define void @intrinsic(i8* %dest, i8* %src, i32 %len) {
-; NOT_CGSCC_NPM: Function Attrs: argmemonly nosync nounwind willreturn
+; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn
 ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@intrinsic
-; NOT_CGSCC_NPM-SAME: (i8* nocapture writeonly [[DEST:%.*]], i8* nocapture readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR5:#.*]] {
-; NOT_CGSCC_NPM-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[DEST]], i8* noalias nocapture readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR11:#.*]]
+; NOT_CGSCC_NPM-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR5:#.*]] {
+; NOT_CGSCC_NPM-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR10:#.*]]
 ; NOT_CGSCC_NPM-NEXT:    ret void
 ;
-; IS__CGSCC_NPM: Function Attrs: argmemonly nosync nounwind willreturn
+; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@intrinsic
-; IS__CGSCC_NPM-SAME: (i8* nocapture writeonly [[DEST:%.*]], i8* nocapture readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR4:#.*]] {
-; IS__CGSCC_NPM-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[DEST]], i8* noalias nocapture readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR8:#.*]]
+; IS__CGSCC_NPM-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC_NPM-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR7:#.*]]
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false)
   ret void
 }
 
 ; CHECK: Function Attrs
 ; CHECK-NEXT: declare void @llvm.memcpy.p0i8.p0i8.i32
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1)
 
 define internal i32 @called_by_norecurse() {
 ; IS__TUNIT____: Function Attrs: nosync readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@called_by_norecurse
 ; IS__TUNIT____-SAME: () [[ATTR3:#.*]] {
 ; IS__TUNIT____-NEXT:    [[A:%.*]] = call i32 @k()
 ; IS__TUNIT____-NEXT:    ret i32 undef
 ;
 ; IS__CGSCC____: Function Attrs: norecurse nosync readnone
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@called_by_norecurse
-; IS__CGSCC____-SAME: () [[ATTR6:#.*]] {
+; IS__CGSCC____-SAME: () [[ATTR5:#.*]] {
 ; IS__CGSCC____-NEXT:    [[A:%.*]] = call i32 @k()
 ; IS__CGSCC____-NEXT:    ret i32 undef
 ;
   %a = call i32 @k()
   ret i32 %a
 }
 define void @m() norecurse {
 ; IS__TUNIT____: Function Attrs: norecurse nosync readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@m
-; IS__TUNIT____-SAME: () [[ATTR7:#.*]] {
+; IS__TUNIT____-SAME: () [[ATTR6:#.*]] {
 ; IS__TUNIT____-NEXT:    [[A:%.*]] = call i32 @called_by_norecurse() [[ATTR3]]
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: norecurse nosync readnone
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@m
-; IS__CGSCC____-SAME: () [[ATTR6]] {
+; IS__CGSCC____-SAME: () [[ATTR5]] {
 ; IS__CGSCC____-NEXT:    [[A:%.*]] = call i32 @called_by_norecurse()
 ; IS__CGSCC____-NEXT:    ret void
 ;
   %a = call i32 @called_by_norecurse()
   ret void
 }
 
 define internal i32 @called_by_norecurse_indirectly() {

 ; IS__TUNIT____: Function Attrs: nosync readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@o
 ; IS__TUNIT____-SAME: () [[ATTR3]] {
 ; IS__TUNIT____-NEXT:    [[A:%.*]] = call i32 @called_by_norecurse_indirectly() [[ATTR3]]
 ; IS__TUNIT____-NEXT:    ret i32 [[A]]
 ;
 ; IS__CGSCC____: Function Attrs: norecurse nosync readnone
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@o
-; IS__CGSCC____-SAME: () [[ATTR6]] {
+; IS__CGSCC____-SAME: () [[ATTR5]] {
 ; IS__CGSCC____-NEXT:    [[A:%.*]] = call i32 @called_by_norecurse_indirectly()
 ; IS__CGSCC____-NEXT:    ret i32 [[A]]
 ;
   %a = call i32 @called_by_norecurse_indirectly()
   ret i32 %a
 }
 define i32 @p() norecurse {
 ; IS__TUNIT____: Function Attrs: norecurse nosync readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@p
-; IS__TUNIT____-SAME: () [[ATTR7]] {
+; IS__TUNIT____-SAME: () [[ATTR6]] {
 ; IS__TUNIT____-NEXT:    [[A:%.*]] = call i32 @o() [[ATTR3]]
 ; IS__TUNIT____-NEXT:    ret i32 [[A]]
 ;
 ; IS__CGSCC____: Function Attrs: norecurse nosync readnone
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@p
-; IS__CGSCC____-SAME: () [[ATTR6]] {
+; IS__CGSCC____-SAME: () [[ATTR5]] {
 ; IS__CGSCC____-NEXT:    [[A:%.*]] = call i32 @o()
 ; IS__CGSCC____-NEXT:    ret i32 [[A]]
 ;
   %a = call i32 @o()
   ret i32 %a
 }
 
 define void @f(i32 %x)  {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@f
-; IS__TUNIT____-SAME: (i32 [[X:%.*]]) [[ATTR8:#.*]] {
+; IS__TUNIT____-SAME: (i32 [[X:%.*]]) [[ATTR7:#.*]] {
 ; IS__TUNIT____-NEXT:  entry:
 ; IS__TUNIT____-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
 ; IS__TUNIT____-NEXT:    store i32 [[X]], i32* [[X_ADDR]], align 4
 ; IS__TUNIT____-NEXT:    [[TMP0:%.*]] = load i32, i32* [[X_ADDR]], align 4
 ; IS__TUNIT____-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 ; IS__TUNIT____-NEXT:    br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; IS__TUNIT____:       if.then:
-; IS__TUNIT____-NEXT:    call void @g() [[ATTR9:#.*]]
+; IS__TUNIT____-NEXT:    call void @g() [[ATTR8:#.*]]
 ; IS__TUNIT____-NEXT:    br label [[IF_END]]
 ; IS__TUNIT____:       if.end:
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind readnone
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f
-; IS__CGSCC_OPM-SAME: (i32 [[X:%.*]]) [[ATTR8:#.*]] {
+; IS__CGSCC_OPM-SAME: (i32 [[X:%.*]]) [[ATTR7:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  entry:
 ; IS__CGSCC_OPM-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
 ; IS__CGSCC_OPM-NEXT:    store i32 [[X]], i32* [[X_ADDR]], align 4
 ; IS__CGSCC_OPM-NEXT:    [[TMP0:%.*]] = load i32, i32* [[X_ADDR]], align 4
 ; IS__CGSCC_OPM-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 ; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 ; IS__CGSCC_OPM:       if.then:
 ; IS__CGSCC_OPM-NEXT:    br label [[IF_END]]

 
 if.end:
   ret void
 }
 
 define void @g() norecurse {
 ; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@g
-; IS__TUNIT____-SAME: () [[ATTR9]] {
+; IS__TUNIT____-SAME: () [[ATTR8]] {
 ; IS__TUNIT____-NEXT:  entry:
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@g
-; IS__CGSCC_OPM-SAME: () [[ATTR9:#.*]] {
+; IS__CGSCC_OPM-SAME: () [[ATTR8:#.*]] {
 ; IS__CGSCC_OPM-NEXT:  entry:
-; IS__CGSCC_OPM-NEXT:    call void @f(i32 noundef 0) [[ATTR8]]
+; IS__CGSCC_OPM-NEXT:    call void @f(i32 noundef 0) [[ATTR7]]
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
 ; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@g
 ; IS__CGSCC_NPM-SAME: () [[ATTR0]] {
 ; IS__CGSCC_NPM-NEXT:  entry:
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;

 ;
   %3 = tail call i32 %0(i32 %1) #2
   ret i32 %3
 }
 
 define i32 @eval_func2(i32 (i32)* , i32) local_unnamed_addr null_pointer_is_valid{
 ; CHECK: Function Attrs: null_pointer_is_valid
 ; CHECK-LABEL: define {{[^@]+}}@eval_func2
-; CHECK-SAME: (i32 (i32)* nocapture nofree [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr [[ATTR7:#.*]] {
+; CHECK-SAME: (i32 (i32)* nocapture nofree [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr [[ATTR6:#.*]] {
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 [[TMP0]](i32 [[TMP1]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %3 = tail call i32 %0(i32 %1) #2
   ret i32 %3
 }
 
 ; Call an unknown function in a dead block.

llvm/test/Transforms/Attributor/nosync.ll

 declare void @llvm.memcpy(i8* %dest, i8* %src, i32 %len, i1 %isvolatile)
 declare void @llvm.memset(i8* %dest, i8 %val, i32 %len, i1 %isvolatile)
 
 ; TEST 14 - negative, checking volatile intrinsics.
 
 ; It is odd to add nocapture but a result of the llvm.memcpy nocapture.
 ;
 define i32 @memcpy_volatile(i8* %ptr1, i8* %ptr2) {
-; CHECK: Function Attrs: argmemonly nounwind willreturn
-; CHECK-LABEL: define {{[^@]+}}@memcpy_volatile
-; CHECK-SAME: (i8* nocapture writeonly [[PTR1:%.*]], i8* nocapture readonly [[PTR2:%.*]]) [[ATTR10:#.*]] {
-; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[PTR1]], i8* noalias nocapture readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR19:#.*]]
-; CHECK-NEXT:    ret i32 4
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@memcpy_volatile
+; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) [[ATTR10:#.*]] {
+; IS__TUNIT____-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR17:#.*]]
+; IS__TUNIT____-NEXT:    ret i32 4
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@memcpy_volatile
+; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) [[ATTR10:#.*]] {
+; IS__CGSCC____-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR18:#.*]]
+; IS__CGSCC____-NEXT:    ret i32 4
 ;
   call void @llvm.memcpy(i8* %ptr1, i8* %ptr2, i32 8, i1 1)
   ret i32 4
 }
 
 ; TEST 15 - positive, non-volatile intrinsic.
 
 ; It is odd to add nocapture but a result of the llvm.memset nocapture.
 ;
 define i32 @memset_non_volatile(i8* %ptr1, i8 %val) {
-; CHECK: Function Attrs: argmemonly nosync nounwind willreturn writeonly
-; CHECK-LABEL: define {{[^@]+}}@memset_non_volatile
-; CHECK-SAME: (i8* nocapture writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] {
-; CHECK-NEXT:    call void @llvm.memset.p0i8.i32(i8* nocapture writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR20:#.*]]
-; CHECK-NEXT:    ret i32 4
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@memset_non_volatile
+; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] {
+; IS__TUNIT____-NEXT:    call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR18:#.*]]
+; IS__TUNIT____-NEXT:    ret i32 4
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@memset_non_volatile
+; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] {
+; IS__CGSCC____-NEXT:    call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR19:#.*]]
+; IS__CGSCC____-NEXT:    ret i32 4
 ;
   call void @llvm.memset(i8* %ptr1, i8 %val, i32 8, i1 0)
   ret i32 4
 }
 
 ; TEST 16 - negative, inline assembly.
 
 define i32 @inline_asm_test(i32 %x) {

 ; IS__CGSCC____-SAME: (float [[X:%.*]]) [[ATTR15:#.*]] {
 ; IS__CGSCC____-NEXT:    ret i32 4
 ;
   call float @llvm.cos(float %x)
   ret i32 4
 }
 
 define float @cos_test2(float %x) {
-; CHECK: Function Attrs: nosync nounwind readnone willreturn
-; CHECK-LABEL: define {{[^@]+}}@cos_test2
-; CHECK-SAME: (float [[X:%.*]]) [[ATTR16:#.*]] {
-; CHECK-NEXT:    [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR19]]
-; CHECK-NEXT:    ret float [[C]]
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@cos_test2
+; IS__TUNIT____-SAME: (float [[X:%.*]]) [[ATTR15]] {
+; IS__TUNIT____-NEXT:    [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR17]]
+; IS__TUNIT____-NEXT:    ret float [[C]]
+;
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@cos_test2
+; IS__CGSCC____-SAME: (float [[X:%.*]]) [[ATTR16:#.*]] {
+; IS__CGSCC____-NEXT:    [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR18]]
+; IS__CGSCC____-NEXT:    ret float [[C]]
 ;
   %c = call float @llvm.cos(float %x)
   ret float %c
 }

llvm/test/Transforms/Attributor/readattrs.ll

 }
 
 ; CHECK: declare void @llvm.masked.scatter
 declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>%val, <4 x i32*>, i32, <4 x i1>)
 
 ; CHECK-NOT: readnone
 ; CHECK-NOT: readonly
 define void @test9(<4 x i32*> %ptrs, <4 x i32>%val) {
-; IS__TUNIT____: Function Attrs: nounwind willreturn writeonly
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@test9
-; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR4:#.*]] {
-; IS__TUNIT____-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>) [[ATTR11:#.*]]
+; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR0]] {
+; IS__TUNIT____-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>) [[ATTR10:#.*]]
 ; IS__TUNIT____-NEXT:    ret void
 ;
-; IS__CGSCC____: Function Attrs: nounwind willreturn writeonly
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@test9
 ; IS__CGSCC____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR4:#.*]] {
 ; IS__CGSCC____-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>) [[ATTR12:#.*]]
 ; IS__CGSCC____-NEXT:    ret void
 ;
   call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>%val, <4 x i32*> %ptrs, i32 4, <4 x i1><i1 true, i1 false, i1 true, i1 false>)
   ret void
 }
 
 ; CHECK: declare <4 x i32> @llvm.masked.gather
 declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
 define <4 x i32> @test10(<4 x i32*> %ptrs) {
-; IS__TUNIT____: Function Attrs: nounwind readonly willreturn
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@test10
-; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR5:#.*]] {
-; IS__TUNIT____-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef) [[ATTR12:#.*]]
+; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT____-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef) [[ATTR11:#.*]]
 ; IS__TUNIT____-NEXT:    ret <4 x i32> [[RES]]
 ;
-; IS__CGSCC____: Function Attrs: nounwind readonly willreturn
+; IS__CGSCC____: Function Attrs: nofree nosync nounwind readonly willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@test10
 ; IS__CGSCC____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR5:#.*]] {
 ; IS__CGSCC____-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef <i1 true, i1 false, i1 true, i1 false>, <4 x i32> undef) [[ATTR13:#.*]]
 ; IS__CGSCC____-NEXT:    ret <4 x i32> [[RES]]
 ;
   %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1><i1 true, i1 false, i1 true, i1 false>, <4 x i32>undef)
   ret <4 x i32> %res
 }
;
   ret <4 x i32> %res
 }
 
 declare <4 x i32> @test12_1(<4 x i32*>) argmemonly nounwind
 ; CHECK-NOT: readnone
 define <4 x i32> @test12_2(<4 x i32*> %ptrs) {
 ; IS__TUNIT____: Function Attrs: argmemonly nounwind
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@test12_2
-; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR7:#.*]] {
-; IS__TUNIT____-NEXT:    [[RES:%.*]] = call <4 x i32> @test12_1(<4 x i32*> [[PTRS]]) [[ATTR13:#.*]]
+; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR6:#.*]] {
+; IS__TUNIT____-NEXT:    [[RES:%.*]] = call <4 x i32> @test12_1(<4 x i32*> [[PTRS]]) [[ATTR12:#.*]]
 ; IS__TUNIT____-NEXT:    ret <4 x i32> [[RES]]
 ;
 ; IS__CGSCC____: Function Attrs: argmemonly nounwind
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@test12_2
 ; IS__CGSCC____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR7:#.*]] {
 ; IS__CGSCC____-NEXT:    [[RES:%.*]] = call <4 x i32> @test12_1(<4 x i32*> [[PTRS]]) [[ATTR14:#.*]]
 ; IS__CGSCC____-NEXT:    ret <4 x i32> [[RES]]
 ;
   %res = call <4 x i32> @test12_1(<4 x i32*> %ptrs)
   ret <4 x i32> %res
 }
 
 define i32 @volatile_load(i32* %p) {
 ; IS__TUNIT____: Function Attrs: argmemonly nofree nounwind willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@volatile_load
-; IS__TUNIT____-SAME: (i32* nofree align 4 [[P:%.*]]) [[ATTR8:#.*]] {
+; IS__TUNIT____-SAME: (i32* nofree align 4 [[P:%.*]]) [[ATTR7:#.*]] {
 ; IS__TUNIT____-NEXT:    [[LOAD:%.*]] = load volatile i32, i32* [[P]], align 4
 ; IS__TUNIT____-NEXT:    ret i32 [[LOAD]]
 ;
 ; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nounwind willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@volatile_load
 ; IS__CGSCC____-SAME: (i32* nofree align 4 [[P:%.*]]) [[ATTR8:#.*]] {
 ; IS__CGSCC____-NEXT:    [[LOAD:%.*]] = load volatile i32, i32* [[P]], align 4
 ; IS__CGSCC____-NEXT:    ret i32 [[LOAD]]

llvm/test/Transforms/Attributor/value-simplify.ll

 ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@test_preallocated
 ; IS__CGSCC____-SAME: (i32* noalias nofree noundef nonnull returned writeonly preallocated(i32) align 536870912 dereferenceable(4) "no-capture-maybe-returned" [[A:%.*]]) [[ATTR1]] {
 ; IS__CGSCC____-NEXT:    ret i32* [[A]]
 ;
   ret i32* %a
 }
 define i32* @complicated_args_preallocated() {
-; IS__TUNIT_OPM: Function Attrs: nounwind
+; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@complicated_args_preallocated
 ; IS__TUNIT_OPM-SAME: () [[ATTR0:#.*]] {
-; IS__TUNIT_OPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1)
-; IS__TUNIT_OPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR5:#.*]] [ "preallocated"(token [[C]]) ]
+; IS__TUNIT_OPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR5:#.*]]
+; IS__TUNIT_OPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR1:#.*]] [ "preallocated"(token [[C]]) ]
 ; IS__TUNIT_OPM-NEXT:    ret i32* [[CALL]]
 ;
-; IS__TUNIT_NPM: Function Attrs: nounwind
+; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@complicated_args_preallocated
 ; IS__TUNIT_NPM-SAME: () [[ATTR0:#.*]] {
-; IS__TUNIT_NPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1)
-; IS__TUNIT_NPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR4:#.*]] [ "preallocated"(token [[C]]) ]
+; IS__TUNIT_NPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR4:#.*]]
+; IS__TUNIT_NPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR1:#.*]] [ "preallocated"(token [[C]]) ]
 ; IS__TUNIT_NPM-NEXT:    ret i32* [[CALL]]
 ;
-; IS__CGSCC_OPM: Function Attrs: nounwind
+; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@complicated_args_preallocated
 ; IS__CGSCC_OPM-SAME: () [[ATTR0:#.*]] {
-; IS__CGSCC_OPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1)
+; IS__CGSCC_OPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR5]]
 ; IS__CGSCC_OPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR6:#.*]] [ "preallocated"(token [[C]]) ]
 ; IS__CGSCC_OPM-NEXT:    ret i32* [[CALL]]
 ;
-; IS__CGSCC_NPM: Function Attrs: nounwind
+; IS__CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@complicated_args_preallocated
 ; IS__CGSCC_NPM-SAME: () [[ATTR0:#.*]] {
-; IS__CGSCC_NPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1)
+; IS__CGSCC_NPM-NEXT:    [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR4]]
 ; IS__CGSCC_NPM-NEXT:    [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR5:#.*]] [ "preallocated"(token [[C]]) ]
 ; IS__CGSCC_NPM-NEXT:    ret i32* [[CALL]]
 ;
   %c = call token @llvm.call.preallocated.setup(i32 1)
   %call = call i32* @test_preallocated(i32* preallocated(i32) null) ["preallocated"(token %c)]
   ret i32* %call
 }
 

llvm/test/Transforms/Attributor/willreturn.ll

 define i32 @fib(i32 %0) local_unnamed_addr #0 {
 ; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@fib
 ; IS__TUNIT_OPM-SAME: (i32 [[TMP0:%.*]]) local_unnamed_addr [[ATTR1:#.*]] {
 ; IS__TUNIT_OPM-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP0]], 2
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP2]], label [[TMP9:%.*]], label [[TMP3:%.*]]
 ; IS__TUNIT_OPM:       3:
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = add nsw i32 [[TMP0]], -1
-; IS__TUNIT_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR16:#.*]]
+; IS__TUNIT_OPM-NEXT:    [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR15:#.*]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP6:%.*]] = add nsw i32 [[TMP0]], -2
-; IS__TUNIT_OPM-NEXT:    [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR16]]
+; IS__TUNIT_OPM-NEXT:    [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR15]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP8:%.*]] = add nsw i32 [[TMP7]], [[TMP5]]
 ; IS__TUNIT_OPM-NEXT:    ret i32 [[TMP8]]
 ; IS__TUNIT_OPM:       9:
 ; IS__TUNIT_OPM-NEXT:    ret i32 [[TMP0]]
 ;
 ; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@fib
 ; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]]) local_unnamed_addr [[ATTR1:#.*]] {
 ; IS__TUNIT_NPM-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP0]], 2
 ; IS__TUNIT_NPM-NEXT:    br i1 [[TMP2]], label [[TMP9:%.*]], label [[TMP3:%.*]]
 ; IS__TUNIT_NPM:       3:
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = add nsw i32 [[TMP0]], -1
-; IS__TUNIT_NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR17:#.*]]
+; IS__TUNIT_NPM-NEXT:    [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR16:#.*]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP6:%.*]] = add nsw i32 [[TMP0]], -2
-; IS__TUNIT_NPM-NEXT:    [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR17]]
+; IS__TUNIT_NPM-NEXT:    [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR16]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP8:%.*]] = add nsw i32 [[TMP7]], [[TMP5]]
 ; IS__TUNIT_NPM-NEXT:    ret i32 [[TMP8]]
 ; IS__TUNIT_NPM:       9:
 ; IS__TUNIT_NPM-NEXT:    ret i32 [[TMP0]]
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@fib
 ; IS__CGSCC_OPM-SAME: (i32 [[TMP0:%.*]]) local_unnamed_addr [[ATTR1:#.*]] {

 declare void @sink() nounwind willreturn nosync nofree
 
 define void @mutual_recursion1(i1 %c) #0 {
 ; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@mutual_recursion1
 ; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]]) [[ATTR3:#.*]] {
 ; IS__TUNIT_OPM-NEXT:    br i1 [[C]], label [[REC:%.*]], label [[END:%.*]]
 ; IS__TUNIT_OPM:       rec:
-; IS__TUNIT_OPM-NEXT:    call void @sink() [[ATTR12:#.*]]
-; IS__TUNIT_OPM-NEXT:    call void @mutual_recursion2(i1 [[C]]) [[ATTR17:#.*]]
+; IS__TUNIT_OPM-NEXT:    call void @sink() [[ATTR11:#.*]]
+; IS__TUNIT_OPM-NEXT:    call void @mutual_recursion2(i1 [[C]]) [[ATTR16:#.*]]
 ; IS__TUNIT_OPM-NEXT:    br label [[END]]
 ; IS__TUNIT_OPM:       end:
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@mutual_recursion1
 ; IS__TUNIT_NPM-SAME: (i1 [[C:%.*]]) [[ATTR3:#.*]] {
 ; IS__TUNIT_NPM-NEXT:    br i1 [[C]], label [[REC:%.*]], label [[END:%.*]]
 ; IS__TUNIT_NPM:       rec:
-; IS__TUNIT_NPM-NEXT:    call void @sink() [[ATTR12:#.*]]
-; IS__TUNIT_NPM-NEXT:    call void @mutual_recursion2(i1 noundef [[C]]) [[ATTR19:#.*]]
+; IS__TUNIT_NPM-NEXT:    call void @sink() [[ATTR11:#.*]]
+; IS__TUNIT_NPM-NEXT:    call void @mutual_recursion2(i1 noundef [[C]]) [[ATTR18:#.*]]
 ; IS__TUNIT_NPM-NEXT:    br label [[END]]
 ; IS__TUNIT_NPM:       end:
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@mutual_recursion1
 ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]]) [[ATTR4:#.*]] {
 ; IS__CGSCC_OPM-NEXT:    br i1 [[C]], label [[REC:%.*]], label [[END:%.*]]
end:
   ret void
 }
 
 
 define void @mutual_recursion2(i1 %c) #0 {
 ; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@mutual_recursion2
 ; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]]) [[ATTR3]] {
-; IS__TUNIT_OPM-NEXT:    call void @mutual_recursion1(i1 [[C]]) [[ATTR17]]
+; IS__TUNIT_OPM-NEXT:    call void @mutual_recursion1(i1 [[C]]) [[ATTR16]]
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@mutual_recursion2
 ; IS__TUNIT_NPM-SAME: (i1 [[C:%.*]]) [[ATTR3]] {
-; IS__TUNIT_NPM-NEXT:    call void @mutual_recursion1(i1 [[C]]) [[ATTR19]]
+; IS__TUNIT_NPM-NEXT:    call void @mutual_recursion1(i1 [[C]]) [[ATTR18]]
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind uwtable
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@mutual_recursion2
 ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]]) [[ATTR4]] {
 ; IS__CGSCC_OPM-NEXT:    call void @mutual_recursion1(i1 [[C]]) [[ATTR20]]
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
; <label>:8:                                      ; preds = %5
   unreachable
 
 ; <label>:9:                                      ; preds = %5
   ret void
 }
 
 ; TEST 6 (positive case)
 ; Call intrinsic function
-; CHECK: Function Attrs: nounwind readnone speculatable willreturn
+; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn
 ; CHECK-NEXT: declare float @llvm.floor.f32(float)
 declare float @llvm.floor.f32(float)
 
 define void @call_floor(float %a) #0 {
 ; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@call_floor
 ; IS__TUNIT____-SAME: (float [[A:%.*]]) [[ATTR0]] {
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@call_floor
 ; IS__CGSCC____-SAME: (float [[A:%.*]]) [[ATTR0]] {
 ; IS__CGSCC____-NEXT:    ret void
 ;
   tail call float @llvm.floor.f32(float %a)
   ret void
 }
 
 define float @call_floor2(float %a) #0 {
-; IS__TUNIT_OPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn
+; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@call_floor2
-; IS__TUNIT_OPM-SAME: (float [[A:%.*]]) [[ATTR8:#.*]] {
-; IS__TUNIT_OPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR18:#.*]]
+; IS__TUNIT_OPM-SAME: (float [[A:%.*]]) [[ATTR0:#.*]] {
+; IS__TUNIT_OPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR17:#.*]]
 ; IS__TUNIT_OPM-NEXT:    ret float [[C]]
 ;
-; IS__TUNIT_NPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn
+; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@call_floor2
-; IS__TUNIT_NPM-SAME: (float [[A:%.*]]) [[ATTR8:#.*]] {
-; IS__TUNIT_NPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR20:#.*]]
+; IS__TUNIT_NPM-SAME: (float [[A:%.*]]) [[ATTR0]] {
+; IS__TUNIT_NPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR19:#.*]]
 ; IS__TUNIT_NPM-NEXT:    ret float [[C]]
 ;
-; IS__CGSCC_OPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn
+; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@call_floor2
 ; IS__CGSCC_OPM-SAME: (float [[A:%.*]]) [[ATTR9:#.*]] {
 ; IS__CGSCC_OPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR21:#.*]]
 ; IS__CGSCC_OPM-NEXT:    ret float [[C]]
 ;
-; IS__CGSCC_NPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn
+; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor2
 ; IS__CGSCC_NPM-SAME: (float [[A:%.*]]) [[ATTR9:#.*]] {
 ; IS__CGSCC_NPM-NEXT:    [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR23:#.*]]
 ; IS__CGSCC_NPM-NEXT:    ret float [[C]]
 ;
   %c = tail call float @llvm.floor.f32(float %a)
   ret float %c
 }
 
 
 ; TEST 7 (negative case)
 ; Call function declaration without willreturn
 
 ; CHECK: Function Attrs: noinline nounwind uwtable
 ; CHECK-NOT: willreturn
 ; CHECK-NEXT: declare void @maybe_noreturn()
 declare void @maybe_noreturn() #0
 
 define void @call_maybe_noreturn() #0 {
 ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@call_maybe_noreturn
 ; IS__TUNIT_OPM-SAME: () [[ATTR6:#.*]] {
-; IS__TUNIT_OPM-NEXT:    tail call void @maybe_noreturn() [[ATTR19:#.*]]
+; IS__TUNIT_OPM-NEXT:    tail call void @maybe_noreturn() [[ATTR18:#.*]]
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@call_maybe_noreturn
 ; IS__TUNIT_NPM-SAME: () [[ATTR6:#.*]] {
-; IS__TUNIT_NPM-NEXT:    tail call void @maybe_noreturn() [[ATTR21:#.*]]
+; IS__TUNIT_NPM-NEXT:    tail call void @maybe_noreturn() [[ATTR20:#.*]]
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@call_maybe_noreturn
 ; IS__CGSCC_OPM-SAME: () [[ATTR7:#.*]] {
 ; IS__CGSCC_OPM-NEXT:    tail call void @maybe_noreturn() [[ATTR22:#.*]]
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;

 
 ; CHECK: Function Attrs: norecurse willreturn
 ; CHECK-NEXT: declare void @will_return()
 declare void @will_return() willreturn norecurse
 
 define void @f1() #0 {
 ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f1
-; IS__TUNIT_OPM-SAME: () [[ATTR10:#.*]] {
-; IS__TUNIT_OPM-NEXT:    tail call void @will_return() [[ATTR18]]
+; IS__TUNIT_OPM-SAME: () [[ATTR9:#.*]] {
+; IS__TUNIT_OPM-NEXT:    tail call void @will_return() [[ATTR17]]
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@f1
-; IS__TUNIT_NPM-SAME: () [[ATTR10:#.*]] {
-; IS__TUNIT_NPM-NEXT:    tail call void @will_return() [[ATTR20]]
+; IS__TUNIT_NPM-SAME: () [[ATTR9:#.*]] {
+; IS__TUNIT_NPM-NEXT:    tail call void @will_return() [[ATTR19]]
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;
 ; IS__CGSCC_OPM: Function Attrs: noinline norecurse nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f1
 ; IS__CGSCC_OPM-SAME: () [[ATTR11:#.*]] {
 ; IS__CGSCC_OPM-NEXT:    tail call void @will_return() [[ATTR21]]
 ; IS__CGSCC_OPM-NEXT:    ret void
 ;
 ; IS__CGSCC_NPM: Function Attrs: noinline norecurse nounwind uwtable willreturn
 ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f1
 ; IS__CGSCC_NPM-SAME: () [[ATTR11:#.*]] {
 ; IS__CGSCC_NPM-NEXT:    tail call void @will_return() [[ATTR23]]
 ; IS__CGSCC_NPM-NEXT:    ret void
 ;
   tail call void @will_return()
   ret void
 }
 
 define void @f2() #0 {
 ; IS__TUNIT____: Function Attrs: noinline nounwind uwtable willreturn
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@f2
-; IS__TUNIT____-SAME: () [[ATTR10:#.*]] {
-; IS__TUNIT____-NEXT:    tail call void @f1() [[ATTR12:#.*]]
+; IS__TUNIT____-SAME: () [[ATTR9:#.*]] {
+; IS__TUNIT____-NEXT:    tail call void @f1() [[ATTR11:#.*]]
 ; IS__TUNIT____-NEXT:    ret void
 ;
 ; IS__CGSCC____: Function Attrs: noinline norecurse nounwind uwtable willreturn
 ; IS__CGSCC____-LABEL: define {{[^@]+}}@f2
 ; IS__CGSCC____-SAME: () [[ATTR11:#.*]] {
 ; IS__CGSCC____-NEXT:    tail call void @f1() [[ATTR14:#.*]]
 ; IS__CGSCC____-NEXT:    ret void
 ;

 
 ; CHECK: Function Attrs: noinline uwtable willreturn
 ; CHECK-NEXT: declare i1 @maybe_raise_exception()
 declare i1 @maybe_raise_exception() #1 willreturn
 
 define void @invoke_test() personality i32 (...)* @__gxx_personality_v0 {
 ; IS__TUNIT_OPM: Function Attrs: nounwind willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@invoke_test
-; IS__TUNIT_OPM-SAME: () [[ATTR12]] personality i32 (...)* @__gxx_personality_v0 {
-; IS__TUNIT_OPM-NEXT:    [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR18]]
+; IS__TUNIT_OPM-SAME: () [[ATTR11]] personality i32 (...)* @__gxx_personality_v0 {
+; IS__TUNIT_OPM-NEXT:    [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR17]]
 ; IS__TUNIT_OPM-NEXT:    to label [[N:%.*]] unwind label [[F:%.*]]
 ; IS__TUNIT_OPM:       N:
 ; IS__TUNIT_OPM-NEXT:    ret void
 ; IS__TUNIT_OPM:       F:
 ; IS__TUNIT_OPM-NEXT:    [[VAL:%.*]] = landingpad { i8*, i32 }
 ; IS__TUNIT_OPM-NEXT:    catch i8* null
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: nounwind willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@invoke_test
-; IS__TUNIT_NPM-SAME: () [[ATTR12]] personality i32 (...)* @__gxx_personality_v0 {
-; IS__TUNIT_NPM-NEXT:    [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR20]]
+; IS__TUNIT_NPM-SAME: () [[ATTR11]] personality i32 (...)* @__gxx_personality_v0 {
+; IS__TUNIT_NPM-NEXT:    [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR19]]
 ; IS__TUNIT_NPM-NEXT:    to label [[N:%.*]] unwind label [[F:%.*]]
 ; IS__TUNIT_NPM:       N:
 ; IS__TUNIT_NPM-NEXT:    ret void
 ; IS__TUNIT_NPM:       F:
 ; IS__TUNIT_NPM-NEXT:    [[VAL:%.*]] = landingpad { i8*, i32 }
 ; IS__TUNIT_NPM-NEXT:    catch i8* null
 ; IS__TUNIT_NPM-NEXT:    ret void
 ;

 ;        ans += p[i];
 ;    }
 ;    return ans;
 ; }
 
 define i32 @loop_constant_trip_count(i32* nocapture readonly %0) #0 {
 ; IS__TUNIT_OPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@loop_constant_trip_count
-; IS__TUNIT_OPM-SAME: (i32* nocapture nofree readonly [[TMP0:%.*]]) [[ATTR13:#.*]] {
+; IS__TUNIT_OPM-SAME: (i32* nocapture nofree readonly [[TMP0:%.*]]) [[ATTR12:#.*]] {
 ; IS__TUNIT_OPM-NEXT:    br label [[TMP3:%.*]]
 ; IS__TUNIT_OPM:       2:
 ; IS__TUNIT_OPM-NEXT:    ret i32 [[TMP8:%.*]]
 ; IS__TUNIT_OPM:       3:
 ; IS__TUNIT_OPM-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP1:%.*]] ], [ [[TMP9:%.*]], [[TMP3]] ]
 ; IS__TUNIT_OPM-NEXT:    [[TMP5:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP8]], [[TMP3]] ]
 ; IS__TUNIT_OPM-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[TMP4]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
 ; IS__TUNIT_OPM-NEXT:    [[TMP8]] = add nsw i32 [[TMP7]], [[TMP5]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP9]] = add nuw nsw i64 [[TMP4]], 1
 ; IS__TUNIT_OPM-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 10
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP10]], label [[TMP2:%.*]], label [[TMP3]]
 ;
 ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@loop_constant_trip_count
-; IS__TUNIT_NPM-SAME: (i32* nocapture nofree nonnull readonly dereferenceable(4) [[TMP0:%.*]]) [[ATTR13:#.*]] {
+; IS__TUNIT_NPM-SAME: (i32* nocapture nofree nonnull readonly dereferenceable(4) [[TMP0:%.*]]) [[ATTR12:#.*]] {
 ; IS__TUNIT_NPM-NEXT:    br label [[TMP3:%.*]]
 ; IS__TUNIT_NPM:       2:
 ; IS__TUNIT_NPM-NEXT:    ret i32 [[TMP8:%.*]]
 ; IS__TUNIT_NPM:       3:
 ; IS__TUNIT_NPM-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP1:%.*]] ], [ [[TMP9:%.*]], [[TMP3]] ]
 ; IS__TUNIT_NPM-NEXT:    [[TMP5:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP8]], [[TMP3]] ]
 ; IS__TUNIT_NPM-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[TMP4]]
 ; IS__TUNIT_NPM-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4

 ;     for(unsigned i = s;i != e;i+=offset){
 ;         ans += p[i];
 ;     }
 ;     return ans;
 ; }
 define i32 @loop_trip_count_unbound(i32 %0, i32 %1, i32* nocapture readonly %2, i32 %3) local_unnamed_addr #0 {
 ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@loop_trip_count_unbound
-; IS__TUNIT____-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32* nocapture nofree readonly [[TMP2:%.*]], i32 [[TMP3:%.*]]) local_unnamed_addr [[ATTR14:#.*]] {
+; IS__TUNIT____-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32* nocapture nofree readonly [[TMP2:%.*]], i32 [[TMP3:%.*]]) local_unnamed_addr [[ATTR13:#.*]] {
 ; IS__TUNIT____-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP0]], [[TMP1]]
 ; IS__TUNIT____-NEXT:    br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP8:%.*]]
 ; IS__TUNIT____:       6:
 ; IS__TUNIT____-NEXT:    [[TMP7:%.*]] = phi i32 [ 0, [[TMP4:%.*]] ], [ [[TMP14:%.*]], [[TMP8]] ]
 ; IS__TUNIT____-NEXT:    ret i32 [[TMP7]]
 ; IS__TUNIT____:       8:
 ; IS__TUNIT____-NEXT:    [[TMP9:%.*]] = phi i32 [ [[TMP15:%.*]], [[TMP8]] ], [ [[TMP0]], [[TMP4]] ]
 ; IS__TUNIT____-NEXT:    [[TMP10:%.*]] = phi i32 [ [[TMP14]], [[TMP8]] ], [ 0, [[TMP4]] ]

 ;    }
 ;    return ans;
 ;  }
 
 
 define i32 @loop_trip_dec(i32 %0, i32* nocapture readonly %1) local_unnamed_addr #0 {
 ; IS__TUNIT_OPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@loop_trip_dec
-; IS__TUNIT_OPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR13]] {
+; IS__TUNIT_OPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR12]] {
 ; IS__TUNIT_OPM-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP0]], -1
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP14:%.*]]
 ; IS__TUNIT_OPM:       4:
 ; IS__TUNIT_OPM-NEXT:    [[TMP5:%.*]] = sext i32 [[TMP0]] to i64
 ; IS__TUNIT_OPM-NEXT:    br label [[TMP6:%.*]]
 ; IS__TUNIT_OPM:       6:
 ; IS__TUNIT_OPM-NEXT:    [[TMP7:%.*]] = phi i64 [ [[TMP5]], [[TMP4]] ], [ [[TMP12:%.*]], [[TMP6]] ]
 ; IS__TUNIT_OPM-NEXT:    [[TMP8:%.*]] = phi i32 [ 0, [[TMP4]] ], [ [[TMP11:%.*]], [[TMP6]] ]
 ; IS__TUNIT_OPM-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[TMP7]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
 ; IS__TUNIT_OPM-NEXT:    [[TMP11]] = add nsw i32 [[TMP10]], [[TMP8]]
 ; IS__TUNIT_OPM-NEXT:    [[TMP12]] = add nsw i64 [[TMP7]], -1
 ; IS__TUNIT_OPM-NEXT:    [[TMP13:%.*]] = icmp sgt i64 [[TMP7]], 0
 ; IS__TUNIT_OPM-NEXT:    br i1 [[TMP13]], label [[TMP6]], label [[TMP14]]
 ; IS__TUNIT_OPM:       14:
 ; IS__TUNIT_OPM-NEXT:    [[TMP15:%.*]] = phi i32 [ 0, [[TMP2:%.*]] ], [ [[TMP11]], [[TMP6]] ]
 ; IS__TUNIT_OPM-NEXT:    ret i32 [[TMP15]]
 ;
 ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@loop_trip_dec
-; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR13]] {
+; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR12]] {
 ; IS__TUNIT_NPM-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP0]], -1
 ; IS__TUNIT_NPM-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP14:%.*]]
 ; IS__TUNIT_NPM:       4:
 ; IS__TUNIT_NPM-NEXT:    [[TMP5:%.*]] = sext i32 [[TMP0]] to i64
 ; IS__TUNIT_NPM-NEXT:    br label [[TMP6:%.*]]
 ; IS__TUNIT_NPM:       6:
 ; IS__TUNIT_NPM-NEXT:    [[TMP7:%.*]] = phi i64 [ [[TMP5]], [[TMP4]] ], [ [[TMP12:%.*]], [[TMP6]] ]
 ; IS__TUNIT_NPM-NEXT:    [[TMP8:%.*]] = phi i32 [ 0, [[TMP4]] ], [ [[TMP11:%.*]], [[TMP6]] ]

 
 ; TEST 15 (positive & negative case)
 ; unreachable exit
 
 ; 15.1 (positive case)
 define void @unreachable_exit_positive1() #0 {
 ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable willreturn
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unreachable_exit_positive1
-; IS__TUNIT_OPM-SAME: () [[ATTR10]] {
-; IS__TUNIT_OPM-NEXT:    tail call void @will_return() [[ATTR18]]
+; IS__TUNIT_OPM-SAME: () [[ATTR9]] {
+; IS__TUNIT_OPM-NEXT:    tail call void @will_return() [[ATTR17]]
 ; IS__TUNIT_OPM-NEXT:    ret void
 ; IS__TUNIT_OPM:       unreachable_label:
 ; IS__TUNIT_OPM-NEXT:    unreachable
 ;
 ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@unreachable_exit_positive1
-; IS__TUNIT_NPM-SAME: () [[ATTR10]] {
-; IS__TUNIT_NPM-NEXT:    tail call void @will_return() [[ATTR20]]
+; IS__TUNIT_NPM-SAME: () [[ATTR9]] {
+; IS__TUNIT_NPM-NEXT:    tail call void @will_return() [[ATTR19]]
 ; IS__TUNIT_NPM-NEXT:    ret void
 ; IS__TUNIT_NPM:       unreachable_label:
 ; IS__TUNIT_NPM-NEXT:    unreachable
 ;
 ; IS__CGSCC_OPM: Function Attrs: noinline norecurse nounwind uwtable willreturn
 ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@unreachable_exit_positive1
 ; IS__CGSCC_OPM-SAME: () [[ATTR11]] {
 ; IS__CGSCC_OPM-NEXT:    tail call void @will_return() [[ATTR21]]

 unreachable_label:
   tail call void @exit(i32 0)
   unreachable
 }
 
 define void @unreachable_exit_negative2() #0 {
 ; IS__TUNIT____: Function Attrs: nofree noinline noreturn nosync nounwind readnone uwtable
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@unreachable_exit_negative2
-; IS__TUNIT____-SAME: () [[ATTR15:#.*]] {
+; IS__TUNIT____-SAME: () [[ATTR14:#.*]] {
 ; IS__TUNIT____-NEXT:    br label [[L1:%.*]]
 ; IS__TUNIT____:       L1:
 ; IS__TUNIT____-NEXT:    br label [[L2:%.*]]
 ; IS__TUNIT____:       L2:
 ; IS__TUNIT____-NEXT:    br label [[L1]]
 ; IS__TUNIT____:       unreachable_label:
 ; IS__TUNIT____-NEXT:    unreachable
 ;

 ;       ans++;
 ;   }
 ;   return ans;
 ; }
 
 define i32 @infinite_loop_inside_bounded_loop(i32 %n) {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@infinite_loop_inside_bounded_loop
-; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17:#.*]] {
+; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16:#.*]] {
 ; IS__TUNIT____-NEXT:  entry:
 ; IS__TUNIT____-NEXT:    br label [[FOR_COND:%.*]]
 ; IS__TUNIT____:       for.cond:
 ; IS__TUNIT____-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[N]], 0
 ; IS__TUNIT____-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; IS__TUNIT____:       for.cond.cleanup:
 ; IS__TUNIT____-NEXT:    br label [[FOR_END:%.*]]
 ; IS__TUNIT____:       for.body:

 ;     }
 ;   }
 ;   return ans;
 ; }
 
 define i32 @bounded_nested_loops(i32 %n) {
 ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@bounded_nested_loops
-; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] {
+; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR15]] {
 ; IS__TUNIT_OPM-NEXT:  entry:
 ; IS__TUNIT_OPM-NEXT:    br label [[FOR_COND:%.*]]
 ; IS__TUNIT_OPM:       for.cond:
 ; IS__TUNIT_OPM-NEXT:    [[I_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[FOR_INC:%.*]] ]
 ; IS__TUNIT_OPM-NEXT:    [[ANS_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP:%.*]], [[FOR_INC]] ]
 ; IS__TUNIT_OPM-NEXT:    [[N_ADDR_0:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ -1, [[FOR_INC]] ]
 ; IS__TUNIT_OPM-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N_ADDR_0]]
 ; IS__TUNIT_OPM-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]

 ; IS__TUNIT_OPM:       for.inc:
 ; IS__TUNIT_OPM-NEXT:    [[INC1]] = add nuw nsw i32 [[I_0]], 1
 ; IS__TUNIT_OPM-NEXT:    br label [[FOR_COND]]
 ; IS__TUNIT_OPM:       for.end:
 ; IS__TUNIT_OPM-NEXT:    ret i32 [[ANS_0_LCSSA]]
 ;
 ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@bounded_nested_loops
-; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR18:#.*]] {
+; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR17:#.*]] {
 ; IS__TUNIT_NPM-NEXT:  entry:
 ; IS__TUNIT_NPM-NEXT:    br label [[FOR_COND:%.*]]
 ; IS__TUNIT_NPM:       for.cond:
 ; IS__TUNIT_NPM-NEXT:    [[I_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[FOR_INC:%.*]] ]
 ; IS__TUNIT_NPM-NEXT:    [[ANS_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP:%.*]], [[FOR_INC]] ]
 ; IS__TUNIT_NPM-NEXT:    [[N_ADDR_0:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ -1, [[FOR_INC]] ]
 ; IS__TUNIT_NPM-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N_ADDR_0]]
 ; IS__TUNIT_NPM-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]

 ;     }
 ;   }
 ;   return ans;
 ; }
 
 define i32 @bounded_loop_inside_unbounded_loop(i32 %n) {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@bounded_loop_inside_unbounded_loop
-; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17]] {
+; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16]] {
 ; IS__TUNIT____-NEXT:  entry:
 ; IS__TUNIT____-NEXT:    br label [[WHILE_COND:%.*]]
 ; IS__TUNIT____:       while.cond:
 ; IS__TUNIT____-NEXT:    [[ANS_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[FOR_END:%.*]] ]
 ; IS__TUNIT____-NEXT:    [[N_ADDR_0:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ [[INC:%.*]], [[FOR_END]] ]
 ; IS__TUNIT____-NEXT:    [[TMP:%.*]] = icmp sgt i32 [[N_ADDR_0]], -1
 ; IS__TUNIT____-NEXT:    [[SMAX:%.*]] = select i1 [[TMP]], i32 [[N_ADDR_0]], i32 -1
 ; IS__TUNIT____-NEXT:    [[INC]] = add nsw i32 [[N_ADDR_0]], 1

 ;     }
 ;   }
 ;   return ans;
 ; }
 
 define i32 @nested_unbounded_loops(i32 %n) {
 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT____-LABEL: define {{[^@]+}}@nested_unbounded_loops
-; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17]] {
+; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16]] {
 ; IS__TUNIT____-NEXT:  entry:
 ; IS__TUNIT____-NEXT:    br label [[WHILE_COND:%.*]]
 ; IS__TUNIT____:       while.cond:
 ; IS__TUNIT____-NEXT:    [[ANS_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[WHILE_END10:%.*]] ]
 ; IS__TUNIT____-NEXT:    [[N_ADDR_0:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ -1, [[WHILE_END10]] ]
 ; IS__TUNIT____-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[N_ADDR_0]], 0
 ; IS__TUNIT____-NEXT:    br i1 [[TOBOOL]], label [[WHILE_END11:%.*]], label [[WHILE_BODY:%.*]]
 ; IS__TUNIT____:       while.body:

 ;        goto entry1;
 ;    exit:
 ;      return;
 ;    }
 
 define void @non_loop_cycle(i32 %n) {
 ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@non_loop_cycle
-; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] {
+; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR15]] {
 ; IS__TUNIT_OPM-NEXT:  entry:
-; IS__TUNIT_OPM-NEXT:    [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
+; IS__TUNIT_OPM-NEXT:    [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]]
 ; IS__TUNIT_OPM-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CALL]], 5
 ; IS__TUNIT_OPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; IS__TUNIT_OPM:       if.then:
 ; IS__TUNIT_OPM-NEXT:    br label [[ENTRY1:%.*]]
 ; IS__TUNIT_OPM:       if.else:
 ; IS__TUNIT_OPM-NEXT:    br label [[ENTRY2:%.*]]
 ; IS__TUNIT_OPM:       entry1:
-; IS__TUNIT_OPM-NEXT:    [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
+; IS__TUNIT_OPM-NEXT:    [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]]
 ; IS__TUNIT_OPM-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[CALL1]], 5
 ; IS__TUNIT_OPM-NEXT:    br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_ELSE4:%.*]]
 ; IS__TUNIT_OPM:       if.then3:
 ; IS__TUNIT_OPM-NEXT:    br label [[EXIT:%.*]]
 ; IS__TUNIT_OPM:       if.else4:
 ; IS__TUNIT_OPM-NEXT:    br label [[ENTRY2]]
 ; IS__TUNIT_OPM:       entry2:
-; IS__TUNIT_OPM-NEXT:    [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
+; IS__TUNIT_OPM-NEXT:    [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]]
 ; IS__TUNIT_OPM-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[CALL5]], 5
 ; IS__TUNIT_OPM-NEXT:    br i1 [[CMP6]], label [[IF_THEN7:%.*]], label [[IF_ELSE8:%.*]]
 ; IS__TUNIT_OPM:       if.then7:
 ; IS__TUNIT_OPM-NEXT:    br label [[EXIT]]
 ; IS__TUNIT_OPM:       if.else8:
 ; IS__TUNIT_OPM-NEXT:    br label [[ENTRY1]]
 ; IS__TUNIT_OPM:       exit:
 ; IS__TUNIT_OPM-NEXT:    ret void
 ;
 ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone
 ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@non_loop_cycle
-; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR17]] {
+; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] {
 ; IS__TUNIT_NPM-NEXT:  entry:
-; IS__TUNIT_NPM-NEXT:    [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]]
+; IS__TUNIT_NPM-NEXT:    [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
 ; IS__TUNIT_NPM-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[CALL]], 5
 ; IS__TUNIT_NPM-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; IS__TUNIT_NPM:       if.then:
 ; IS__TUNIT_NPM-NEXT:    br label [[ENTRY1:%.*]]
 ; IS__TUNIT_NPM:       if.else:
 ; IS__TUNIT_NPM-NEXT:    br label [[ENTRY2:%.*]]
 ; IS__TUNIT_NPM:       entry1:
-; IS__TUNIT_NPM-NEXT:    [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]]
+; IS__TUNIT_NPM-NEXT:    [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
 ; IS__TUNIT_NPM-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[CALL1]], 5
 ; IS__TUNIT_NPM-NEXT:    br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_ELSE4:%.*]]
 ; IS__TUNIT_NPM:       if.then3:
 ; IS__TUNIT_NPM-NEXT:    br label [[EXIT:%.*]]
 ; IS__TUNIT_NPM:       if.else4:
 ; IS__TUNIT_NPM-NEXT:    br label [[ENTRY2]]
 ; IS__TUNIT_NPM:       entry2:
-; IS__TUNIT_NPM-NEXT:    [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]]
+; IS__TUNIT_NPM-NEXT:    [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]]
 ; IS__TUNIT_NPM-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[CALL5]], 5
 ; IS__TUNIT_NPM-NEXT:    br i1 [[CMP6]], label [[IF_THEN7:%.*]], label [[IF_ELSE8:%.*]]
 ; IS__TUNIT_NPM:       if.then7:
 ; IS__TUNIT_NPM-NEXT:    br label [[EXIT]]
 ; IS__TUNIT_NPM:       if.else8:
 ; IS__TUNIT_NPM-NEXT:    br label [[ENTRY1]]
 ; IS__TUNIT_NPM:       exit:
 ; IS__TUNIT_NPM-NEXT:    ret void

llvm/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
 ; RUN: opt -S -deadargelim < %s | FileCheck %s
 
 @.str = private constant [1 x i8] zeroinitializer, align 1 ; <[1 x i8]*> [#uses=1]
 
 define i8* @vfs_addname(i8* %name, i32 %len, i32 %hash, i32 %flags) nounwind ssp {
+;
 entry:
   call void @llvm.dbg.value(metadata i8* %name, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   call void @llvm.dbg.value(metadata i32 %len, metadata !10, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   call void @llvm.dbg.value(metadata i32 %hash, metadata !11, metadata !DIExpression()), !dbg !DILocation(scope: !1)
   call void @llvm.dbg.value(metadata i32 %flags, metadata !12, metadata !DIExpression()), !dbg !DILocation(scope: !1)
 ; CHECK:  call fastcc i8* @add_name_internal(i8* %name, i32 %hash) [[NUW:#[0-9]+]], !dbg !{{[0-9]+}}
   %0 = call fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext 0, i32 %flags) nounwind, !dbg !13 ; <i8*> [#uses=1]
   ret i8* %0, !dbg !13
 }
 
 declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone
 
 define internal fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext %extra, i32 %flags) noinline nounwind ssp {
+;
 entry:
   call void @llvm.dbg.value(metadata i8* %name, metadata !15, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   call void @llvm.dbg.value(metadata i32 %len, metadata !20, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   call void @llvm.dbg.value(metadata i32 %hash, metadata !21, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   call void @llvm.dbg.value(metadata i8 %extra, metadata !22, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   call void @llvm.dbg.value(metadata i32 %flags, metadata !23, metadata !DIExpression()), !dbg !DILocation(scope: !16)
   %0 = icmp eq i32 %hash, 0, !dbg !24             ; <i1> [#uses=1]
   br i1 %0, label %bb, label %bb1, !dbg !24
 
 bb:                                               ; preds = %entry
   br label %bb2, !dbg !26
 
 bb1:                                              ; preds = %entry
   br label %bb2, !dbg !27
 
 bb2:                                              ; preds = %bb1, %bb
   %.0 = phi i8* [ getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0), %bb ], [ %name, %bb1 ] ; <i8*> [#uses=1]
   ret i8* %.0, !dbg !27
 }
 
 declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone
 
 ; CHECK: attributes #0 = { nounwind ssp }
-; CHECK: attributes #1 = { nounwind readnone speculatable willreturn }
+; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
 ; CHECK: attributes #2 = { noinline nounwind ssp }
 ; CHECK: attributes [[NUW]] = { nounwind }
 
 !llvm.dbg.cu = !{!3}
 !llvm.module.flags = !{!30}
 !0 = !DILocalVariable(name: "name", line: 8, arg: 1, scope: !1, file: !2, type: !6)
 !1 = distinct !DISubprogram(name: "vfs_addname", linkageName: "vfs_addname", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !28, scope: !2, type: !4)
 !2 = !DIFile(filename: "tail.c", directory: "/Users/echeng/LLVM/radars/r7927803/")

llvm/test/Transforms/DeadArgElim/keepalive.ll

 ; RUN: opt < %s -deadargelim -S | FileCheck %s
 
 declare token @llvm.call.preallocated.setup(i32)
 declare i8* @llvm.call.preallocated.arg(token, i32)
 
 %Ty = type <{ i32, i32 }>
 
 ; Check if the pass doesn't modify anything that doesn't need changing. We feed
 ; an unused argument to each function to lure it into changing _something_ about
 ; the function and then changing too much.
 
 ; This checks if the return value attributes are not removed
-; CHECK: define internal zeroext i32 @test1() #0
+; CHECK: define internal zeroext i32 @test1() #1
 define internal zeroext i32 @test1(i32 %DEADARG1) nounwind {
-        ret i32 1
+;
+;
 }
 
 ; This checks if the struct doesn't get non-packed
 ; CHECK-LABEL: define internal <{ i32, i32 }> @test2(
 define internal <{ i32, i32 }> @test2(i32 %DEADARG1) {
-        ret <{ i32, i32 }> <{ i32 1, i32 2 }>
+;
+;
 }
 
 ; We use this external function to make sure the return values don't become dead
 declare void @user(i32, <{ i32, i32 }>)
 
 define void @caller() {
-        %B = call i32 @test1(i32 1)
-        %C = call <{ i32, i32 }> @test2(i32 2)
-        call void @user(i32 %B, <{ i32, i32 }> %C)
-        ret void
+;
+;
 }
 
 ; We can't remove 'this' here, as that would put argmem in ecx instead of
 ; memory.
 define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) {
-  %v = load i32, i32* %argmem
-  ret i32 %v
+;
+;
+  %v = load i32, i32* %argmem
+  ret i32 %v
 }
 ; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem)
 
 define i32 @caller2() {
-  %t = alloca i32
-  %m = alloca inalloca i32
-  store i32 42, i32* %m
-  %v = call x86_thiscallcc i32 @unused_this(i32* %t, i32* inalloca %m)
-  ret i32 %v
+;
+;
+  %t = alloca i32
+  %m = alloca inalloca i32
+  store i32 42, i32* %m
+  %v = call x86_thiscallcc i32 @unused_this(i32* %t, i32* inalloca %m)
+  ret i32 %v
 }
 
 ; We can't remove 'this' here, as that would put argmem in ecx instead of
 ; memory.
 define internal x86_thiscallcc i32 @unused_this_preallocated(i32* %this, i32* preallocated(i32) %argmem) {
-  %v = load i32, i32* %argmem
-  ret i32 %v
+;
+;
+  %v = load i32, i32* %argmem
+  ret i32 %v
 }
 ; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this_preallocated(i32* %this, i32* preallocated(i32) %argmem)
 
 define i32 @caller3() {
-  %t = alloca i32
-  %c = call token @llvm.call.preallocated.setup(i32 1)
-  %M = call i8* @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32)
-  %m = bitcast i8* %M to i32*
-  store i32 42, i32* %m
-  %v = call x86_thiscallcc i32 @unused_this_preallocated(i32* %t, i32* preallocated(i32) %m) ["preallocated"(token %c)]
-  ret i32 %v
+;
+;
+  %t = alloca i32
+  %c = call token @llvm.call.preallocated.setup(i32 1)
+  %M = call i8* @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32)
+  %m = bitcast i8* %M to i32*
+  store i32 42, i32* %m
+  %v = call x86_thiscallcc i32 @unused_this_preallocated(i32* %t, i32* preallocated(i32) %m) ["preallocated"(token %c)]
+  ret i32 %v
 }
 
-; CHECK: attributes #0 = { nounwind }
+; CHECK: attributes #0 = { nofree nosync nounwind willreturn }
+; CHECK: attributes #1 = { nounwind }

llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -basic-aa -dse -enable-dse-memoryssa=false -S | FileCheck %s
 ; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa=false -S | FileCheck %s
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
 declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture, i8, i64, i32) nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
 declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
 declare void @llvm.init.trampoline(i8*, i8*, i8*)
 
 define void @test1(i32* %Q, i32* %P) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    store i32 0, i32* [[P:%.*]]
+; CHECK-NEXT:    store i32 0, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
   %DEAD = load i32, i32* %Q
   store i32 %DEAD, i32* %P
   store i32 0, i32* %P
   ret void
 }
 
;
   %tmp3 = load i32, i32* @g, align 4
   ret i32 %tmp3
 }
 
 
 define void @test4(i32* %Q) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:    [[A:%.*]] = load i32, i32* [[Q:%.*]], align 4
-; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Q]]
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Q]], align 4
 ; CHECK-NEXT:    ret void
 ;
   %a = load i32, i32* %Q
   store volatile i32 %a, i32* %Q
   ret void
 }
 
 define void @test5(i32* %Q) {
;
   call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 %q, i8* align 4 %r, i64 900, i32 4)
   store atomic i32 30, i32* %p unordered, align 4
   ret void
 }
 
 ; Do not delete stores that are only partially killed.
 define i32 @test8() {
 ; CHECK-LABEL: @test8(
-; CHECK-NEXT:    [[V:%.*]] = alloca i32
-; CHECK-NEXT:    store i32 1234567, i32* [[V]]
-; CHECK-NEXT:    [[X:%.*]] = load i32, i32* [[V]]
+; CHECK-NEXT:    [[V:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    store i32 1234567, i32* [[V]], align 4
+; CHECK-NEXT:    [[X:%.*]] = load i32, i32* [[V]], align 4
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %V = alloca i32
   store i32 1234567, i32* %V
   %V2 = bitcast i32* %V to i8*
   store i8 0, i8* %V2
   %X = load i32, i32* %V
   ret i32 %X
;
   %tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0
   store i32 1, i32* %tmp2, align 4
   ret void
 }
 
 ; va_arg has fuzzy dependence, the store shouldn't be zapped.
 define double @test10(i8* %X) {
 ; CHECK-LABEL: @test10(
-; CHECK-NEXT:    [[X_ADDR:%.*]] = alloca i8*
-; CHECK-NEXT:    store i8* [[X:%.*]], i8** [[X_ADDR]]
+; CHECK-NEXT:    [[X_ADDR:%.*]] = alloca i8*, align 8
+; CHECK-NEXT:    store i8* [[X:%.*]], i8** [[X_ADDR]], align 8
 ; CHECK-NEXT:    [[TMP_0:%.*]] = va_arg i8** [[X_ADDR]], double
 ; CHECK-NEXT:    ret double [[TMP_0]]
 ;
   %X_addr = alloca i8*
   store i8* %X, i8** %X_addr
   %tmp.0 = va_arg i8** %X_addr, double
   ret double %tmp.0
 }

 
 ; %P doesn't escape, the DEAD instructions should be removed.
 declare void @test13f()
 define i32* @test13() {
 ; CHECK-LABEL: @test13(
 ; CHECK-NEXT:    [[PTR:%.*]] = tail call i8* @malloc(i32 4)
 ; CHECK-NEXT:    [[P:%.*]] = bitcast i8* [[PTR]] to i32*
 ; CHECK-NEXT:    call void @test13f()
-; CHECK-NEXT:    store i32 0, i32* [[P]]
+; CHECK-NEXT:    store i32 0, i32* [[P]], align 4
 ; CHECK-NEXT:    ret i32* [[P]]
 ;
   %ptr = tail call i8* @malloc(i32 4)
   %P = bitcast i8* %ptr to i32*
   %DEAD = load i32, i32* %P
   %DEAD2 = add i32 %DEAD, 1
   store i32 %DEAD2, i32* %P
   call void @test13f( )
   store i32 0, i32* %P
   ret i32* %P
 }
 
 define i32 addrspace(1)* @test13_addrspacecast() {
 ; CHECK-LABEL: @test13_addrspacecast(
 ; CHECK-NEXT:    [[P:%.*]] = tail call i8* @malloc(i32 4)
 ; CHECK-NEXT:    [[P_BC:%.*]] = bitcast i8* [[P]] to i32*
 ; CHECK-NEXT:    [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)*
 ; CHECK-NEXT:    call void @test13f()
-; CHECK-NEXT:    store i32 0, i32 addrspace(1)* [[P]]
+; CHECK-NEXT:    store i32 0, i32 addrspace(1)* [[P]], align 4
 ; CHECK-NEXT:    ret i32 addrspace(1)* [[P]]
 ;
   %p = tail call i8* @malloc(i32 4)
   %p.bc = bitcast i8* %p to i32*
   %P = addrspacecast i32* %p.bc to i32 addrspace(1)*
   %DEAD = load i32, i32 addrspace(1)* %P
   %DEAD2 = add i32 %DEAD, 1
   store i32 %DEAD2, i32 addrspace(1)* %P
;
   store i32 %DEAD, i32* %P
   ret void
 
 }
 
 ; Dead store on an aligned_alloc: should know that %M doesn't alias with %A.
 define i32 @test14a(i8* %M, i8 %value) {
 ; CHECK-LABEL: @test14a(
-; CHECK-NOT: store
-; CHECK:     ret i32 0
+; CHECK-NEXT:    [[A:%.*]] = tail call i8* @aligned_alloc(i32 32, i32 1024)
+; CHECK-NEXT:    tail call void @free(i8* [[A]])
+; CHECK-NEXT:    ret i32 0
 ;
   %A = tail call i8* @aligned_alloc(i32 32, i32 1024)
   store i8 %value, i8* %A
   tail call void @free(i8* %A)
   ret i32 0
 }
 
 ; PR8701

 
 ; The store here is not dead because the byval call reads it.
 declare void @test19f({i32}* byval align 4 %P)
 
 define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp {
 ; CHECK-LABEL: @test19(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0
-; CHECK-NEXT:    store i32 912, i32* [[TMP7]]
+; CHECK-NEXT:    store i32 912, i32* [[TMP7]], align 4
 ; CHECK-NEXT:    call void @test19f({ i32 }* byval align 4 [[ARG5]])
 ; CHECK-NEXT:    ret void
 ;
 bb:
   %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0
   store i32 912, i32* %tmp7
   call void @test19f({i32}* byval align 4 %arg5)
   ret void

 declare noalias i8* @strdup(i8* nocapture) nounwind
 define noalias i8* @test23() nounwind uwtable ssp {
 ; CHECK-LABEL: @test23(
 ; CHECK-NEXT:    [[X:%.*]] = alloca [2 x i8], align 1
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8], [2 x i8]* [[X]], i64 0, i64 0
 ; CHECK-NEXT:    store i8 97, i8* [[ARRAYIDX]], align 1
 ; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], [2 x i8]* [[X]], i64 0, i64 1
 ; CHECK-NEXT:    store i8 0, i8* [[ARRAYIDX1]], align 1
-; CHECK-NEXT:    [[CALL:%.*]] = call i8* @strdup(i8* [[ARRAYIDX]]) #3
+; CHECK-NEXT:    [[CALL:%.*]] = call i8* @strdup(i8* [[ARRAYIDX]]) [[ATTR5:#.*]]
 ; CHECK-NEXT:    ret i8* [[CALL]]
 ;
   %x = alloca [2 x i8], align 1
   %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* %x, i64 0, i64 0
   store i8 97, i8* %arrayidx, align 1
   %arrayidx1 = getelementptr inbounds [2 x i8], [2 x i8]* %x, i64 0, i64 1
   store i8 0, i8* %arrayidx1, align 1
   %call = call i8* @strdup(i8* %arrayidx) nounwind

 }
 
 ; Check another case like PR13547 where strdup is not like malloc.
 define i8* @test25(i8* %p) nounwind {
 ; CHECK-LABEL: @test25(
 ; CHECK-NEXT:    [[P_4:%.*]] = getelementptr i8, i8* [[P:%.*]], i64 4
 ; CHECK-NEXT:    [[TMP:%.*]] = load i8, i8* [[P_4]], align 1
 ; CHECK-NEXT:    store i8 0, i8* [[P_4]], align 1
-; CHECK-NEXT:    [[Q:%.*]] = call i8* @strdup(i8* [[P]]) #6
+; CHECK-NEXT:    [[Q:%.*]] = call i8* @strdup(i8* [[P]]) [[ATTR8:#.*]]
 ; CHECK-NEXT:    store i8 [[TMP]], i8* [[P_4]], align 1
 ; CHECK-NEXT:    ret i8* [[Q]]
 ;
   %p.4 = getelementptr i8, i8* %p, i64 4
   %tmp = load i8, i8* %p.4, align 1
   store i8 0, i8* %p.4, align 1
   %q = call i8* @strdup(i8* %p) nounwind optsize
   store i8 %tmp, i8* %p.4, align 1
bb2:
   br i1 undef, label %bb1, label %bb3
 bb3:
   ret i32 0
 }
 
 ; Don't remove redundant store: unknown_func could unwind
 define void @test34(i32* noalias %p) {
 ; CHECK-LABEL: @test34(
-; CHECK-NEXT:    store i32 1, i32* [[P:%.*]]
+; CHECK-NEXT:    store i32 1, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    call void @unknown_func()
-; CHECK-NEXT:    store i32 0, i32* [[P]]
+; CHECK-NEXT:    store i32 0, i32* [[P]], align 4
 ; CHECK-NEXT:    ret void
 ;
   store i32 1, i32* %p
   call void @unknown_func()
   store i32 0, i32* %p
   ret void
 }
 
 ; Remove redundant store even with an unwinding function in the same block
 define void @test35(i32* noalias %p) {
 ; CHECK-LABEL: @test35(
 ; CHECK-NEXT:    call void @unknown_func()
-; CHECK-NEXT:    store i32 0, i32* [[P:%.*]]
+; CHECK-NEXT:    store i32 0, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
   call void @unknown_func()
   store i32 1, i32* %p
   store i32 0, i32* %p
   ret void
 }
 

 ; CHECK-LABEL: @test40(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]]
-; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]]
+; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]], align 1
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15
 ; CHECK-NEXT:    br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %m = call i8* @calloc(i32 9, i32 20)
   br label %loop

 ; CHECK-LABEL: @test41(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT:%.*]] ]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]]
-; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]]
+; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]], align 1
 ; CHECK-NEXT:    br label [[CONT]]
 ; CHECK:       cont:
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15
 ; CHECK-NEXT:    br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %m = call i8* @calloc(i32 9, i32 20)
   br label %loop

 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT:%.*]] ]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    br label [[CONT]]
 ; CHECK:       cont:
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15
 ; CHECK-NEXT:    br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %m = call i8* @calloc(i32 9, i32 20)
   br label %loop

 ; CHECK-LABEL: @test43(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT_2:%.*]] ]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]]
-; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]]
+; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]], align 1
 ; CHECK-NEXT:    br label [[CONT:%.*]]
 ; CHECK:       cont:
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    br label [[CONT_2]]
 ; CHECK:       cont.2:
 ; CHECK-NEXT:    [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15
 ; CHECK-NEXT:    br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT_2:%.*]] ]
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]]
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    br label [[CONT:%.*]]
 ; CHECK:       cont:
-; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]]
+; CHECK-NEXT:    store i8 1, i8* [[P_NEXT]], align 1
 ; CHECK-NEXT:    br label [[CONT_2]]
 ; CHECK:       cont.2:
 ; CHECK-NEXT:    [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15
 ; CHECK-NEXT:    br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:

 ; clobbering instructions.
 define i32 @test45(i1 %c) {
 ; CHECK-LABEL: @test45(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    [[P_1:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 1
-; CHECK-NEXT:    store i8 1, i8* [[P_1]]
+; CHECK-NEXT:    store i8 1, i8* [[P_1]], align 1
 ; CHECK-NEXT:    br label [[CONT:%.*]]
 ; CHECK:       false:
 ; CHECK-NEXT:    [[P_2:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 2
-; CHECK-NEXT:    store i8 1, i8* [[P_2]]
+; CHECK-NEXT:    store i8 1, i8* [[P_2]], align 1
 ; CHECK-NEXT:    br label [[CONT]]
 ; CHECK:       cont:
 ; CHECK-NEXT:    [[OFFSET:%.*]] = phi i64 [ 2, [[TRUE]] ], [ 1, [[FALSE]] ]
 ; CHECK-NEXT:    [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[OFFSET]]
-; CHECK-NEXT:    store i8 0, i8* [[P]]
+; CHECK-NEXT:    store i8 0, i8* [[P]], align 1
 ; CHECK-NEXT:    br label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %m = call i8* @calloc(i32 9, i32 20)
   br i1 %c, label %true, label %false
 

 define i32 @test46(i1 %c) {
 ; CHECK-LABEL: @test46(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[M:%.*]] = call i8* @calloc(i32 9, i32 20)
 ; CHECK-NEXT:    [[P_1:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 1
 ; CHECK-NEXT:    [[P_2:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 2
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
-; CHECK-NEXT:    store i8 1, i8* [[P_1]]
+; CHECK-NEXT:    store i8 1, i8* [[P_1]], align 1
 ; CHECK-NEXT:    br label [[CONT:%.*]]
 ; CHECK:       false:
-; CHECK-NEXT:    store i8 1, i8* [[P_1]]
+; CHECK-NEXT:    store i8 1, i8* [[P_1]], align 1
 ; CHECK-NEXT:    br label [[CONT]]
 ; CHECK:       cont:
 ; CHECK-NEXT:    br label [[RETURN:%.*]]
 ; CHECK:       return:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %m = call i8* @calloc(i32 9, i32 20)

llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[VLA_I:%.*]] = alloca float, i64 15000, align 16
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i1 [[B:%.*]], true
 ; CHECK-NEXT:    br i1 [[COND]], label [[EXIT:%.*]], label [[SPLIT:%.*]]
 ; CHECK:       split:
 ; CHECK-NEXT:    [[SAVEDSTACK:%.*]] = call i8* @llvm.stacksave()
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast float* [[VLA_I]] to i8*
 ; CHECK-NEXT:    call void @llvm.lifetime.start.p0i8(i64 60000, i8* [[TMP0]])
-; CHECK-NEXT:    call void @extern_call(float* nonnull [[VLA_I]]) #2
+; CHECK-NEXT:    call void @extern_call(float* nonnull [[VLA_I]]) #3
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[VLA_I]] to i8*
 ; CHECK-NEXT:    call void @llvm.lifetime.end.p0i8(i64 60000, i8* [[TMP1]])
 ; CHECK-NEXT:    call void @llvm.stackrestore(i8* [[SAVEDSTACK]])
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
 entry:

 ; CHECK-NEXT:    [[SAVEDSTACK:%.*]] = call i8* @llvm.stacksave()
 ; CHECK-NEXT:    [[CMP_I:%.*]] = icmp ult i32 [[SIZE:%.*]], 100
 ; CHECK-NEXT:    [[CONV_I:%.*]] = zext i32 [[SIZE]] to i64
 ; CHECK-NEXT:    br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]
 ; CHECK:       if.then.i:
 ; CHECK-NEXT:    [[TMP0:%.*]] = alloca i8, i64 [[CONV_I]], align 8
 ; CHECK-NEXT:    br label [[STACK_ALLOCATE_EXIT:%.*]]
 ; CHECK:       if.end.i:
-; CHECK-NEXT:    [[CALL_I:%.*]] = tail call i8* @malloc(i64 [[CONV_I]]) #2
+; CHECK-NEXT:    [[CALL_I:%.*]] = tail call i8* @malloc(i64 [[CONV_I]]) #3
 ; CHECK-NEXT:    br label [[STACK_ALLOCATE_EXIT]]
 ; CHECK:       stack_allocate.exit:
 ; CHECK-NEXT:    [[RETVAL_0_I:%.*]] = phi i8* [ [[TMP0]], [[IF_THEN_I]] ], [ [[CALL_I]], [[IF_END_I]] ]
 ; CHECK-NEXT:    call void @llvm.stackrestore(i8* [[SAVEDSTACK]])
 ; CHECK-NEXT:    ret i8* [[RETVAL_0_I]]
 ;
 entry:
   %call = tail call i8* @stack_allocate(i32 %size)

llvm/test/Transforms/Inline/inline_invoke.ll

 ; CHECK:    [[FIX]]:
 ; CHECK-NEXT: [[T1:%.*]] = phi i32 [ 0, %[[JOIN]] ], [ 1, %lpad ]
 ; CHECK-NEXT: call void @use(i32 [[T1]])
 ; CHECK-NEXT: call void @_ZSt9terminatev()
 
 ; CHECK: attributes [[NUW]] = { nounwind }
 ; CHECK: attributes #1 = { nounwind readnone }
 ; CHECK: attributes #2 = { ssp uwtable }
-; CHECK: attributes #3 = { argmemonly nounwind willreturn }
+; CHECK: attributes #3 = { argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #4 = { noreturn nounwind }

llvm/test/Transforms/Inline/noalias-calls.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
 ; RUN: opt -basic-aa -inline -enable-noalias-to-md-conversion -S < %s | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #0
 declare void @hey() #0
 
 define void @hello(i8* noalias nocapture %a, i8* noalias nocapture readonly %c, i8* nocapture %b) #1 {

 define void @foo_cs(i8* nocapture %a, i8* nocapture readonly %c, i8* nocapture %b) #2 {
 entry:
   tail call void @hello_cs(i8* noalias %a, i8* noalias %c, i8* %b)
   ret void
 }
 
 ; CHECK: define void @foo(i8* nocapture %a, i8* nocapture readonly %c, i8* nocapture %b) #2 {
 ; CHECK: entry:
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #1, !noalias !0
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #1, !noalias !3
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #1, !alias.scope !5
-; CHECK:   call void @hey() #1, !noalias !5
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #1, !noalias !3
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #2, !noalias !0
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #2, !noalias !3
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #2, !alias.scope !5
+; CHECK:   call void @hey() #2, !noalias !5
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #2, !noalias !3
 ; CHECK:   ret void
 ; CHECK: }
 
 ; CHECK: define void @foo_cs(i8* nocapture %a, i8* nocapture readonly %c, i8* nocapture %b) #2 {
 ; CHECK: entry:
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #1, !noalias !6
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #1, !noalias !9
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #1, !alias.scope !11
-; CHECK:   call void @hey() #1, !noalias !11
-; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #1, !noalias !9
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #2, !noalias !6
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #2, !noalias !9
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #2, !alias.scope !11
+; CHECK:   call void @hey() #2, !noalias !11
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #2, !noalias !9
 ; CHECK:   ret void
 ; CHECK: }
 
-attributes #0 = { nounwind argmemonly willreturn }
-attributes #1 = { nounwind }
-attributes #2 = { nounwind uwtable }
+attributes #0 = { argmemonly nofree nosync nounwind willreturn }
+attributes #1 = { argmemonly nounwind willreturn }
+attributes #2 = { nounwind }
+attributes #3 = { nounwind uwtable }
 
 ; CHECK: !0 = !{!1}
 ; CHECK: !1 = distinct !{!1, !2, !"hello: %c"}
 ; CHECK: !2 = distinct !{!2, !"hello"}
 ; CHECK: !3 = !{!4}
 ; CHECK: !4 = distinct !{!4, !2, !"hello: %a"}
 ; CHECK: !5 = !{!4, !1}
 
 ; CHECK: !6 = !{!7}
 ; CHECK: !7 = distinct !{!7, !8, !"hello_cs: %c"}
 ; CHECK: !8 = distinct !{!8, !"hello_cs"}
 ; CHECK: !9 = !{!10}
 ; CHECK: !10 = distinct !{!10, !8, !"hello_cs: %a"}
 ; CHECK: !11 = !{!10, !7}
-

llvm/test/Transforms/InstCombine/sdiv-guard.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 declare void @llvm.experimental.guard(i1, ...)
 
 ; Regression test. If %flag is false then %s == 0 and guard should be triggered.
 define i32 @a(i1 %flag, i32 %X) nounwind readnone {
 ; CHECK-LABEL: @a(
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP1]], [[FLAG:%.*]]
-; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #1 [ "deopt"() ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 0
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #2 [ "deopt"() ]
 ; CHECK-NEXT:    [[R:%.*]] = sdiv i32 100, [[X]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %s = select i1 %flag, i32 %X, i32 0
   %cmp = icmp ne i32 %s, 0
   call void(i1, ...) @llvm.experimental.guard( i1 %cmp )[ "deopt"() ]
   %r = sdiv i32 100, %s
   ret i32 %r
 }

llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll

 ; CHECK-NEXT:    ret <8 x double> [[TMP1]]
 ;
 entry:
   %load = call <8 x double> @llvm.matrix.column.major.load.v8f64(double* %in, i64 %stride, i1 false, i32 4, i32 2)
   ret <8 x double> %load
 }
 
 ; CHECK: declare <9 x double> @llvm.matrix.column.major.load.v9f64(double* nocapture, i64, i1 immarg, i32 immarg, i32 immarg) [[READONLY]]
-; CHECK: attributes [[READONLY]] = { argmemonly nosync nounwind readonly willreturn }
+; CHECK: attributes [[READONLY]] = { argmemonly nofree nosync nounwind readonly willreturn }

llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll

 ;
   call void @llvm.matrix.column.major.store.v10f64(<10 x double> %in, double* %out, i64 4, i1 false, i32 2, i32 5)
   ret void
 }
 
 declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double*, i64, i1, i32, i32)
 declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double*, i64, i1, i32, i32)
 
-; CHECK: declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 
-; CHECK: declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 
-; CHECK: attributes #0 = { argmemonly nosync nounwind willreturn writeonly }
+; CHECK: declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0
+; CHECK: declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0
+; CHECK: attributes #0 = { argmemonly nofree nosync nounwind willreturn writeonly }

llvm/test/Transforms/MemCpyOpt/memcpy.ll

 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
 declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture, i8* nocapture, i64, i1) nounwind
 
 declare void @f1(%struct.big* nocapture sret)
 declare void @f2(%struct.big*)
 
 ; CHECK: attributes [[ATTR0]] = { nounwind }
-; CHECK: attributes #1 = { argmemonly nounwind willreturn }
+; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn }
 ; CHECK: attributes #2 = { nounwind ssp }
 ; CHECK: attributes #3 = { nounwind ssp uwtable }
+; CHECK: attributes #4 = { argmemonly nofree nosync nounwind willreturn writeonly }

llvm/test/Transforms/ObjCARC/basic.ll

 !3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang",
                              file: !4,
                              isOptimized: true, flags: "-O2",
                              splitDebugFilename: "abc.debug", emissionKind: 2)
 !4 = !DIFile(filename: "path/to/file", directory: "/path/to/dir")
 !5 = !{i32 2, !"Debug Info Version", i32 3}
 
 ; CHECK: attributes [[NUW]] = { nounwind }
-; CHECK: attributes #1 = { nounwind readnone speculatable willreturn }
+; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
 ; CHECK: ![[RELEASE]] = !{}

llvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll

 
 declare void @llvm.objc.release(i8*) nonlazybind
 
 declare void @NSLog(i8*, ...)
 
 declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone
 
 ; CHECK: attributes #0 = { ssp uwtable }
-; CHECK: attributes #1 = { nounwind readnone speculatable willreturn }
+; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
 ; CHECK: attributes #2 = { nonlazybind }
 ; CHECK: attributes [[NUW]] = { nounwind }
 ; CHECK: attributes #4 = { noinline ssp uwtable }
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33, !34, !35, !36, !61}
 
 !0 = distinct !DICompileUnit(language: DW_LANG_ObjC, producer: "clang version 3.3 ", isOptimized: true, runtimeVersion: 2, emissionKind: FullDebug, file: !60, enums: !1, retainedTypes: !1, globals: !1)

llvm/test/Transforms/ObjCARC/nested.ll

entry:
   %strongdestroy25 = load i8*, i8** %foo10, align 8
   call void @llvm.objc.release(i8* %strongdestroy25) nounwind, !clang.imprecise_release !0
   call void @llvm.objc.release(i8* %call) nounwind, !clang.imprecise_release !0
   ret void
 }
 
 
 ; CHECK: attributes [[NUW]] = { nounwind }
-; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly }
+; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }
 ; CHECK: attributes #2 = { nonlazybind }

llvm/test/Transforms/SLPVectorizer/X86/call.ll

 }
 
 
 ; CHECK: declare <2 x double> @llvm.sin.v2f64(<2 x double>) [[ATTR0:#[0-9]+]]
 ; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) [[ATTR0]]
 ; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) [[ATTR0]]
 ; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) [[ATTR0]]
 
-; CHECK: attributes [[ATTR0]] = { nounwind readnone speculatable willreturn }
+; CHECK: attributes [[ATTR0]] = { nofree nosync nounwind readnone speculatable willreturn }
 

llvm/test/Verifier/fp-intrinsics.ll

 ; RUN: opt -verify -S < %s 2>&1 | FileCheck --check-prefix=CHECK1 %s
 ; RUN: sed -e s/.T2:// %s | not opt -verify -disable-output 2>&1 | FileCheck --check-prefix=CHECK2 %s
 ; RUN: sed -e s/.T3:// %s | not opt -verify -disable-output 2>&1 | FileCheck --check-prefix=CHECK3 %s
 ; RUN: sed -e s/.T4:// %s | not opt -verify -disable-output 2>&1 | FileCheck --check-prefix=CHECK4 %s
 ; RUN: sed -e s/.T5:// %s | not opt -verify -disable-output 2>&1 | FileCheck --check-prefix=CHECK5 %s
 
 ; Common declarations used for all runs.
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
 
 ; Test that the verifier accepts legal code, and that the correct attributes are
 ; attached to the FP intrinsic.
 ; CHECK1: declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata) #[[ATTR:[0-9]+]]
 ; CHECK1: declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata) #[[ATTR]]
-; CHECK1: attributes #[[ATTR]] = { inaccessiblememonly nounwind willreturn }
+; CHECK1: attributes #[[ATTR]] = { inaccessiblememonly nofree nosync nounwind willreturn }
 ; Note: FP exceptions aren't usually caught through normal unwind mechanisms,
 ;       but we may want to revisit this for asynchronous exception handling.
 define double @f1(double %a, double %b) #0 {
 entry:
   %fadd = call double @llvm.experimental.constrained.fadd.f64(
                                                double %a, double %b,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0