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Differential D85385

[X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics.
ClosedPublic

Authored by pengfei on Aug 5 2020, 5:50 PM.

Details

Reviewers
craig.topper
RKSimon
andrew.w.kaylor
uweigand
kpn
Commits
rG951252594702: [X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics.
Summary

When we use mask compare intrinsics under strict FP option, the masked
elements shouldn't raise any exception. So, we cann't replace the
intrinsic with a full compare + "and" operation.

Diff Detail

Unit TestsFailed

TimeTest
80 mslinux > Polly.Isl/Ast::alias_checks_with_empty_context.ll

Event Timeline

pengfei created this revision.Aug 5 2020, 5:50 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptAug 5 2020, 5:50 PM
Herald added subscribers: llvm-commits, cfe-commits, hiraditya. · View Herald Transcript
pengfei requested review of this revision.Aug 5 2020, 5:50 PM
Harbormaster completed remote builds in B67234: Diff 283458.Aug 5 2020, 6:09 PM
pengfei added a comment.Aug 10 2020, 5:19 PM

Ping.

craig.topper added inline comments.Aug 10 2020, 5:43 PM
clang/test/CodeGen/avx512f-builtins-constrained-cmp.c
793

I missed this in our internal review. All of these check lines check "#2" at the end, do we need that?

llvm/lib/IR/AutoUpgrade.cpp
3764

Can we use getX86MaskVec here?

pengfei updated this revision to Diff 284547.Aug 10 2020, 6:41 PM
pengfei marked 2 inline comments as done.

Address review comments.

pengfei added inline comments.Aug 10 2020, 6:42 PM
clang/test/CodeGen/avx512f-builtins-constrained-cmp.c
793

No. I forgot to remove them. Thank you.

llvm/lib/IR/AutoUpgrade.cpp
3764

Sure. It's more clean now. Thanks.

craig.topper accepted this revision.Aug 10 2020, 6:58 PM

LGTM

This revision is now accepted and ready to land.Aug 10 2020, 6:58 PM
Harbormaster completed remote builds in B67827: Diff 284547.Aug 10 2020, 7:10 PM
This revision was landed with ongoing or failed builds.Aug 10 2020, 7:28 PM
Closed by commit rG951252594702: [X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics. (authored by Wang, Pengfei <pengfei.wang@intel.com>). · Explain Why
This revision was automatically updated to reflect the committed changes.
pengfei added a commit: rG951252594702: [X86][FPEnv] Teach X86 mask compare intrinsics to respect strict FP semantics..

Revision Contents

Diff 284547

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===// //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 11,749 Lines • ▼ Show 20 LinesValue *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
if (BuiltinID == X86::BI__builtin_cpu_is) if (BuiltinID == X86::BI__builtin_cpu_is)
return EmitX86CpuIs(E); return EmitX86CpuIs(E);
if (BuiltinID == X86::BI__builtin_cpu_supports) if (BuiltinID == X86::BI__builtin_cpu_supports)
return EmitX86CpuSupports(E); return EmitX86CpuSupports(E);
if (BuiltinID == X86::BI__builtin_cpu_init) if (BuiltinID == X86::BI__builtin_cpu_init)
return EmitX86CpuInit(); return EmitX86CpuInit();
SmallVector<Value*, 4> Ops; SmallVector<Value*, 4> Ops;
bool IsMaskFCmp = false;
// Find out if any arguments are required to be integer constant expressions. // Find out if any arguments are required to be integer constant expressions.
unsigned ICEArguments = 0; unsigned ICEArguments = 0;
ASTContext::GetBuiltinTypeError Error; ASTContext::GetBuiltinTypeError Error;
getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments); getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
assert(Error == ASTContext::GE_None && "Should not codegen an error"); assert(Error == ASTContext::GE_None && "Should not codegen an error");
for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) { for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
▲ Show 20 Lines • Show All 1,882 Lines • ▼ Show 20 Lines
case X86::BI__builtin_ia32_cmpnltpd: case X86::BI__builtin_ia32_cmpnltpd:
return getVectorFCmpIR(CmpInst::FCMP_UGE, /*IsSignaling*/true); return getVectorFCmpIR(CmpInst::FCMP_UGE, /*IsSignaling*/true);
case X86::BI__builtin_ia32_cmpnleps: case X86::BI__builtin_ia32_cmpnleps:
case X86::BI__builtin_ia32_cmpnlepd: case X86::BI__builtin_ia32_cmpnlepd:
return getVectorFCmpIR(CmpInst::FCMP_UGT, /*IsSignaling*/true); return getVectorFCmpIR(CmpInst::FCMP_UGT, /*IsSignaling*/true);
case X86::BI__builtin_ia32_cmpordps: case X86::BI__builtin_ia32_cmpordps:
case X86::BI__builtin_ia32_cmpordpd: case X86::BI__builtin_ia32_cmpordpd:
return getVectorFCmpIR(CmpInst::FCMP_ORD, /*IsSignaling*/false); return getVectorFCmpIR(CmpInst::FCMP_ORD, /*IsSignaling*/false);
case X86::BI__builtin_ia32_cmpps:
case X86::BI__builtin_ia32_cmpps256:
case X86::BI__builtin_ia32_cmppd:
case X86::BI__builtin_ia32_cmppd256:
case X86::BI__builtin_ia32_cmpps128_mask: case X86::BI__builtin_ia32_cmpps128_mask:
case X86::BI__builtin_ia32_cmpps256_mask: case X86::BI__builtin_ia32_cmpps256_mask:
case X86::BI__builtin_ia32_cmpps512_mask: case X86::BI__builtin_ia32_cmpps512_mask:
case X86::BI__builtin_ia32_cmppd128_mask: case X86::BI__builtin_ia32_cmppd128_mask:
case X86::BI__builtin_ia32_cmppd256_mask: case X86::BI__builtin_ia32_cmppd256_mask:
case X86::BI__builtin_ia32_cmppd512_mask: { case X86::BI__builtin_ia32_cmppd512_mask:
IsMaskFCmp = true;
LLVM_FALLTHROUGH;
case X86::BI__builtin_ia32_cmpps:
case X86::BI__builtin_ia32_cmpps256:
case X86::BI__builtin_ia32_cmppd:
case X86::BI__builtin_ia32_cmppd256: {
// Lowering vector comparisons to fcmp instructions, while // Lowering vector comparisons to fcmp instructions, while
// ignoring signalling behaviour requested // ignoring signalling behaviour requested
// ignoring rounding mode requested // ignoring rounding mode requested
// This is is only possible as long as FENV_ACCESS is not implemented. // This is is only possible as long as FENV_ACCESS is not implemented.
// See also: https://reviews.llvm.org/D45616 // See also: https://reviews.llvm.org/D45616
// The third argument is the comparison condition, and integer in the // The third argument is the comparison condition, and integer in the
// range [0, 31] // range [0, 31]
Show All 28 Lines case X86::BI__builtin_ia32_cmppd256: {
// Invert the signalling behavior for 16-31. // Invert the signalling behavior for 16-31.
if (CC & 0x10) if (CC & 0x10)
IsSignaling = !IsSignaling; IsSignaling = !IsSignaling;
// If the predicate is true or false and we're using constrained intrinsics, // If the predicate is true or false and we're using constrained intrinsics,
// we don't have a compare intrinsic we can use. Just use the legacy X86 // we don't have a compare intrinsic we can use. Just use the legacy X86
// specific intrinsic. // specific intrinsic.
if ((Pred == FCmpInst::FCMP_TRUE || Pred == FCmpInst::FCMP_FALSE) && // If the intrinsic is mask enabled and we're using constrained intrinsics,
Builder.getIsFPConstrained()) { // use the legacy X86 specific intrinsic.
if (Builder.getIsFPConstrained() &&
(Pred == FCmpInst::FCMP_TRUE || Pred == FCmpInst::FCMP_FALSE ||
IsMaskFCmp)) {
Intrinsic::ID IID; Intrinsic::ID IID;
switch (BuiltinID) { switch (BuiltinID) {
default: llvm_unreachable("Unexpected builtin"); default: llvm_unreachable("Unexpected builtin");
case X86::BI__builtin_ia32_cmpps: case X86::BI__builtin_ia32_cmpps:
IID = Intrinsic::x86_sse_cmp_ps; IID = Intrinsic::x86_sse_cmp_ps;
break; break;
case X86::BI__builtin_ia32_cmpps256: case X86::BI__builtin_ia32_cmpps256:
IID = Intrinsic::x86_avx_cmp_ps_256; IID = Intrinsic::x86_avx_cmp_ps_256;
break; break;
case X86::BI__builtin_ia32_cmppd: case X86::BI__builtin_ia32_cmppd:
IID = Intrinsic::x86_sse2_cmp_pd; IID = Intrinsic::x86_sse2_cmp_pd;
break; break;
case X86::BI__builtin_ia32_cmppd256: case X86::BI__builtin_ia32_cmppd256:
IID = Intrinsic::x86_avx_cmp_pd_256; IID = Intrinsic::x86_avx_cmp_pd_256;
break; break;
case X86::BI__builtin_ia32_cmpps512_mask: case X86::BI__builtin_ia32_cmpps512_mask:
IID = Intrinsic::x86_avx512_cmp_ps_512; IID = Intrinsic::x86_avx512_mask_cmp_ps_512;
break; break;
case X86::BI__builtin_ia32_cmppd512_mask: case X86::BI__builtin_ia32_cmppd512_mask:
IID = Intrinsic::x86_avx512_cmp_pd_512; IID = Intrinsic::x86_avx512_mask_cmp_pd_512;
break; break;
case X86::BI__builtin_ia32_cmpps128_mask: case X86::BI__builtin_ia32_cmpps128_mask:
IID = Intrinsic::x86_avx512_cmp_ps_128; IID = Intrinsic::x86_avx512_mask_cmp_ps_128;
break; break;
case X86::BI__builtin_ia32_cmpps256_mask: case X86::BI__builtin_ia32_cmpps256_mask:
IID = Intrinsic::x86_avx512_cmp_ps_256; IID = Intrinsic::x86_avx512_mask_cmp_ps_256;
break; break;
case X86::BI__builtin_ia32_cmppd128_mask: case X86::BI__builtin_ia32_cmppd128_mask:
IID = Intrinsic::x86_avx512_cmp_pd_128; IID = Intrinsic::x86_avx512_mask_cmp_pd_128;
break; break;
case X86::BI__builtin_ia32_cmppd256_mask: case X86::BI__builtin_ia32_cmppd256_mask:
IID = Intrinsic::x86_avx512_cmp_pd_256; IID = Intrinsic::x86_avx512_mask_cmp_pd_256;
break; break;
} }
Function *Intr = CGM.getIntrinsic(IID); Function *Intr = CGM.getIntrinsic(IID);
if (cast<llvm::VectorType>(Intr->getReturnType()) if (IsMaskFCmp) {
->getElementType()
->isIntegerTy(1)) {
unsigned NumElts = unsigned NumElts =
cast<llvm::VectorType>(Ops[0]->getType())->getNumElements(); cast<llvm::VectorType>(Ops[0]->getType())->getNumElements();
Value *MaskIn = Ops[3]; Ops[3] = getMaskVecValue(*this, Ops[3], NumElts);
Ops.erase(&Ops[3]);
Value *Cmp = Builder.CreateCall(Intr, Ops); Value *Cmp = Builder.CreateCall(Intr, Ops);
return EmitX86MaskedCompareResult(*this, Cmp, NumElts, MaskIn); return EmitX86MaskedCompareResult(*this, Cmp, NumElts, nullptr);
} }
return Builder.CreateCall(Intr, Ops); return Builder.CreateCall(Intr, Ops);
} }
// Builtins without the _mask suffix return a vector of integers // Builtins without the _mask suffix return a vector of integers
// of the same width as the input vectors // of the same width as the input vectors
switch (BuiltinID) { if (IsMaskFCmp) {
case X86::BI__builtin_ia32_cmpps512_mask: // We ignore SAE if strict FP is disabled. We only keep precise
case X86::BI__builtin_ia32_cmppd512_mask: // exception behavior under strict FP.
case X86::BI__builtin_ia32_cmpps128_mask:
case X86::BI__builtin_ia32_cmpps256_mask:
case X86::BI__builtin_ia32_cmppd128_mask:
case X86::BI__builtin_ia32_cmppd256_mask: {
// FIXME: Support SAE.
unsigned NumElts = unsigned NumElts =
cast<llvm::VectorType>(Ops[0]->getType())->getNumElements(); cast<llvm::VectorType>(Ops[0]->getType())->getNumElements();
Value *Cmp; Value *Cmp;
if (IsSignaling) if (IsSignaling)
Cmp = Builder.CreateFCmpS(Pred, Ops[0], Ops[1]); Cmp = Builder.CreateFCmpS(Pred, Ops[0], Ops[1]);
else else
Cmp = Builder.CreateFCmp(Pred, Ops[0], Ops[1]); Cmp = Builder.CreateFCmp(Pred, Ops[0], Ops[1]);
return EmitX86MaskedCompareResult(*this, Cmp, NumElts, Ops[3]); return EmitX86MaskedCompareResult(*this, Cmp, NumElts, Ops[3]);
} }
default:
return getVectorFCmpIR(Pred, IsSignaling); return getVectorFCmpIR(Pred, IsSignaling);
} }
}
// SSE scalar comparison intrinsics // SSE scalar comparison intrinsics
case X86::BI__builtin_ia32_cmpeqss: case X86::BI__builtin_ia32_cmpeqss:
return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 0); return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 0);
case X86::BI__builtin_ia32_cmpltss: case X86::BI__builtin_ia32_cmpltss:
return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 1); return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 1);
case X86::BI__builtin_ia32_cmpless: case X86::BI__builtin_ia32_cmpless:
return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 2); return getCmpIntrinsicCall(Intrinsic::x86_sse_cmp_ss, 2);
▲ Show 20 Lines • Show All 2,976 Lines • Show Last 20 Lines

clang/test/CodeGen/avx512f-builtins-constrained-cmp.c

// RUN: %clang_cc1 -fexperimental-new-pass-manager -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -fexperimental-new-pass-manager -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s
#include <immintrin.h> #include <immintrin.h>
__mmask16 test_mm512_cmp_round_ps_mask(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_round_ps_mask(__m512 a, __m512 b) {
// CHECK-LABEL: @test_mm512_cmp_round_ps_mask // CHECK-LABEL: @test_mm512_cmp_round_ps_mask
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 0, <16 x i1> {{.*}}, i32 8)
return _mm512_cmp_round_ps_mask(a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC); return _mm512_cmp_round_ps_mask(a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC);
} }
__mmask16 test_mm512_mask_cmp_round_ps_mask(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_round_ps_mask(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: @test_mm512_mask_cmp_round_ps_mask // CHECK-LABEL: @test_mm512_mask_cmp_round_ps_mask
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 0, <16 x i1> {{.*}}, i32 8)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_round_ps_mask(m, a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC); return _mm512_mask_cmp_round_ps_mask(m, a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC);
} }
__mmask16 test_mm512_cmp_ps_mask_eq_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_eq_oq(__m512 a, __m512 b) {
// CHECK-LABEL: @test_mm512_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm512_cmp_ps_mask_eq_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 0, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_EQ_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_EQ_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_lt_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_lt_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm512_cmp_ps_mask_lt_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 1, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_LT_OS); return _mm512_cmp_ps_mask(a, b, _CMP_LT_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_le_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_le_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_le_os // CHECK-LABEL: test_mm512_cmp_ps_mask_le_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 2, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_LE_OS); return _mm512_cmp_ps_mask(a, b, _CMP_LE_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_unord_q(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_unord_q(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm512_cmp_ps_mask_unord_q
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 3, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_UNORD_Q); return _mm512_cmp_ps_mask(a, b, _CMP_UNORD_Q);
} }
__mmask16 test_mm512_cmp_ps_mask_neq_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_neq_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_neq_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 4, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_nlt_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nlt_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm512_cmp_ps_mask_nlt_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 5, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NLT_US); return _mm512_cmp_ps_mask(a, b, _CMP_NLT_US);
} }
__mmask16 test_mm512_cmp_ps_mask_nle_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nle_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm512_cmp_ps_mask_nle_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 6, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NLE_US); return _mm512_cmp_ps_mask(a, b, _CMP_NLE_US);
} }
__mmask16 test_mm512_cmp_ps_mask_ord_q(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ord_q(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm512_cmp_ps_mask_ord_q
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 7, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_ORD_Q); return _mm512_cmp_ps_mask(a, b, _CMP_ORD_Q);
} }
__mmask16 test_mm512_cmp_ps_mask_eq_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_eq_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_eq_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 8, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_EQ_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_EQ_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_nge_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nge_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm512_cmp_ps_mask_nge_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 9, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NGE_US); return _mm512_cmp_ps_mask(a, b, _CMP_NGE_US);
} }
__mmask16 test_mm512_cmp_ps_mask_ngt_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ngt_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm512_cmp_ps_mask_ngt_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 10, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NGT_US); return _mm512_cmp_ps_mask(a, b, _CMP_NGT_US);
} }
__mmask16 test_mm512_cmp_ps_mask_false_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_false_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_false_oq
// CHECK: call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 11, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 11, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_FALSE_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_neq_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_neq_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_neq_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 12, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_ge_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ge_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm512_cmp_ps_mask_ge_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 13, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_GE_OS); return _mm512_cmp_ps_mask(a, b, _CMP_GE_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_gt_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_gt_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm512_cmp_ps_mask_gt_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 14, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_GT_OS); return _mm512_cmp_ps_mask(a, b, _CMP_GT_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_true_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_true_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_true_uq
// CHECK: call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 15, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 15, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_TRUE_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_eq_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_eq_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm512_cmp_ps_mask_eq_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 16, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_EQ_OS); return _mm512_cmp_ps_mask(a, b, _CMP_EQ_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_lt_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_lt_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_lt_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 17, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_LT_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_LT_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_le_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_le_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_le_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 18, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_LE_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_LE_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_unord_s(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_unord_s(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm512_cmp_ps_mask_unord_s
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 19, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_UNORD_S); return _mm512_cmp_ps_mask(a, b, _CMP_UNORD_S);
} }
__mmask16 test_mm512_cmp_ps_mask_neq_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_neq_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm512_cmp_ps_mask_neq_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 20, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_US); return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_US);
} }
__mmask16 test_mm512_cmp_ps_mask_nlt_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nlt_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_nlt_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 21, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NLT_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_NLT_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_nle_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nle_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_nle_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 22, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NLE_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_NLE_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_ord_s(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ord_s(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm512_cmp_ps_mask_ord_s
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 23, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_ORD_S); return _mm512_cmp_ps_mask(a, b, _CMP_ORD_S);
} }
__mmask16 test_mm512_cmp_ps_mask_eq_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_eq_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm512_cmp_ps_mask_eq_us
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 24, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_EQ_US); return _mm512_cmp_ps_mask(a, b, _CMP_EQ_US);
} }
__mmask16 test_mm512_cmp_ps_mask_nge_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_nge_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_nge_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 25, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NGE_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_NGE_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_ngt_uq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ngt_uq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm512_cmp_ps_mask_ngt_uq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 26, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NGT_UQ); return _mm512_cmp_ps_mask(a, b, _CMP_NGT_UQ);
} }
__mmask16 test_mm512_cmp_ps_mask_false_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_false_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_false_os // CHECK-LABEL: test_mm512_cmp_ps_mask_false_os
// CHECK: call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 27, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 27, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_FALSE_OS); return _mm512_cmp_ps_mask(a, b, _CMP_FALSE_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_neq_os(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_neq_os(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm512_cmp_ps_mask_neq_os
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 28, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_OS); return _mm512_cmp_ps_mask(a, b, _CMP_NEQ_OS);
} }
__mmask16 test_mm512_cmp_ps_mask_ge_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_ge_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_ge_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 29, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_GE_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_GE_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_gt_oq(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_gt_oq(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm512_cmp_ps_mask_gt_oq
// CHECK: call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 30, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_GT_OQ); return _mm512_cmp_ps_mask(a, b, _CMP_GT_OQ);
} }
__mmask16 test_mm512_cmp_ps_mask_true_us(__m512 a, __m512 b) { __mmask16 test_mm512_cmp_ps_mask_true_us(__m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_cmp_ps_mask_true_us // CHECK-LABEL: test_mm512_cmp_ps_mask_true_us
// CHECK: call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 31, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 31, <16 x i1> {{.*}}, i32 4)
return _mm512_cmp_ps_mask(a, b, _CMP_TRUE_US); return _mm512_cmp_ps_mask(a, b, _CMP_TRUE_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_eq_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_eq_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: @test_mm512_mask_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm512_mask_cmp_ps_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 0, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_lt_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_lt_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_lt_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 1, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_le_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_le_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_le_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_le_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 2, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_unord_q(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_unord_q(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_unord_q
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 3, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_neq_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_neq_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 4, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nlt_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nlt_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 5, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nle_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nle_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nle_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 6, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ord_q(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ord_q(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ord_q
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 7, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_eq_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_eq_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 8, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nge_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nge_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nge_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 9, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ngt_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ngt_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 10, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_false_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_false_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_false_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 11, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 11, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_neq_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_neq_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 12, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ge_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ge_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ge_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 13, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_gt_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_gt_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_gt_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 14, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_true_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_true_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_true_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 15, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 15, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_eq_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_eq_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 16, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_lt_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_lt_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 17, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_le_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_le_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_le_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 18, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_unord_s(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_unord_s(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_unord_s
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 19, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_neq_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_neq_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 20, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nlt_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nlt_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 21, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nle_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nle_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 22, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ord_s(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ord_s(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ord_s
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 23, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_eq_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_eq_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_eq_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 24, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_nge_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_nge_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 25, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ngt_uq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ngt_uq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 26, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_false_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_false_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_false_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_false_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 27, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 27, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_neq_os(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_neq_os(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_neq_os
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 28, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_ge_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_ge_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 29, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_gt_oq(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_gt_oq(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 30, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask16 test_mm512_mask_cmp_ps_mask_true_us(__mmask16 m, __m512 a, __m512 b) { __mmask16 test_mm512_mask_cmp_ps_mask_true_us(__mmask16 m, __m512 a, __m512 b) {
// CHECK-LABEL: test_mm512_mask_cmp_ps_mask_true_us // CHECK-LABEL: test_mm512_mask_cmp_ps_mask_true_us
// CHECK: [[CMP:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 31, i32 4) // CHECK: call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %{{.*}}, <16 x float> %{{.*}}, i32 31, <16 x i1> {{.*}}, i32 4)
// CHECK: and <16 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US); return _mm512_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm512_cmp_round_pd_mask(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_round_pd_mask(__m512d a, __m512d b) {
// CHECK-LABEL: @test_mm512_cmp_round_pd_mask // CHECK-LABEL: @test_mm512_cmp_round_pd_mask
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 0, <8 x i1> {{.*}}, i32 8)
return _mm512_cmp_round_pd_mask(a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC); return _mm512_cmp_round_pd_mask(a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC);
} }
__mmask8 test_mm512_mask_cmp_round_pd_mask(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_round_pd_mask(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: @test_mm512_mask_cmp_round_pd_mask // CHECK-LABEL: @test_mm512_mask_cmp_round_pd_mask
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 0, <8 x i1> {{.*}}, i32 8)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_round_pd_mask(m, a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC); return _mm512_mask_cmp_round_pd_mask(m, a, b, _CMP_EQ_OQ, _MM_FROUND_NO_EXC);
} }
__mmask8 test_mm512_cmp_pd_mask_eq_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_eq_oq(__m512d a, __m512d b) {
// CHECK-LABEL: @test_mm512_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm512_cmp_pd_mask_eq_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 0, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_EQ_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_lt_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_lt_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm512_cmp_pd_mask_lt_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 1, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_LT_OS); return _mm512_cmp_pd_mask(a, b, _CMP_LT_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_le_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_le_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_le_os // CHECK-LABEL: test_mm512_cmp_pd_mask_le_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 2, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_LE_OS); return _mm512_cmp_pd_mask(a, b, _CMP_LE_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_unord_q(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_unord_q(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm512_cmp_pd_mask_unord_q
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 3, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_UNORD_Q); return _mm512_cmp_pd_mask(a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm512_cmp_pd_mask_neq_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_neq_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_neq_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 4, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_nlt_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nlt_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm512_cmp_pd_mask_nlt_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 5, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NLT_US); return _mm512_cmp_pd_mask(a, b, _CMP_NLT_US);
} }
__mmask8 test_mm512_cmp_pd_mask_nle_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nle_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm512_cmp_pd_mask_nle_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 6, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NLE_US); return _mm512_cmp_pd_mask(a, b, _CMP_NLE_US);
} }
__mmask8 test_mm512_cmp_pd_mask_ord_q(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ord_q(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm512_cmp_pd_mask_ord_q
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 7, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_ORD_Q); return _mm512_cmp_pd_mask(a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm512_cmp_pd_mask_eq_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_eq_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_eq_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 8, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_EQ_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_nge_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nge_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm512_cmp_pd_mask_nge_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 9, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NGE_US); return _mm512_cmp_pd_mask(a, b, _CMP_NGE_US);
} }
__mmask8 test_mm512_cmp_pd_mask_ngt_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ngt_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm512_cmp_pd_mask_ngt_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 10, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NGT_US); return _mm512_cmp_pd_mask(a, b, _CMP_NGT_US);
} }
__mmask8 test_mm512_cmp_pd_mask_false_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_false_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_false_oq
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 11, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 11, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_FALSE_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_neq_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_neq_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_neq_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 12, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_ge_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ge_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm512_cmp_pd_mask_ge_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 13, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_GE_OS); return _mm512_cmp_pd_mask(a, b, _CMP_GE_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_gt_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_gt_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm512_cmp_pd_mask_gt_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 14, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_GT_OS); return _mm512_cmp_pd_mask(a, b, _CMP_GT_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_true_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_true_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_true_uq
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 15, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 15, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_TRUE_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_eq_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_eq_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm512_cmp_pd_mask_eq_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 16, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_EQ_OS); return _mm512_cmp_pd_mask(a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_lt_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_lt_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_lt_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 17, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_LT_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_le_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_le_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_le_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 18, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_LE_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_unord_s(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_unord_s(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm512_cmp_pd_mask_unord_s
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 19, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_UNORD_S); return _mm512_cmp_pd_mask(a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm512_cmp_pd_mask_neq_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_neq_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm512_cmp_pd_mask_neq_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 20, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_US); return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm512_cmp_pd_mask_nlt_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nlt_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_nlt_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 21, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NLT_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_nle_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nle_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_nle_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 22, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NLE_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_ord_s(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ord_s(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm512_cmp_pd_mask_ord_s
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 23, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_ORD_S); return _mm512_cmp_pd_mask(a, b, _CMP_ORD_S);
} }
__mmask8 test_mm512_cmp_pd_mask_eq_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_eq_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm512_cmp_pd_mask_eq_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 24, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_EQ_US); return _mm512_cmp_pd_mask(a, b, _CMP_EQ_US);
} }
__mmask8 test_mm512_cmp_pd_mask_nge_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_nge_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_nge_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 25, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NGE_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_ngt_uq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ngt_uq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm512_cmp_pd_mask_ngt_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 26, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NGT_UQ); return _mm512_cmp_pd_mask(a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm512_cmp_pd_mask_false_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_false_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_false_os // CHECK-LABEL: test_mm512_cmp_pd_mask_false_os
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 27, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 27, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_FALSE_OS); return _mm512_cmp_pd_mask(a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_neq_os(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_neq_os(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm512_cmp_pd_mask_neq_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 28, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_OS); return _mm512_cmp_pd_mask(a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm512_cmp_pd_mask_ge_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_ge_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_ge_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 29, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_GE_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_gt_oq(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_gt_oq(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm512_cmp_pd_mask_gt_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 30, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_GT_OQ); return _mm512_cmp_pd_mask(a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm512_cmp_pd_mask_true_us(__m512d a, __m512d b) { __mmask8 test_mm512_cmp_pd_mask_true_us(__m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_cmp_pd_mask_true_us // CHECK-LABEL: test_mm512_cmp_pd_mask_true_us
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 31, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 31, <8 x i1> {{.*}}, i32 4)
return _mm512_cmp_pd_mask(a, b, _CMP_TRUE_US); return _mm512_cmp_pd_mask(a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: @test_mm512_mask_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm512_mask_cmp_pd_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 0, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_lt_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_lt_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_lt_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 1, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_le_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_le_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_le_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_le_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 2, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_unord_q(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_unord_q(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_unord_q
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 3, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 4, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 5, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nle_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nle_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nle_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 6, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ord_q(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ord_q(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ord_q
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 7, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 8, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nge_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nge_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nge_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 9, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 10, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_false_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_false_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_false_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 11, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 11, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 12, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ge_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ge_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ge_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 13, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_gt_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_gt_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_gt_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 14, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_true_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_true_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_true_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 15, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 15, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_eq_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_eq_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 16, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 17, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_le_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_le_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_le_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 18, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_unord_s(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_unord_s(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_unord_s
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 19, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_neq_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_neq_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 20, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 21, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 22, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ord_s(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ord_s(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ord_s
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 23, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_eq_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_eq_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_eq_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 24, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 25, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 26, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_false_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_false_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_false_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_false_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 27, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 27, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_neq_os(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_neq_os(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_neq_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 28, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 29, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 30, <8 x i1> {{.*}}, i32 4)
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm512_mask_cmp_pd_mask_true_us(__mmask8 m, __m512d a, __m512d b) { __mmask8 test_mm512_mask_cmp_pd_mask_true_us(__mmask8 m, __m512d a, __m512d b) {
// CHECK-LABEL: test_mm512_mask_cmp_pd_mask_true_us // CHECK-LABEL: test_mm512_mask_cmp_pd_mask_true_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 31, i32 4) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %{{.*}}, <8 x double> %{{.*}}, i32 31, <8 x i1> {{.*}}, i32 4)
craig.topperUnsubmitted
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I missed this in our internal review. All of these check lines check "#2" at the end, do we need that?

craig.topper: I missed this in our internal review. All of these check lines check "#2" at the end, do we…
pengfeiAuthorUnsubmitted
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No. I forgot to remove them. Thank you.

pengfei: No. I forgot to remove them. Thank you.
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US); return _mm512_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US);
} }

clang/test/CodeGen/avx512vl-builtins-constrained-cmp.c

// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -fexperimental-new-pass-manager -triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512vl -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -fexperimental-new-pass-manager -triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512vl -emit-llvm -ffp-exception-behavior=strict -o - -Wall -Werror | FileCheck %s
#include <immintrin.h> #include <immintrin.h>
__mmask8 test_mm256_cmp_ps_mask_eq_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_eq_oq(__m256 a, __m256 b) {
// CHECK-LABEL: @test_mm256_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm256_cmp_ps_mask_eq_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 0, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_EQ_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_lt_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_lt_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm256_cmp_ps_mask_lt_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 1, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_LT_OS); return _mm256_cmp_ps_mask(a, b, _CMP_LT_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_le_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_le_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_le_os // CHECK-LABEL: test_mm256_cmp_ps_mask_le_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 2, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_LE_OS); return _mm256_cmp_ps_mask(a, b, _CMP_LE_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_unord_q(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_unord_q(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm256_cmp_ps_mask_unord_q
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 3, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_UNORD_Q); return _mm256_cmp_ps_mask(a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm256_cmp_ps_mask_neq_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_neq_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_neq_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 4, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_nlt_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nlt_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm256_cmp_ps_mask_nlt_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 5, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NLT_US); return _mm256_cmp_ps_mask(a, b, _CMP_NLT_US);
} }
__mmask8 test_mm256_cmp_ps_mask_nle_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nle_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm256_cmp_ps_mask_nle_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 6, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NLE_US); return _mm256_cmp_ps_mask(a, b, _CMP_NLE_US);
} }
__mmask8 test_mm256_cmp_ps_mask_ord_q(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ord_q(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm256_cmp_ps_mask_ord_q
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 7, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_ORD_Q); return _mm256_cmp_ps_mask(a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm256_cmp_ps_mask_eq_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_eq_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_eq_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 8, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_EQ_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_nge_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nge_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm256_cmp_ps_mask_nge_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 9, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NGE_US); return _mm256_cmp_ps_mask(a, b, _CMP_NGE_US);
} }
__mmask8 test_mm256_cmp_ps_mask_ngt_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ngt_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm256_cmp_ps_mask_ngt_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 10, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NGT_US); return _mm256_cmp_ps_mask(a, b, _CMP_NGT_US);
} }
__mmask8 test_mm256_cmp_ps_mask_false_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_false_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_false_oq
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 11) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 11, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_FALSE_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_neq_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_neq_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_neq_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 12, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_ge_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ge_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm256_cmp_ps_mask_ge_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 13, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_GE_OS); return _mm256_cmp_ps_mask(a, b, _CMP_GE_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_gt_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_gt_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm256_cmp_ps_mask_gt_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 14, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_GT_OS); return _mm256_cmp_ps_mask(a, b, _CMP_GT_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_true_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_true_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_true_uq
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 15) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 15, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_TRUE_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_eq_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_eq_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm256_cmp_ps_mask_eq_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 16, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_EQ_OS); return _mm256_cmp_ps_mask(a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_lt_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_lt_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_lt_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 17, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_LT_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_le_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_le_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_le_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 18, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_LE_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_unord_s(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_unord_s(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm256_cmp_ps_mask_unord_s
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 19, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_UNORD_S); return _mm256_cmp_ps_mask(a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm256_cmp_ps_mask_neq_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_neq_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm256_cmp_ps_mask_neq_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 20, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_US); return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm256_cmp_ps_mask_nlt_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nlt_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_nlt_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 21, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NLT_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_nle_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nle_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_nle_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 22, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NLE_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_ord_s(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ord_s(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm256_cmp_ps_mask_ord_s
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 23, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_ORD_S); return _mm256_cmp_ps_mask(a, b, _CMP_ORD_S);
} }
__mmask8 test_mm256_cmp_ps_mask_eq_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_eq_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm256_cmp_ps_mask_eq_us
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 24, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_EQ_US); return _mm256_cmp_ps_mask(a, b, _CMP_EQ_US);
} }
__mmask8 test_mm256_cmp_ps_mask_nge_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_nge_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_nge_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 25, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NGE_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_ngt_uq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ngt_uq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm256_cmp_ps_mask_ngt_uq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 26, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NGT_UQ); return _mm256_cmp_ps_mask(a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm256_cmp_ps_mask_false_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_false_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_false_os // CHECK-LABEL: test_mm256_cmp_ps_mask_false_os
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 27) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 27, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_FALSE_OS); return _mm256_cmp_ps_mask(a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_neq_os(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_neq_os(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm256_cmp_ps_mask_neq_os
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 28, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_OS); return _mm256_cmp_ps_mask(a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm256_cmp_ps_mask_ge_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_ge_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_ge_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 29, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_GE_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_gt_oq(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_gt_oq(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm256_cmp_ps_mask_gt_oq
// CHECK: call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 30, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_GT_OQ); return _mm256_cmp_ps_mask(a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm256_cmp_ps_mask_true_us(__m256 a, __m256 b) { __mmask8 test_mm256_cmp_ps_mask_true_us(__m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_cmp_ps_mask_true_us // CHECK-LABEL: test_mm256_cmp_ps_mask_true_us
// CHECK: call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 31) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 31, <8 x i1> {{.*}})
return _mm256_cmp_ps_mask(a, b, _CMP_TRUE_US); return _mm256_cmp_ps_mask(a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_eq_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_eq_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: @test_mm256_mask_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm256_mask_cmp_ps_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 0, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_lt_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_lt_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_lt_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 1, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_le_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_le_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_le_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_le_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 2, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_unord_q(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_unord_q(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_unord_q
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 3, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_neq_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_neq_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 4, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nlt_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nlt_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 5, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nle_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nle_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nle_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 6, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ord_q(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ord_q(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ord_q
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 7, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_eq_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_eq_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 8, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nge_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nge_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nge_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 9, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ngt_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ngt_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 10, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_false_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_false_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_false_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 11) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 11, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_neq_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_neq_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 12, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ge_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ge_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ge_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 13, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_gt_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_gt_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_gt_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 14, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_true_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_true_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_true_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 15) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 15, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_eq_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_eq_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 16, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_lt_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_lt_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 17, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_le_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_le_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_le_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 18, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_unord_s(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_unord_s(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_unord_s
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 19, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_neq_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_neq_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 20, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nlt_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nlt_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 21, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nle_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nle_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 22, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ord_s(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ord_s(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ord_s
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 23, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_eq_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_eq_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_eq_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 24, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_nge_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_nge_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 25, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ngt_uq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ngt_uq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 26, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_false_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_false_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_false_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_false_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 27) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 27, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_neq_os(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_neq_os(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_neq_os
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 28, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_ge_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_ge_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 29, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_gt_oq(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_gt_oq(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 30, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm256_mask_cmp_ps_mask_true_us(__mmask8 m, __m256 a, __m256 b) { __mmask8 test_mm256_mask_cmp_ps_mask_true_us(__mmask8 m, __m256 a, __m256 b) {
// CHECK-LABEL: test_mm256_mask_cmp_ps_mask_true_us // CHECK-LABEL: test_mm256_mask_cmp_ps_mask_true_us
// CHECK: [[CMP:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 31) // CHECK: call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %{{.*}}, <8 x float> %{{.*}}, i32 31, <8 x i1> {{.*}})
// CHECK: and <8 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US); return _mm256_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm256_cmp_pd_mask_eq_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_eq_oq(__m256d a, __m256d b) {
// CHECK-LABEL: @test_mm256_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm256_cmp_pd_mask_eq_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 0, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_EQ_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_lt_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_lt_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm256_cmp_pd_mask_lt_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 1, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_LT_OS); return _mm256_cmp_pd_mask(a, b, _CMP_LT_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_le_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_le_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_le_os // CHECK-LABEL: test_mm256_cmp_pd_mask_le_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 2, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_LE_OS); return _mm256_cmp_pd_mask(a, b, _CMP_LE_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_unord_q(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_unord_q(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm256_cmp_pd_mask_unord_q
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 3, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_UNORD_Q); return _mm256_cmp_pd_mask(a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm256_cmp_pd_mask_neq_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_neq_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_neq_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 4, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_nlt_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nlt_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm256_cmp_pd_mask_nlt_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 5, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NLT_US); return _mm256_cmp_pd_mask(a, b, _CMP_NLT_US);
} }
__mmask8 test_mm256_cmp_pd_mask_nle_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nle_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm256_cmp_pd_mask_nle_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 6, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NLE_US); return _mm256_cmp_pd_mask(a, b, _CMP_NLE_US);
} }
__mmask8 test_mm256_cmp_pd_mask_ord_q(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ord_q(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm256_cmp_pd_mask_ord_q
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 7, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_ORD_Q); return _mm256_cmp_pd_mask(a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm256_cmp_pd_mask_eq_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_eq_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_eq_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 8, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_EQ_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_nge_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nge_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm256_cmp_pd_mask_nge_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 9, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NGE_US); return _mm256_cmp_pd_mask(a, b, _CMP_NGE_US);
} }
__mmask8 test_mm256_cmp_pd_mask_ngt_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ngt_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm256_cmp_pd_mask_ngt_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 10, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NGT_US); return _mm256_cmp_pd_mask(a, b, _CMP_NGT_US);
} }
__mmask8 test_mm256_cmp_pd_mask_false_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_false_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_false_oq
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 11) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 11, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_FALSE_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_neq_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_neq_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_neq_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 12, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_ge_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ge_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm256_cmp_pd_mask_ge_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 13, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_GE_OS); return _mm256_cmp_pd_mask(a, b, _CMP_GE_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_gt_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_gt_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm256_cmp_pd_mask_gt_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 14, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_GT_OS); return _mm256_cmp_pd_mask(a, b, _CMP_GT_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_true_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_true_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_true_uq
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 15) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 15, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_TRUE_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_eq_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_eq_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm256_cmp_pd_mask_eq_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 16, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_EQ_OS); return _mm256_cmp_pd_mask(a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_lt_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_lt_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_lt_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 17, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_LT_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_le_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_le_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_le_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 18, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_LE_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_unord_s(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_unord_s(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm256_cmp_pd_mask_unord_s
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 19, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_UNORD_S); return _mm256_cmp_pd_mask(a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm256_cmp_pd_mask_neq_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_neq_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm256_cmp_pd_mask_neq_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 20, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_US); return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm256_cmp_pd_mask_nlt_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nlt_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_nlt_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 21, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NLT_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_nle_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nle_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_nle_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 22, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NLE_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_ord_s(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ord_s(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm256_cmp_pd_mask_ord_s
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 23, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_ORD_S); return _mm256_cmp_pd_mask(a, b, _CMP_ORD_S);
} }
__mmask8 test_mm256_cmp_pd_mask_eq_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_eq_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm256_cmp_pd_mask_eq_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 24, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_EQ_US); return _mm256_cmp_pd_mask(a, b, _CMP_EQ_US);
} }
__mmask8 test_mm256_cmp_pd_mask_nge_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_nge_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_nge_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 25, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NGE_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_ngt_uq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ngt_uq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm256_cmp_pd_mask_ngt_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 26, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NGT_UQ); return _mm256_cmp_pd_mask(a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm256_cmp_pd_mask_false_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_false_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_false_os // CHECK-LABEL: test_mm256_cmp_pd_mask_false_os
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 27) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 27, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_FALSE_OS); return _mm256_cmp_pd_mask(a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_neq_os(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_neq_os(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm256_cmp_pd_mask_neq_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 28, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_OS); return _mm256_cmp_pd_mask(a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm256_cmp_pd_mask_ge_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_ge_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_ge_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 29, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_GE_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_gt_oq(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_gt_oq(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm256_cmp_pd_mask_gt_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 30, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_GT_OQ); return _mm256_cmp_pd_mask(a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm256_cmp_pd_mask_true_us(__m256d a, __m256d b) { __mmask8 test_mm256_cmp_pd_mask_true_us(__m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_cmp_pd_mask_true_us // CHECK-LABEL: test_mm256_cmp_pd_mask_true_us
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 31) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 31, <4 x i1> {{.*}})
return _mm256_cmp_pd_mask(a, b, _CMP_TRUE_US); return _mm256_cmp_pd_mask(a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: @test_mm256_mask_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm256_mask_cmp_pd_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 0, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_lt_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_lt_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_lt_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 1, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_le_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_le_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_le_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_le_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 2, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_unord_q(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_unord_q(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_unord_q
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 3, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 4, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 5, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nle_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nle_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nle_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 6, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ord_q(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ord_q(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ord_q
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 7, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 8, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nge_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nge_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nge_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 9, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 10, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_false_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_false_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_false_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 11) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 11, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 12, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ge_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ge_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ge_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 13, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_gt_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_gt_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_gt_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 14, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_true_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_true_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_true_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 15) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 15, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_eq_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_eq_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 16, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 17, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_le_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_le_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_le_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 18, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_unord_s(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_unord_s(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_unord_s
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 19, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_neq_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_neq_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 20, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 21, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 22, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ord_s(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ord_s(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ord_s
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 23, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_eq_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_eq_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_eq_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 24, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 25, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 26, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_false_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_false_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_false_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_false_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 27) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 27, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_neq_os(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_neq_os(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_neq_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 28, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 29, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 30, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm256_mask_cmp_pd_mask_true_us(__mmask8 m, __m256d a, __m256d b) { __mmask8 test_mm256_mask_cmp_pd_mask_true_us(__mmask8 m, __m256d a, __m256d b) {
// CHECK-LABEL: test_mm256_mask_cmp_pd_mask_true_us // CHECK-LABEL: test_mm256_mask_cmp_pd_mask_true_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 31) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %{{.*}}, <4 x double> %{{.*}}, i32 31, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US); return _mm256_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm_cmp_ps_mask_eq_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_eq_oq(__m128 a, __m128 b) {
// CHECK-LABEL: @test_mm_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm_cmp_ps_mask_eq_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 0, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_EQ_OQ); return _mm_cmp_ps_mask(a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_lt_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_lt_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm_cmp_ps_mask_lt_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 1, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_LT_OS); return _mm_cmp_ps_mask(a, b, _CMP_LT_OS);
} }
__mmask8 test_mm_cmp_ps_mask_le_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_le_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_le_os // CHECK-LABEL: test_mm_cmp_ps_mask_le_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 2, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_LE_OS); return _mm_cmp_ps_mask(a, b, _CMP_LE_OS);
} }
__mmask8 test_mm_cmp_ps_mask_unord_q(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_unord_q(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm_cmp_ps_mask_unord_q
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 3, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_UNORD_Q); return _mm_cmp_ps_mask(a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm_cmp_ps_mask_neq_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_neq_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm_cmp_ps_mask_neq_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 4, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NEQ_UQ); return _mm_cmp_ps_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_nlt_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nlt_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm_cmp_ps_mask_nlt_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 5, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NLT_US); return _mm_cmp_ps_mask(a, b, _CMP_NLT_US);
} }
__mmask8 test_mm_cmp_ps_mask_nle_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nle_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm_cmp_ps_mask_nle_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 6, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NLE_US); return _mm_cmp_ps_mask(a, b, _CMP_NLE_US);
} }
__mmask8 test_mm_cmp_ps_mask_ord_q(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ord_q(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm_cmp_ps_mask_ord_q
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 7, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_ORD_Q); return _mm_cmp_ps_mask(a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm_cmp_ps_mask_eq_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_eq_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm_cmp_ps_mask_eq_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 8, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_EQ_UQ); return _mm_cmp_ps_mask(a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_nge_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nge_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm_cmp_ps_mask_nge_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 9, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NGE_US); return _mm_cmp_ps_mask(a, b, _CMP_NGE_US);
} }
__mmask8 test_mm_cmp_ps_mask_ngt_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ngt_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm_cmp_ps_mask_ngt_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 10, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NGT_US); return _mm_cmp_ps_mask(a, b, _CMP_NGT_US);
} }
__mmask8 test_mm_cmp_ps_mask_false_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_false_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm_cmp_ps_mask_false_oq
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 11) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 11, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_FALSE_OQ); return _mm_cmp_ps_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_neq_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_neq_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm_cmp_ps_mask_neq_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 12, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NEQ_OQ); return _mm_cmp_ps_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_ge_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ge_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm_cmp_ps_mask_ge_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 13, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_GE_OS); return _mm_cmp_ps_mask(a, b, _CMP_GE_OS);
} }
__mmask8 test_mm_cmp_ps_mask_gt_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_gt_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm_cmp_ps_mask_gt_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 14, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_GT_OS); return _mm_cmp_ps_mask(a, b, _CMP_GT_OS);
} }
__mmask8 test_mm_cmp_ps_mask_true_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_true_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm_cmp_ps_mask_true_uq
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 15) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 15, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_TRUE_UQ); return _mm_cmp_ps_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_eq_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_eq_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm_cmp_ps_mask_eq_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 16, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_EQ_OS); return _mm_cmp_ps_mask(a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm_cmp_ps_mask_lt_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_lt_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm_cmp_ps_mask_lt_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 17, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_LT_OQ); return _mm_cmp_ps_mask(a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_le_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_le_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm_cmp_ps_mask_le_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 18, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_LE_OQ); return _mm_cmp_ps_mask(a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_unord_s(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_unord_s(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm_cmp_ps_mask_unord_s
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 19, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_UNORD_S); return _mm_cmp_ps_mask(a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm_cmp_ps_mask_neq_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_neq_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm_cmp_ps_mask_neq_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 20, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NEQ_US); return _mm_cmp_ps_mask(a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm_cmp_ps_mask_nlt_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nlt_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm_cmp_ps_mask_nlt_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 21, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NLT_UQ); return _mm_cmp_ps_mask(a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_nle_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nle_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm_cmp_ps_mask_nle_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 22, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NLE_UQ); return _mm_cmp_ps_mask(a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_ord_s(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ord_s(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm_cmp_ps_mask_ord_s
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 23, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_ORD_S); return _mm_cmp_ps_mask(a, b, _CMP_ORD_S);
} }
__mmask8 test_mm_cmp_ps_mask_eq_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_eq_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm_cmp_ps_mask_eq_us
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 24, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_EQ_US); return _mm_cmp_ps_mask(a, b, _CMP_EQ_US);
} }
__mmask8 test_mm_cmp_ps_mask_nge_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_nge_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm_cmp_ps_mask_nge_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 25, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NGE_UQ); return _mm_cmp_ps_mask(a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_ngt_uq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ngt_uq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm_cmp_ps_mask_ngt_uq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 26, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NGT_UQ); return _mm_cmp_ps_mask(a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm_cmp_ps_mask_false_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_false_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_false_os // CHECK-LABEL: test_mm_cmp_ps_mask_false_os
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 27) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 27, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_FALSE_OS); return _mm_cmp_ps_mask(a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm_cmp_ps_mask_neq_os(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_neq_os(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm_cmp_ps_mask_neq_os
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 28, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_NEQ_OS); return _mm_cmp_ps_mask(a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm_cmp_ps_mask_ge_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_ge_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm_cmp_ps_mask_ge_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 29, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_GE_OQ); return _mm_cmp_ps_mask(a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_gt_oq(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_gt_oq(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm_cmp_ps_mask_gt_oq
// CHECK: call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 30, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_GT_OQ); return _mm_cmp_ps_mask(a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm_cmp_ps_mask_true_us(__m128 a, __m128 b) { __mmask8 test_mm_cmp_ps_mask_true_us(__m128 a, __m128 b) {
// CHECK-LABEL: test_mm_cmp_ps_mask_true_us // CHECK-LABEL: test_mm_cmp_ps_mask_true_us
// CHECK: call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 31) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 31, <4 x i1> {{.*}})
return _mm_cmp_ps_mask(a, b, _CMP_TRUE_US); return _mm_cmp_ps_mask(a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_eq_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_eq_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: @test_mm_mask_cmp_ps_mask_eq_oq // CHECK-LABEL: @test_mm_mask_cmp_ps_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 0, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_lt_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_lt_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_lt_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_lt_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 1, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LT_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_le_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_le_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_le_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_le_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 2, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LE_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_unord_q(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_unord_q(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_unord_q // CHECK-LABEL: test_mm_mask_cmp_ps_mask_unord_q
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 3, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm_mask_cmp_ps_mask_neq_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_neq_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 4, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nlt_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nlt_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nlt_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 5, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLT_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nle_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nle_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nle_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nle_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 6, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLE_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ord_q(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ord_q(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ord_q // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ord_q
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 7, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm_mask_cmp_ps_mask_eq_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_eq_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 8, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nge_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nge_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nge_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nge_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 9, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGE_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ngt_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ngt_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ngt_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 10, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGT_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_false_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_false_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_false_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_false_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 11) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 11, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_neq_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_neq_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 12, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ge_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ge_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ge_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ge_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 13, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GE_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_gt_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_gt_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_gt_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_gt_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 14, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GT_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_true_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_true_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_true_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_true_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 15) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 15, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_eq_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_eq_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 16, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_lt_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_lt_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_lt_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 17, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_le_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_le_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_le_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_le_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 18, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_unord_s(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_unord_s(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_unord_s // CHECK-LABEL: test_mm_mask_cmp_ps_mask_unord_s
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 19, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm_mask_cmp_ps_mask_neq_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_neq_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 20, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nlt_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nlt_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nlt_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 21, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nle_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nle_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nle_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 22, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ord_s(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ord_s(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ord_s // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ord_s
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 23, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_ORD_S);
} }
__mmask8 test_mm_mask_cmp_ps_mask_eq_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_eq_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_eq_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 24, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_EQ_US);
} }
__mmask8 test_mm_mask_cmp_ps_mask_nge_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_nge_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_nge_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 25, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ngt_uq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ngt_uq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ngt_uq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 26, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_false_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_false_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_false_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_false_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 27) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 27, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_neq_os(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_neq_os(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_os // CHECK-LABEL: test_mm_mask_cmp_ps_mask_neq_os
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 28, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm_mask_cmp_ps_mask_ge_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_ge_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_ge_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 29, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_gt_oq(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_gt_oq(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_gt_oq // CHECK-LABEL: test_mm_mask_cmp_ps_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 30, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm_mask_cmp_ps_mask_true_us(__mmask8 m, __m128 a, __m128 b) { __mmask8 test_mm_mask_cmp_ps_mask_true_us(__mmask8 m, __m128 a, __m128 b) {
// CHECK-LABEL: test_mm_mask_cmp_ps_mask_true_us // CHECK-LABEL: test_mm_mask_cmp_ps_mask_true_us
// CHECK: [[CMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 31) // CHECK: call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %{{.*}}, <4 x float> %{{.*}}, i32 31, <4 x i1> {{.*}})
// CHECK: and <4 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US); return _mm_mask_cmp_ps_mask(m, a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm_cmp_pd_mask_eq_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_eq_oq(__m128d a, __m128d b) {
// CHECK-LABEL: @test_mm_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm_cmp_pd_mask_eq_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 0, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_EQ_OQ); return _mm_cmp_pd_mask(a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_lt_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_lt_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm_cmp_pd_mask_lt_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 1, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_LT_OS); return _mm_cmp_pd_mask(a, b, _CMP_LT_OS);
} }
__mmask8 test_mm_cmp_pd_mask_le_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_le_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_le_os // CHECK-LABEL: test_mm_cmp_pd_mask_le_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 2, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_LE_OS); return _mm_cmp_pd_mask(a, b, _CMP_LE_OS);
} }
__mmask8 test_mm_cmp_pd_mask_unord_q(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_unord_q(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm_cmp_pd_mask_unord_q
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 3, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_UNORD_Q); return _mm_cmp_pd_mask(a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm_cmp_pd_mask_neq_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_neq_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm_cmp_pd_mask_neq_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 4, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NEQ_UQ); return _mm_cmp_pd_mask(a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_nlt_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nlt_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm_cmp_pd_mask_nlt_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 5, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NLT_US); return _mm_cmp_pd_mask(a, b, _CMP_NLT_US);
} }
__mmask8 test_mm_cmp_pd_mask_nle_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nle_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm_cmp_pd_mask_nle_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 6, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NLE_US); return _mm_cmp_pd_mask(a, b, _CMP_NLE_US);
} }
__mmask8 test_mm_cmp_pd_mask_ord_q(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ord_q(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm_cmp_pd_mask_ord_q
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 7, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_ORD_Q); return _mm_cmp_pd_mask(a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm_cmp_pd_mask_eq_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_eq_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm_cmp_pd_mask_eq_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 8, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_EQ_UQ); return _mm_cmp_pd_mask(a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_nge_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nge_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm_cmp_pd_mask_nge_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 9, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NGE_US); return _mm_cmp_pd_mask(a, b, _CMP_NGE_US);
} }
__mmask8 test_mm_cmp_pd_mask_ngt_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ngt_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm_cmp_pd_mask_ngt_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 10, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NGT_US); return _mm_cmp_pd_mask(a, b, _CMP_NGT_US);
} }
__mmask8 test_mm_cmp_pd_mask_false_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_false_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm_cmp_pd_mask_false_oq
// CHECK: call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 11) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 11, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_FALSE_OQ); return _mm_cmp_pd_mask(a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_neq_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_neq_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm_cmp_pd_mask_neq_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 12, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NEQ_OQ); return _mm_cmp_pd_mask(a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_ge_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ge_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm_cmp_pd_mask_ge_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 13, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_GE_OS); return _mm_cmp_pd_mask(a, b, _CMP_GE_OS);
} }
__mmask8 test_mm_cmp_pd_mask_gt_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_gt_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm_cmp_pd_mask_gt_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 14, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_GT_OS); return _mm_cmp_pd_mask(a, b, _CMP_GT_OS);
} }
__mmask8 test_mm_cmp_pd_mask_true_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_true_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm_cmp_pd_mask_true_uq
// CHECK: call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 15) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 15, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_TRUE_UQ); return _mm_cmp_pd_mask(a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_eq_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_eq_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm_cmp_pd_mask_eq_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 16, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_EQ_OS); return _mm_cmp_pd_mask(a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm_cmp_pd_mask_lt_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_lt_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm_cmp_pd_mask_lt_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 17, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_LT_OQ); return _mm_cmp_pd_mask(a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_le_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_le_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm_cmp_pd_mask_le_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 18, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_LE_OQ); return _mm_cmp_pd_mask(a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_unord_s(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_unord_s(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm_cmp_pd_mask_unord_s
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 19, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_UNORD_S); return _mm_cmp_pd_mask(a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm_cmp_pd_mask_neq_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_neq_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm_cmp_pd_mask_neq_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 20, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NEQ_US); return _mm_cmp_pd_mask(a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm_cmp_pd_mask_nlt_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nlt_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm_cmp_pd_mask_nlt_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 21, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NLT_UQ); return _mm_cmp_pd_mask(a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_nle_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nle_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm_cmp_pd_mask_nle_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 22, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NLE_UQ); return _mm_cmp_pd_mask(a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_ord_s(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ord_s(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm_cmp_pd_mask_ord_s
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 23, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_ORD_S); return _mm_cmp_pd_mask(a, b, _CMP_ORD_S);
} }
__mmask8 test_mm_cmp_pd_mask_eq_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_eq_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm_cmp_pd_mask_eq_us
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 24, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_EQ_US); return _mm_cmp_pd_mask(a, b, _CMP_EQ_US);
} }
__mmask8 test_mm_cmp_pd_mask_nge_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_nge_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm_cmp_pd_mask_nge_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 25, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NGE_UQ); return _mm_cmp_pd_mask(a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_ngt_uq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ngt_uq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm_cmp_pd_mask_ngt_uq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 26, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NGT_UQ); return _mm_cmp_pd_mask(a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm_cmp_pd_mask_false_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_false_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_false_os // CHECK-LABEL: test_mm_cmp_pd_mask_false_os
// CHECK: call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 27) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 27, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_FALSE_OS); return _mm_cmp_pd_mask(a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm_cmp_pd_mask_neq_os(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_neq_os(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm_cmp_pd_mask_neq_os
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 28, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_NEQ_OS); return _mm_cmp_pd_mask(a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm_cmp_pd_mask_ge_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_ge_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm_cmp_pd_mask_ge_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 29, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_GE_OQ); return _mm_cmp_pd_mask(a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_gt_oq(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_gt_oq(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm_cmp_pd_mask_gt_oq
// CHECK: call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 30, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_GT_OQ); return _mm_cmp_pd_mask(a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm_cmp_pd_mask_true_us(__m128d a, __m128d b) { __mmask8 test_mm_cmp_pd_mask_true_us(__m128d a, __m128d b) {
// CHECK-LABEL: test_mm_cmp_pd_mask_true_us // CHECK-LABEL: test_mm_cmp_pd_mask_true_us
// CHECK: call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 31) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 31, <2 x i1> {{.*}})
return _mm_cmp_pd_mask(a, b, _CMP_TRUE_US); return _mm_cmp_pd_mask(a, b, _CMP_TRUE_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_eq_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: @test_mm_mask_cmp_pd_mask_eq_oq // CHECK-LABEL: @test_mm_mask_cmp_pd_mask_eq_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 0, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_lt_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_lt_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_lt_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_lt_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 1, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LT_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_le_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_le_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_le_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_le_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 2, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LE_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_unord_q(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_unord_q(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_unord_q // CHECK-LABEL: test_mm_mask_cmp_pd_mask_unord_q
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 3, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_Q);
} }
__mmask8 test_mm_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_neq_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 4, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nlt_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nlt_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nlt_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 5, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLT_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nle_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nle_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nle_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nle_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 6, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLE_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ord_q(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ord_q(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ord_q // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ord_q
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 7, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_ORD_Q);
} }
__mmask8 test_mm_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_eq_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 8, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nge_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nge_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nge_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nge_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 9, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGE_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ngt_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ngt_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ngt_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 10, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGT_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_false_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_false_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_false_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_false_oq
// [[CMP]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 11) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 11, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_neq_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 12, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ge_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ge_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ge_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ge_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 13, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GE_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_gt_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_gt_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_gt_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_gt_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 14, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GT_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_true_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_true_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_true_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_true_uq
// [[CMP]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 15) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 15, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_eq_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_eq_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oeq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 16, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_lt_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_lt_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_lt_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"olt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 17, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LT_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_le_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_le_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_le_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_le_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ole", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 18, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_LE_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_unord_s(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_unord_s(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_unord_s // CHECK-LABEL: test_mm_mask_cmp_pd_mask_unord_s
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uno", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 19, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_UNORD_S);
} }
__mmask8 test_mm_mask_cmp_pd_mask_neq_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_neq_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"une", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 20, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nlt_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nlt_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nlt_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"uge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 21, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLT_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nle_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nle_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nle_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ugt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 22, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NLE_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ord_s(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ord_s(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ord_s // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ord_s
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ord", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 23, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_ORD_S);
} }
__mmask8 test_mm_mask_cmp_pd_mask_eq_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_eq_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_eq_us
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ueq", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 24, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_EQ_US);
} }
__mmask8 test_mm_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_nge_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_nge_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_nge_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ult", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 25, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGE_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ngt_uq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ngt_uq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ngt_uq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ule", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 26, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NGT_UQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_false_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_false_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_false_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_false_os
// [[CMP]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 27) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 27, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_FALSE_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_neq_os(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_neq_os(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_os // CHECK-LABEL: test_mm_mask_cmp_pd_mask_neq_os
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"one", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 28, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_NEQ_OS);
} }
__mmask8 test_mm_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_ge_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_ge_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_ge_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"oge", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 29, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GE_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_gt_oq(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_gt_oq // CHECK-LABEL: test_mm_mask_cmp_pd_mask_gt_oq
// CHECK: [[CMP:%.*]] = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 30, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_GT_OQ);
} }
__mmask8 test_mm_mask_cmp_pd_mask_true_us(__mmask8 m, __m128d a, __m128d b) { __mmask8 test_mm_mask_cmp_pd_mask_true_us(__mmask8 m, __m128d a, __m128d b) {
// CHECK-LABEL: test_mm_mask_cmp_pd_mask_true_us // CHECK-LABEL: test_mm_mask_cmp_pd_mask_true_us
// [[CMP]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 31) // CHECK: call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i32 31, <2 x i1> {{.*}})
// CHECK: and <2 x i1> [[CMP]], {{.*}}
return _mm_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US); return _mm_mask_cmp_pd_mask(m, a, b, _CMP_TRUE_US);
} }

llvm/include/llvm/IR/IntrinsicsX86.td

Show First 20 Lines • Show All 4,743 Lines • ▼ Show 20 Lines def int_x86_avx512_vp2intersect_d_128 :
[llvm_v4i32_ty, llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>; [IntrNoMem]>;
} }
// Misc. // Misc.
let TargetPrefix = "x86" in { let TargetPrefix = "x86" in {
// NOTE: These comparison intrinsics are not used by clang as long as the // NOTE: These comparison intrinsics are not used by clang as long as the
// distinction in signaling behaviour is not implemented. // distinction in signaling behaviour is not implemented.
def int_x86_avx512_cmp_ps_512 : def int_x86_avx512_mask_cmp_ps_512 :
Intrinsic<[llvm_v16i1_ty], [llvm_v16f32_ty, llvm_v16f32_ty, Intrinsic<[llvm_v16i1_ty], [llvm_v16f32_ty, llvm_v16f32_ty,
llvm_i32_ty, llvm_i32_ty], llvm_i32_ty, llvm_v16i1_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<4>>]>;
def int_x86_avx512_cmp_pd_512 : def int_x86_avx512_mask_cmp_pd_512 :
Intrinsic<[llvm_v8i1_ty], [llvm_v8f64_ty, llvm_v8f64_ty, Intrinsic<[llvm_v8i1_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
llvm_i32_ty, llvm_i32_ty], llvm_i32_ty, llvm_v8i1_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<4>>]>;
def int_x86_avx512_cmp_ps_256 : def int_x86_avx512_mask_cmp_ps_256 :
Intrinsic<[llvm_v8i1_ty], [llvm_v8f32_ty, llvm_v8f32_ty, Intrinsic<[llvm_v8i1_ty], [llvm_v8f32_ty, llvm_v8f32_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; llvm_i32_ty, llvm_v8i1_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_x86_avx512_cmp_pd_256 : def int_x86_avx512_mask_cmp_pd_256 :
Intrinsic<[llvm_v4i1_ty], [llvm_v4f64_ty, llvm_v4f64_ty, Intrinsic<[llvm_v4i1_ty], [llvm_v4f64_ty, llvm_v4f64_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; llvm_i32_ty, llvm_v4i1_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_x86_avx512_cmp_ps_128 : def int_x86_avx512_mask_cmp_ps_128 :
Intrinsic<[llvm_v4i1_ty], [llvm_v4f32_ty, llvm_v4f32_ty, Intrinsic<[llvm_v4i1_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; llvm_i32_ty, llvm_v4i1_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_x86_avx512_cmp_pd_128 : def int_x86_avx512_mask_cmp_pd_128 :
Intrinsic<[llvm_v2i1_ty], [llvm_v2f64_ty, llvm_v2f64_ty, Intrinsic<[llvm_v2i1_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>; llvm_i32_ty, llvm_v2i1_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_x86_avx512_mask_cmp_ss : def int_x86_avx512_mask_cmp_ss :
GCCBuiltin<"__builtin_ia32_cmpss_mask">, GCCBuiltin<"__builtin_ia32_cmpss_mask">,
Intrinsic<[llvm_i8_ty], [llvm_v4f32_ty, llvm_v4f32_ty, Intrinsic<[llvm_i8_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
llvm_i32_ty, llvm_i8_ty, llvm_i32_ty], llvm_i32_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<4>>]>; [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<4>>]>;
def int_x86_avx512_mask_cmp_sd : def int_x86_avx512_mask_cmp_sd :
GCCBuiltin<"__builtin_ia32_cmpsd_mask">, GCCBuiltin<"__builtin_ia32_cmpsd_mask">,
▲ Show 20 Lines • Show All 200 Lines • Show Last 20 Lines

llvm/lib/IR/AutoUpgrade.cpp

//===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines if (!LastArgType->isIntegerTy(32))
return false; return false;
// Move this function aside and map down. // Move this function aside and map down.
rename(F); rename(F);
NewFn = Intrinsic::getDeclaration(F->getParent(), IID); NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
return true; return true;
} }
// Upgrade the declaration of fp compare intrinsics that change return type
// from scalar to vXi1 mask.
static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID,
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for function 'UpgradeX86MaskedFPCompare' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for function 'UpgradeX86MaskedFPCompare' [readability…
Function *&NewFn) {
// Check if the return type is a vector.
if (F->getReturnType()->isVectorTy())
return false;
rename(F);
NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
return true;
}
static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
// All of the intrinsics matches below should be marked with which llvm // All of the intrinsics matches below should be marked with which llvm
// version started autoupgrading them. At some point in the future we would // version started autoupgrading them. At some point in the future we would
// like to use this information to remove upgrade code for some older // like to use this information to remove upgrade code for some older
// intrinsics. It is currently undecided how we will determine that future // intrinsics. It is currently undecided how we will determine that future
// point. // point.
if (Name == "addcarryx.u32" || // Added in 8.0 if (Name == "addcarryx.u32" || // Added in 8.0
Lint: Pre-merge checks
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clang-format: please reformat the code

-  if (Name == "addcarryx.u32" || // Added in 8.0
-      Name == "addcarryx.u64" || // Added in 8.0
-      Name == "addcarry.u32" || // Added in 8.0
-      Name == "addcarry.u64" || // Added in 8.0
-      Name == "subborrow.u32" || // Added in 8.0
-      Name == "subborrow.u64" || // Added in 8.0
-      Name.startswith("sse2.padds.") || // Added in 8.0
-      Name.startswith("sse2.psubs.") || // Added in 8.0
-      Name.startswith("sse2.paddus.") || // Added in 8.0
-      Name.startswith("sse2.psubus.") || // Added in 8.0

394 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - if (Name == "addcarryx.u32" || // Added in 8.0…
Name == "addcarryx.u64" || // Added in 8.0 Name == "addcarryx.u64" || // Added in 8.0
Name == "addcarry.u32" || // Added in 8.0 Name == "addcarry.u32" || // Added in 8.0
Name == "addcarry.u64" || // Added in 8.0 Name == "addcarry.u64" || // Added in 8.0
Name == "subborrow.u32" || // Added in 8.0 Name == "subborrow.u32" || // Added in 8.0
Name == "subborrow.u64" || // Added in 8.0 Name == "subborrow.u64" || // Added in 8.0
Name.startswith("sse2.padds.") || // Added in 8.0 Name.startswith("sse2.padds.") || // Added in 8.0
Name.startswith("sse2.psubs.") || // Added in 8.0 Name.startswith("sse2.psubs.") || // Added in 8.0
Name.startswith("sse2.paddus.") || // Added in 8.0 Name.startswith("sse2.paddus.") || // Added in 8.0
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines if (Name == "addcarryx.u32" || // Added in 8.0
Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0
Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0
Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0
Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0
Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0
Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0
Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0
Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0
Name.startswith("avx512.mask.cmp.p") || // Added in 7.0 Name.startswith("avx512.cmp.p") || // Added in 12.0
Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0
Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0
Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0
Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0
Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0
Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0
Name.startswith("avx512.mask.psll.d") || // Added in 4.0 Name.startswith("avx512.mask.psll.d") || // Added in 4.0
Name.startswith("avx512.mask.psll.q") || // Added in 4.0 Name.startswith("avx512.mask.psll.q") || // Added in 4.0
Show All 19 Lines if (Name == "addcarryx.u32" || // Added in 8.0
Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0
Name.startswith("avx512.mask.pternlog.") || // Added in 7.0 Name.startswith("avx512.mask.pternlog.") || // Added in 7.0
Name.startswith("avx512.maskz.pternlog.") || // Added in 7.0 Name.startswith("avx512.maskz.pternlog.") || // Added in 7.0
Name.startswith("avx512.mask.vpmadd52") || // Added in 7.0 Name.startswith("avx512.mask.vpmadd52") || // Added in 7.0
Name.startswith("avx512.maskz.vpmadd52") || // Added in 7.0 Name.startswith("avx512.maskz.vpmadd52") || // Added in 7.0
Name.startswith("avx512.mask.vpermi2var.") || // Added in 7.0 Name.startswith("avx512.mask.vpermi2var.") || // Added in 7.0
Name.startswith("avx512.mask.vpermt2var.") || // Added in 7.0 Name.startswith("avx512.mask.vpermt2var.") || // Added in 7.0
Name.startswith("avx512.maskz.vpermt2var.") || // Added in 7.0 Name.startswith("avx512.maskz.vpermt2var.") || // Added in 7.0
Name.startswith("avx512.mask.vpdpbusd.") || // Added in 7.0 Name.startswith("avx512.mask.vpdpbusd.") || // Added in 7.0
Lint: Pre-merge checks
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clang-format: please reformat the code

-      Name.startswith("avx512.mask.vpdpbusd.") || // Added in 7.0
-      Name.startswith("avx512.maskz.vpdpbusd.") || // Added in 7.0
-      Name.startswith("avx512.mask.vpdpbusds.") || // Added in 7.0
-      Name.startswith("avx512.maskz.vpdpbusds.") || // Added in 7.0
-      Name.startswith("avx512.mask.vpdpwssd.") || // Added in 7.0
-      Name.startswith("avx512.maskz.vpdpwssd.") || // Added in 7.0
-      Name.startswith("avx512.mask.vpdpwssds.") || // Added in 7.0
-      Name.startswith("avx512.maskz.vpdpwssds.") || // Added in 7.0
-      Name.startswith("avx512.mask.dbpsadbw.") || // Added in 7.0
-      Name.startswith("avx512.mask.vpshld.") || // Added in 7.0

24 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name.startswith("avx512.mask.vpdpbusd.") ||…
Name.startswith("avx512.maskz.vpdpbusd.") || // Added in 7.0 Name.startswith("avx512.maskz.vpdpbusd.") || // Added in 7.0
Name.startswith("avx512.mask.vpdpbusds.") || // Added in 7.0 Name.startswith("avx512.mask.vpdpbusds.") || // Added in 7.0
Name.startswith("avx512.maskz.vpdpbusds.") || // Added in 7.0 Name.startswith("avx512.maskz.vpdpbusds.") || // Added in 7.0
Name.startswith("avx512.mask.vpdpwssd.") || // Added in 7.0 Name.startswith("avx512.mask.vpdpwssd.") || // Added in 7.0
Name.startswith("avx512.maskz.vpdpwssd.") || // Added in 7.0 Name.startswith("avx512.maskz.vpdpwssd.") || // Added in 7.0
Name.startswith("avx512.mask.vpdpwssds.") || // Added in 7.0 Name.startswith("avx512.mask.vpdpwssds.") || // Added in 7.0
Name.startswith("avx512.maskz.vpdpwssds.") || // Added in 7.0 Name.startswith("avx512.maskz.vpdpwssds.") || // Added in 7.0
Name.startswith("avx512.mask.dbpsadbw.") || // Added in 7.0 Name.startswith("avx512.mask.dbpsadbw.") || // Added in 7.0
Name.startswith("avx512.mask.vpshld.") || // Added in 7.0 Name.startswith("avx512.mask.vpshld.") || // Added in 7.0
Name.startswith("avx512.mask.vpshrd.") || // Added in 7.0 Name.startswith("avx512.mask.vpshrd.") || // Added in 7.0
Name.startswith("avx512.mask.vpshldv.") || // Added in 8.0 Name.startswith("avx512.mask.vpshldv.") || // Added in 8.0
Name.startswith("avx512.mask.vpshrdv.") || // Added in 8.0 Name.startswith("avx512.mask.vpshrdv.") || // Added in 8.0
Name.startswith("avx512.maskz.vpshldv.") || // Added in 8.0 Name.startswith("avx512.maskz.vpshldv.") || // Added in 8.0
Name.startswith("avx512.maskz.vpshrdv.") || // Added in 8.0 Name.startswith("avx512.maskz.vpshrdv.") || // Added in 8.0
Name.startswith("avx512.vpshld.") || // Added in 8.0 Name.startswith("avx512.vpshld.") || // Added in 8.0
Name.startswith("avx512.vpshrd.") || // Added in 8.0 Name.startswith("avx512.vpshrd.") || // Added in 8.0
Name.startswith("avx512.mask.add.p") || // Added in 7.0. 128/256 in 4.0 Name.startswith("avx512.mask.add.p") || // Added in 7.0. 128/256 in 4.0
Name.startswith("avx512.mask.sub.p") || // Added in 7.0. 128/256 in 4.0 Name.startswith("avx512.mask.sub.p") || // Added in 7.0. 128/256 in 4.0
Name.startswith("avx512.mask.mul.p") || // Added in 7.0. 128/256 in 4.0 Name.startswith("avx512.mask.mul.p") || // Added in 7.0. 128/256 in 4.0
Name.startswith("avx512.mask.div.p") || // Added in 7.0. 128/256 in 4.0 Name.startswith("avx512.mask.div.p") || // Added in 7.0. 128/256 in 4.0
Name.startswith("avx512.mask.max.p") || // Added in 7.0. 128/256 in 5.0 Name.startswith("avx512.mask.max.p") || // Added in 7.0. 128/256 in 5.0
Name.startswith("avx512.mask.min.p") || // Added in 7.0. 128/256 in 5.0 Name.startswith("avx512.mask.min.p") || // Added in 7.0. 128/256 in 5.0
Name.startswith("avx512.mask.fpclass.p") || // Added in 7.0 Name.startswith("avx512.mask.fpclass.p") || // Added in 7.0
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Name.startswith("avx512.mask.fpclass.p") || // Added in 7.0
-      Name.startswith("avx512.mask.vpshufbitqmb.") || // Added in 8.0
+      Name.startswith("avx512.mask.fpclass.p") ||       // Added in 7.0
+      Name.startswith("avx512.mask.vpshufbitqmb.") ||   // Added in 8.0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name.startswith("avx512.mask.fpclass.p") ||…
Name.startswith("avx512.mask.vpshufbitqmb.") || // Added in 8.0 Name.startswith("avx512.mask.vpshufbitqmb.") || // Added in 8.0
Name.startswith("avx512.mask.pmultishift.qb.") || // Added in 8.0 Name.startswith("avx512.mask.pmultishift.qb.") || // Added in 8.0
Name.startswith("avx512.mask.conflict.") || // Added in 9.0 Name.startswith("avx512.mask.conflict.") || // Added in 9.0
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Name.startswith("avx512.mask.conflict.") || // Added in 9.0
-      Name == "avx512.mask.pmov.qd.256" || // Added in 9.0
-      Name == "avx512.mask.pmov.qd.512" || // Added in 9.0
-      Name == "avx512.mask.pmov.wb.256" || // Added in 9.0
-      Name == "avx512.mask.pmov.wb.512" || // Added in 9.0
-      Name == "sse.cvtsi2ss" || // Added in 7.0
-      Name == "sse.cvtsi642ss" || // Added in 7.0
-      Name == "sse2.cvtsi2sd" || // Added in 7.0
-      Name == "sse2.cvtsi642sd" || // Added in 7.0
-      Name == "sse2.cvtss2sd" || // Added in 7.0

76 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name.startswith("avx512.mask.conflict.") ||…
Name == "avx512.mask.pmov.qd.256" || // Added in 9.0 Name == "avx512.mask.pmov.qd.256" || // Added in 9.0
Name == "avx512.mask.pmov.qd.512" || // Added in 9.0 Name == "avx512.mask.pmov.qd.512" || // Added in 9.0
Name == "avx512.mask.pmov.wb.256" || // Added in 9.0 Name == "avx512.mask.pmov.wb.256" || // Added in 9.0
Name == "avx512.mask.pmov.wb.512" || // Added in 9.0 Name == "avx512.mask.pmov.wb.512" || // Added in 9.0
Name == "sse.cvtsi2ss" || // Added in 7.0 Name == "sse.cvtsi2ss" || // Added in 7.0
Name == "sse.cvtsi642ss" || // Added in 7.0 Name == "sse.cvtsi642ss" || // Added in 7.0
Name == "sse2.cvtsi2sd" || // Added in 7.0 Name == "sse2.cvtsi2sd" || // Added in 7.0
Name == "sse2.cvtsi642sd" || // Added in 7.0 Name == "sse2.cvtsi642sd" || // Added in 7.0
Show All 27 Lines if (Name == "addcarryx.u32" || // Added in 8.0
Name.startswith("avx512.mask.store.w.") || // Added in 3.9 Name.startswith("avx512.mask.store.w.") || // Added in 3.9
Name.startswith("avx512.mask.store.d.") || // Added in 3.9 Name.startswith("avx512.mask.store.d.") || // Added in 3.9
Name.startswith("avx512.mask.store.q.") || // Added in 3.9 Name.startswith("avx512.mask.store.q.") || // Added in 3.9
Name == "avx512.mask.store.ss" || // Added in 7.0 Name == "avx512.mask.store.ss" || // Added in 7.0
Name.startswith("avx512.mask.loadu.") || // Added in 3.9 Name.startswith("avx512.mask.loadu.") || // Added in 3.9
Name.startswith("avx512.mask.load.") || // Added in 3.9 Name.startswith("avx512.mask.load.") || // Added in 3.9
Name.startswith("avx512.mask.expand.load.") || // Added in 7.0 Name.startswith("avx512.mask.expand.load.") || // Added in 7.0
Name.startswith("avx512.mask.compress.store.") || // Added in 7.0 Name.startswith("avx512.mask.compress.store.") || // Added in 7.0
Name.startswith("avx512.mask.expand.b") || // Added in 9.0 Name.startswith("avx512.mask.expand.b") || // Added in 9.0
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Name.startswith("avx512.mask.expand.b") || // Added in 9.0
-      Name.startswith("avx512.mask.expand.w") || // Added in 9.0
-      Name.startswith("avx512.mask.expand.d") || // Added in 9.0
-      Name.startswith("avx512.mask.expand.q") || // Added in 9.0
-      Name.startswith("avx512.mask.expand.p") || // Added in 9.0
-      Name.startswith("avx512.mask.compress.b") || // Added in 9.0
-      Name.startswith("avx512.mask.compress.w") || // Added in 9.0
-      Name.startswith("avx512.mask.compress.d") || // Added in 9.0
-      Name.startswith("avx512.mask.compress.q") || // Added in 9.0
-      Name.startswith("avx512.mask.compress.p") || // Added in 9.0

46 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name.startswith("avx512.mask.expand.b") || //…
Name.startswith("avx512.mask.expand.w") || // Added in 9.0 Name.startswith("avx512.mask.expand.w") || // Added in 9.0
Name.startswith("avx512.mask.expand.d") || // Added in 9.0 Name.startswith("avx512.mask.expand.d") || // Added in 9.0
Name.startswith("avx512.mask.expand.q") || // Added in 9.0 Name.startswith("avx512.mask.expand.q") || // Added in 9.0
Name.startswith("avx512.mask.expand.p") || // Added in 9.0 Name.startswith("avx512.mask.expand.p") || // Added in 9.0
Name.startswith("avx512.mask.compress.b") || // Added in 9.0 Name.startswith("avx512.mask.compress.b") || // Added in 9.0
Name.startswith("avx512.mask.compress.w") || // Added in 9.0 Name.startswith("avx512.mask.compress.w") || // Added in 9.0
Name.startswith("avx512.mask.compress.d") || // Added in 9.0 Name.startswith("avx512.mask.compress.d") || // Added in 9.0
Name.startswith("avx512.mask.compress.q") || // Added in 9.0 Name.startswith("avx512.mask.compress.q") || // Added in 9.0
Show All 19 Lines if (Name == "addcarryx.u32" || // Added in 8.0
Name.startswith("avx512.mask.broadcastf32x4.") || // Added in 6.0 Name.startswith("avx512.mask.broadcastf32x4.") || // Added in 6.0
Name.startswith("avx512.mask.broadcastf64x2.") || // Added in 6.0 Name.startswith("avx512.mask.broadcastf64x2.") || // Added in 6.0
Name.startswith("avx512.mask.broadcastf32x8.") || // Added in 6.0 Name.startswith("avx512.mask.broadcastf32x8.") || // Added in 6.0
Name.startswith("avx512.mask.broadcastf64x4.") || // Added in 6.0 Name.startswith("avx512.mask.broadcastf64x4.") || // Added in 6.0
Name.startswith("avx512.mask.broadcasti32x4.") || // Added in 6.0 Name.startswith("avx512.mask.broadcasti32x4.") || // Added in 6.0
Name.startswith("avx512.mask.broadcasti64x2.") || // Added in 6.0 Name.startswith("avx512.mask.broadcasti64x2.") || // Added in 6.0
Name.startswith("avx512.mask.broadcasti32x8.") || // Added in 6.0 Name.startswith("avx512.mask.broadcasti32x8.") || // Added in 6.0
Name.startswith("avx512.mask.broadcasti64x4.") || // Added in 6.0 Name.startswith("avx512.mask.broadcasti64x4.") || // Added in 6.0
Name == "xop.vpcmov" || // Added in 3.8 Name == "xop.vpcmov" || // Added in 3.8
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Name == "xop.vpcmov" || // Added in 3.8
-      Name == "xop.vpcmov.256" || // Added in 5.0
-      Name.startswith("avx512.mask.move.s") || // Added in 4.0
-      Name.startswith("avx512.cvtmask2") || // Added in 5.0
-      Name.startswith("xop.vpcom") || // Added in 3.2, Updated in 9.0
-      Name.startswith("xop.vprot") || // Added in 8.0
-      Name.startswith("avx512.prol") || // Added in 8.0
-      Name.startswith("avx512.pror") || // Added in 8.0
+      Name == "xop.vpcmov" ||                           // Added in 3.8
+      Name == "xop.vpcmov.256" ||                       // Added in 5.0

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name == "xop.vpcmov" || // Added in 3.8…
Name == "xop.vpcmov.256" || // Added in 5.0 Name == "xop.vpcmov.256" || // Added in 5.0
Name.startswith("avx512.mask.move.s") || // Added in 4.0 Name.startswith("avx512.mask.move.s") || // Added in 4.0
Name.startswith("avx512.cvtmask2") || // Added in 5.0 Name.startswith("avx512.cvtmask2") || // Added in 5.0
Name.startswith("xop.vpcom") || // Added in 3.2, Updated in 9.0 Name.startswith("xop.vpcom") || // Added in 3.2, Updated in 9.0
Name.startswith("xop.vprot") || // Added in 8.0 Name.startswith("xop.vprot") || // Added in 8.0
Name.startswith("avx512.prol") || // Added in 8.0 Name.startswith("avx512.prol") || // Added in 8.0
Name.startswith("avx512.pror") || // Added in 8.0 Name.startswith("avx512.pror") || // Added in 8.0
Name.startswith("avx512.mask.prorv.") || // Added in 8.0 Name.startswith("avx512.mask.prorv.") || // Added in 8.0
Name.startswith("avx512.mask.pror.") || // Added in 8.0 Name.startswith("avx512.mask.pror.") || // Added in 8.0
Name.startswith("avx512.mask.prolv.") || // Added in 8.0 Name.startswith("avx512.mask.prolv.") || // Added in 8.0
Name.startswith("avx512.mask.prol.") || // Added in 8.0 Name.startswith("avx512.mask.prol.") || // Added in 8.0
Name.startswith("avx512.ptestm") || //Added in 6.0 Name.startswith("avx512.ptestm") || //Added in 6.0
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Name.startswith("avx512.ptestm") || //Added in 6.0
-      Name.startswith("avx512.ptestnm") || //Added in 6.0
-      Name.startswith("avx512.mask.pavg")) // Added in 6.0
+      Name.startswith("avx512.ptestm") ||      // Added in 6.0
+      Name.startswith("avx512.ptestnm") ||     // Added in 6.0
+      Name.startswith("avx512.mask.pavg"))     // Added in 6.0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Name.startswith("avx512.ptestm") || //Added…
Name.startswith("avx512.ptestnm") || //Added in 6.0 Name.startswith("avx512.ptestnm") || //Added in 6.0
Name.startswith("avx512.mask.pavg")) // Added in 6.0 Name.startswith("avx512.mask.pavg")) // Added in 6.0
return true; return true;
return false; return false;
} }
static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name,
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines if (Name == "sse41.mpsadbw") // Added in 3.6
return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw,
NewFn); NewFn);
if (Name == "avx.dp.ps.256") // Added in 3.6 if (Name == "avx.dp.ps.256") // Added in 3.6
return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256,
NewFn); NewFn);
if (Name == "avx2.mpsadbw") // Added in 3.6 if (Name == "avx2.mpsadbw") // Added in 3.6
return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw,
NewFn); NewFn);
if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128,
NewFn);
if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256,
NewFn);
if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512,
NewFn);
if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128,
NewFn);
if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256,
NewFn);
if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0
return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512,
NewFn);
// frcz.ss/sd may need to have an argument dropped. Added in 3.2 // frcz.ss/sd may need to have an argument dropped. Added in 3.2
if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) {
rename(F); rename(F);
NewFn = Intrinsic::getDeclaration(F->getParent(), NewFn = Intrinsic::getDeclaration(F->getParent(),
Intrinsic::x86_xop_vfrcz_ss); Intrinsic::x86_xop_vfrcz_ss);
return true; return true;
} }
▲ Show 20 Lines • Show All 1,528 Lines • ▼ Show 20 Lines if (IsX86 && (Name.startswith("sse2.pcmp") ||
else if (VecWidth == 512 && EltWidth == 64) else if (VecWidth == 512 && EltWidth == 64)
IID = Intrinsic::x86_avx512_fpclass_pd_512; IID = Intrinsic::x86_avx512_fpclass_pd_512;
else else
llvm_unreachable("Unexpected intrinsic"); llvm_unreachable("Unexpected intrinsic");
Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
{ CI->getOperand(0), CI->getArgOperand(1) }); { CI->getOperand(0), CI->getArgOperand(1) });
Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2));
} else if (IsX86 && Name.startswith("avx512.mask.cmp.p")) { } else if (IsX86 && Name.startswith("avx512.cmp.p")) {
Type *OpTy = CI->getArgOperand(0)->getType(); SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
CI->arg_operands().end());
Type *OpTy = Args[0]->getType();
unsigned VecWidth = OpTy->getPrimitiveSizeInBits(); unsigned VecWidth = OpTy->getPrimitiveSizeInBits();
unsigned EltWidth = OpTy->getScalarSizeInBits(); unsigned EltWidth = OpTy->getScalarSizeInBits();
Intrinsic::ID IID; Intrinsic::ID IID;
if (VecWidth == 128 && EltWidth == 32) if (VecWidth == 128 && EltWidth == 32)
IID = Intrinsic::x86_avx512_cmp_ps_128; IID = Intrinsic::x86_avx512_mask_cmp_ps_128;
else if (VecWidth == 256 && EltWidth == 32) else if (VecWidth == 256 && EltWidth == 32)
IID = Intrinsic::x86_avx512_cmp_ps_256; IID = Intrinsic::x86_avx512_mask_cmp_ps_256;
else if (VecWidth == 512 && EltWidth == 32) else if (VecWidth == 512 && EltWidth == 32)
IID = Intrinsic::x86_avx512_cmp_ps_512; IID = Intrinsic::x86_avx512_mask_cmp_ps_512;
else if (VecWidth == 128 && EltWidth == 64) else if (VecWidth == 128 && EltWidth == 64)
IID = Intrinsic::x86_avx512_cmp_pd_128; IID = Intrinsic::x86_avx512_mask_cmp_pd_128;
else if (VecWidth == 256 && EltWidth == 64) else if (VecWidth == 256 && EltWidth == 64)
IID = Intrinsic::x86_avx512_cmp_pd_256; IID = Intrinsic::x86_avx512_mask_cmp_pd_256;
else if (VecWidth == 512 && EltWidth == 64) else if (VecWidth == 512 && EltWidth == 64)
IID = Intrinsic::x86_avx512_cmp_pd_512; IID = Intrinsic::x86_avx512_mask_cmp_pd_512;
else else
llvm_unreachable("Unexpected intrinsic"); llvm_unreachable("Unexpected intrinsic");
SmallVector<Value *, 4> Args; Value *Mask = Constant::getAllOnesValue(CI->getType());
Args.push_back(CI->getArgOperand(0)); if (VecWidth == 512)
Args.push_back(CI->getArgOperand(1)); std::swap(Mask, Args.back());
Args.push_back(CI->getArgOperand(2)); Args.push_back(Mask);
if (CI->getNumArgOperands() == 5)
Args.push_back(CI->getArgOperand(4));
Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
Args); Args);
Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(3)); } else if (IsX86 && Name.startswith("avx512.mask.cmp.")) {
} else if (IsX86 && Name.startswith("avx512.mask.cmp.") &&
Name[16] != 'p') {
// Integer compare intrinsics. // Integer compare intrinsics.
unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); Rep = upgradeMaskedCompare(Builder, *CI, Imm, true);
} else if (IsX86 && Name.startswith("avx512.mask.ucmp.")) { } else if (IsX86 && Name.startswith("avx512.mask.ucmp.")) {
unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); Rep = upgradeMaskedCompare(Builder, *CI, Imm, false);
} else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") ||
Name.startswith("avx512.cvtw2mask.") || Name.startswith("avx512.cvtw2mask.") ||
Name.startswith("avx512.cvtd2mask.") || Name.startswith("avx512.cvtd2mask.") ||
Name.startswith("avx512.cvtq2mask."))) { Name.startswith("avx512.cvtq2mask."))) {
Value *Op = CI->getArgOperand(0); Value *Op = CI->getArgOperand(0);
Value *Zero = llvm::Constant::getNullValue(Op->getType()); Value *Zero = llvm::Constant::getNullValue(Op->getType());
Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero);
Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr); Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr);
} else if(IsX86 && (Name == "ssse3.pabs.b.128" || } else if(IsX86 && (Name == "ssse3.pabs.b.128" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if(IsX86 && (Name == "ssse3.pabs.b.128" ||
-                        Name == "ssse3.pabs.w.128" ||
-                        Name == "ssse3.pabs.d.128" ||
-                        Name.startswith("avx2.pabs") ||
-                        Name.startswith("avx512.mask.pabs"))) {
+    } else if (IsX86 &&
+               (Name == "ssse3.pabs.b.128" || Name == "ssse3.pabs.w.128" ||
+                Name == "ssse3.pabs.d.128" || Name.startswith("avx2.pabs") ||
+                Name.startswith("avx512.mask.pabs"))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if(IsX86 && (Name == "ssse3.pabs.b.128"…
Name == "ssse3.pabs.w.128" || Name == "ssse3.pabs.w.128" ||
Name == "ssse3.pabs.d.128" || Name == "ssse3.pabs.d.128" ||
Name.startswith("avx2.pabs") || Name.startswith("avx2.pabs") ||
Name.startswith("avx512.mask.pabs"))) { Name.startswith("avx512.mask.pabs"))) {
Rep = upgradeAbs(Builder, *CI); Rep = upgradeAbs(Builder, *CI);
} else if (IsX86 && (Name == "sse41.pmaxsb" || } else if (IsX86 && (Name == "sse41.pmaxsb" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse41.pmaxsb" ||
-                         Name == "sse2.pmaxs.w" ||
-                         Name == "sse41.pmaxsd" ||
-                         Name.startswith("avx2.pmaxs") ||
-                         Name.startswith("avx512.mask.pmaxs"))) {
+    } else if (IsX86 &&
+               (Name == "sse41.pmaxsb" || Name == "sse2.pmaxs.w" ||
+                Name == "sse41.pmaxsd" || Name.startswith("avx2.pmaxs") ||
+                Name.startswith("avx512.mask.pmaxs"))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse41.pmaxsb" ||…
Name == "sse2.pmaxs.w" || Name == "sse2.pmaxs.w" ||
Name == "sse41.pmaxsd" || Name == "sse41.pmaxsd" ||
Name.startswith("avx2.pmaxs") || Name.startswith("avx2.pmaxs") ||
Name.startswith("avx512.mask.pmaxs"))) { Name.startswith("avx512.mask.pmaxs"))) {
Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT);
} else if (IsX86 && (Name == "sse2.pmaxu.b" || } else if (IsX86 && (Name == "sse2.pmaxu.b" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.pmaxu.b" ||
-                         Name == "sse41.pmaxuw" ||
-                         Name == "sse41.pmaxud" ||
-                         Name.startswith("avx2.pmaxu") ||
-                         Name.startswith("avx512.mask.pmaxu"))) {
+    } else if (IsX86 &&
+               (Name == "sse2.pmaxu.b" || Name == "sse41.pmaxuw" ||
+                Name == "sse41.pmaxud" || Name.startswith("avx2.pmaxu") ||
+                Name.startswith("avx512.mask.pmaxu"))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.pmaxu.b" ||…
Name == "sse41.pmaxuw" || Name == "sse41.pmaxuw" ||
Name == "sse41.pmaxud" || Name == "sse41.pmaxud" ||
Name.startswith("avx2.pmaxu") || Name.startswith("avx2.pmaxu") ||
Name.startswith("avx512.mask.pmaxu"))) { Name.startswith("avx512.mask.pmaxu"))) {
Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT);
} else if (IsX86 && (Name == "sse41.pminsb" || } else if (IsX86 && (Name == "sse41.pminsb" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse41.pminsb" ||
-                         Name == "sse2.pmins.w" ||
-                         Name == "sse41.pminsd" ||
-                         Name.startswith("avx2.pmins") ||
-                         Name.startswith("avx512.mask.pmins"))) {
+    } else if (IsX86 &&
+               (Name == "sse41.pminsb" || Name == "sse2.pmins.w" ||
+                Name == "sse41.pminsd" || Name.startswith("avx2.pmins") ||
+                Name.startswith("avx512.mask.pmins"))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse41.pminsb" ||…
Name == "sse2.pmins.w" || Name == "sse2.pmins.w" ||
Name == "sse41.pminsd" || Name == "sse41.pminsd" ||
Name.startswith("avx2.pmins") || Name.startswith("avx2.pmins") ||
Name.startswith("avx512.mask.pmins"))) { Name.startswith("avx512.mask.pmins"))) {
Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT);
} else if (IsX86 && (Name == "sse2.pminu.b" || } else if (IsX86 && (Name == "sse2.pminu.b" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.pminu.b" ||
-                         Name == "sse41.pminuw" ||
-                         Name == "sse41.pminud" ||
-                         Name.startswith("avx2.pminu") ||
-                         Name.startswith("avx512.mask.pminu"))) {
+    } else if (IsX86 &&
+               (Name == "sse2.pminu.b" || Name == "sse41.pminuw" ||
+                Name == "sse41.pminud" || Name.startswith("avx2.pminu") ||
+                Name.startswith("avx512.mask.pminu"))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.pminu.b" ||…
Name == "sse41.pminuw" || Name == "sse41.pminuw" ||
Name == "sse41.pminud" || Name == "sse41.pminud" ||
Name.startswith("avx2.pminu") || Name.startswith("avx2.pminu") ||
Name.startswith("avx512.mask.pminu"))) { Name.startswith("avx512.mask.pminu"))) {
Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT);
} else if (IsX86 && (Name == "sse2.pmulu.dq" || } else if (IsX86 && (Name == "sse2.pmulu.dq" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.pmulu.dq" ||
-                         Name == "avx2.pmulu.dq" ||
+    } else if (IsX86 && (Name == "sse2.pmulu.dq" || Name == "avx2.pmulu.dq" ||
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.pmulu.dq" ||…
Name == "avx2.pmulu.dq" || Name == "avx2.pmulu.dq" ||
Name == "avx512.pmulu.dq.512" || Name == "avx512.pmulu.dq.512" ||
Name.startswith("avx512.mask.pmulu.dq."))) { Name.startswith("avx512.mask.pmulu.dq."))) {
Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false); Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false);
} else if (IsX86 && (Name == "sse41.pmuldq" || } else if (IsX86 && (Name == "sse41.pmuldq" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse41.pmuldq" ||
-                         Name == "avx2.pmul.dq" ||
+    } else if (IsX86 && (Name == "sse41.pmuldq" || Name == "avx2.pmul.dq" ||
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse41.pmuldq" ||…
Name == "avx2.pmul.dq" || Name == "avx2.pmul.dq" ||
Name == "avx512.pmul.dq.512" || Name == "avx512.pmul.dq.512" ||
Name.startswith("avx512.mask.pmul.dq."))) { Name.startswith("avx512.mask.pmul.dq."))) {
Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true); Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true);
} else if (IsX86 && (Name == "sse.cvtsi2ss" || } else if (IsX86 && (Name == "sse.cvtsi2ss" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse.cvtsi2ss" ||
-                         Name == "sse2.cvtsi2sd" ||
-                         Name == "sse.cvtsi642ss" ||
-                         Name == "sse2.cvtsi642sd")) {
+    } else if (IsX86 &&
+               (Name == "sse.cvtsi2ss" || Name == "sse2.cvtsi2sd" ||
+                Name == "sse.cvtsi642ss" || Name == "sse2.cvtsi642sd")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse.cvtsi2ss" ||…
Name == "sse2.cvtsi2sd" || Name == "sse2.cvtsi2sd" ||
Name == "sse.cvtsi642ss" || Name == "sse.cvtsi642ss" ||
Name == "sse2.cvtsi642sd")) { Name == "sse2.cvtsi642sd")) {
Rep = Builder.CreateSIToFP( Rep = Builder.CreateSIToFP(
CI->getArgOperand(1), CI->getArgOperand(1),
cast<VectorType>(CI->getType())->getElementType()); cast<VectorType>(CI->getType())->getElementType());
Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0);
} else if (IsX86 && Name == "avx512.cvtusi2sd") { } else if (IsX86 && Name == "avx512.cvtusi2sd") {
Rep = Builder.CreateUIToFP( Rep = Builder.CreateUIToFP(
CI->getArgOperand(1), CI->getArgOperand(1),
cast<VectorType>(CI->getType())->getElementType()); cast<VectorType>(CI->getType())->getElementType());
Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0);
} else if (IsX86 && Name == "sse2.cvtss2sd") { } else if (IsX86 && Name == "sse2.cvtss2sd") {
Rep = Builder.CreateExtractElement(CI->getArgOperand(1), (uint64_t)0); Rep = Builder.CreateExtractElement(CI->getArgOperand(1), (uint64_t)0);
Rep = Builder.CreateFPExt( Rep = Builder.CreateFPExt(
Rep, cast<VectorType>(CI->getType())->getElementType()); Rep, cast<VectorType>(CI->getType())->getElementType());
Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0);
} else if (IsX86 && (Name == "sse2.cvtdq2pd" || } else if (IsX86 && (Name == "sse2.cvtdq2pd" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.cvtdq2pd" ||
-                         Name == "sse2.cvtdq2ps" ||
-                         Name == "avx.cvtdq2.pd.256" ||
-                         Name == "avx.cvtdq2.ps.256" ||
-                         Name.startswith("avx512.mask.cvtdq2pd.") ||
-                         Name.startswith("avx512.mask.cvtudq2pd.") ||
-                         Name.startswith("avx512.mask.cvtdq2ps.") ||
-                         Name.startswith("avx512.mask.cvtudq2ps.") ||
-                         Name.startswith("avx512.mask.cvtqq2pd.") ||
-                         Name.startswith("avx512.mask.cvtuqq2pd.") ||

24 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.cvtdq2pd" ||…
Name == "sse2.cvtdq2ps" || Name == "sse2.cvtdq2ps" ||
Name == "avx.cvtdq2.pd.256" || Name == "avx.cvtdq2.pd.256" ||
Name == "avx.cvtdq2.ps.256" || Name == "avx.cvtdq2.ps.256" ||
Name.startswith("avx512.mask.cvtdq2pd.") || Name.startswith("avx512.mask.cvtdq2pd.") ||
Name.startswith("avx512.mask.cvtudq2pd.") || Name.startswith("avx512.mask.cvtudq2pd.") ||
Name.startswith("avx512.mask.cvtdq2ps.") || Name.startswith("avx512.mask.cvtdq2ps.") ||
Name.startswith("avx512.mask.cvtudq2ps.") || Name.startswith("avx512.mask.cvtudq2ps.") ||
Name.startswith("avx512.mask.cvtqq2pd.") || Name.startswith("avx512.mask.cvtqq2pd.") ||
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines if (IsX86 && (Name.startswith("sse2.pcmp") ||
LaneMask += NumLanes; LaneMask += NumLanes;
for (unsigned i = 0; i != NumElementsInLane; ++i) for (unsigned i = 0; i != NumElementsInLane; ++i)
ShuffleMask.push_back(LaneMask * NumElementsInLane + i); ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
} }
Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), Rep = Builder.CreateShuffleVector(CI->getArgOperand(0),
CI->getArgOperand(1), ShuffleMask); CI->getArgOperand(1), ShuffleMask);
Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep,
CI->getArgOperand(3)); CI->getArgOperand(3));
}else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") ||
+    } else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") ||
Lint: Pre-merge checks: clang-format: please reformat the code ``` - }else if (IsX86 && (Name.startswith("avx512.
Name.startswith("avx512.mask.broadcasti"))) { Name.startswith("avx512.mask.broadcasti"))) {
unsigned NumSrcElts = unsigned NumSrcElts =
cast<VectorType>(CI->getArgOperand(0)->getType())->getNumElements(); cast<VectorType>(CI->getArgOperand(0)->getType())->getNumElements();
unsigned NumDstElts = cast<VectorType>(CI->getType())->getNumElements(); unsigned NumDstElts = cast<VectorType>(CI->getType())->getNumElements();
SmallVector<int, 8> ShuffleMask(NumDstElts); SmallVector<int, 8> ShuffleMask(NumDstElts);
for (unsigned i = 0; i != NumDstElts; ++i) for (unsigned i = 0; i != NumDstElts; ++i)
ShuffleMask[i] = i % NumSrcElts; ShuffleMask[i] = i % NumSrcElts;
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines if (IsX86 && (Name.startswith("sse2.pcmp") ||
false); false);
} else if (IsX86 && Name.startswith("avx512.mask.valign.")) { } else if (IsX86 && Name.startswith("avx512.mask.valign.")) {
Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0),
CI->getArgOperand(1), CI->getArgOperand(1),
CI->getArgOperand(2), CI->getArgOperand(2),
CI->getArgOperand(3), CI->getArgOperand(3),
CI->getArgOperand(4), CI->getArgOperand(4),
true); true);
} else if (IsX86 && (Name == "sse2.psll.dq" || } else if (IsX86 && (Name == "sse2.psll.dq" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.psll.dq" ||
-                         Name == "avx2.psll.dq")) {
+    } else if (IsX86 && (Name == "sse2.psll.dq" || Name == "avx2.psll.dq")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.psll.dq" ||…
Name == "avx2.psll.dq")) { Name == "avx2.psll.dq")) {
// 128/256-bit shift left specified in bits. // 128/256-bit shift left specified in bits.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0),
Shift / 8); // Shift is in bits. Shift / 8); // Shift is in bits.
} else if (IsX86 && (Name == "sse2.psrl.dq" || } else if (IsX86 && (Name == "sse2.psrl.dq" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.psrl.dq" ||
-                         Name == "avx2.psrl.dq")) {
+    } else if (IsX86 && (Name == "sse2.psrl.dq" || Name == "avx2.psrl.dq")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.psrl.dq" ||…
Name == "avx2.psrl.dq")) { Name == "avx2.psrl.dq")) {
// 128/256-bit shift right specified in bits. // 128/256-bit shift right specified in bits.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0),
Shift / 8); // Shift is in bits. Shift / 8); // Shift is in bits.
} else if (IsX86 && (Name == "sse2.psll.dq.bs" || } else if (IsX86 && (Name == "sse2.psll.dq.bs" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.psll.dq.bs" ||
-                         Name == "avx2.psll.dq.bs" ||
-                         Name == "avx512.psll.dq.512")) {
+    } else if (IsX86 &&
+               (Name == "sse2.psll.dq.bs" || Name == "avx2.psll.dq.bs" ||
+                Name == "avx512.psll.dq.512")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.psll.dq.bs"…
Name == "avx2.psll.dq.bs" || Name == "avx2.psll.dq.bs" ||
Name == "avx512.psll.dq.512")) { Name == "avx512.psll.dq.512")) {
// 128/256/512-bit shift left specified in bytes. // 128/256/512-bit shift left specified in bytes.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift);
} else if (IsX86 && (Name == "sse2.psrl.dq.bs" || } else if (IsX86 && (Name == "sse2.psrl.dq.bs" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse2.psrl.dq.bs" ||
-                         Name == "avx2.psrl.dq.bs" ||
-                         Name == "avx512.psrl.dq.512")) {
+    } else if (IsX86 &&
+               (Name == "sse2.psrl.dq.bs" || Name == "avx2.psrl.dq.bs" ||
+                Name == "avx512.psrl.dq.512")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse2.psrl.dq.bs"…
Name == "avx2.psrl.dq.bs" || Name == "avx2.psrl.dq.bs" ||
Name == "avx512.psrl.dq.512")) { Name == "avx512.psrl.dq.512")) {
// 128/256/512-bit shift right specified in bytes. // 128/256/512-bit shift right specified in bytes.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift);
} else if (IsX86 && (Name == "sse41.pblendw" || } else if (IsX86 && (Name == "sse41.pblendw" ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name == "sse41.pblendw" ||
-                         Name.startswith("sse41.blendp") ||
-                         Name.startswith("avx.blend.p") ||
-                         Name == "avx2.pblendw" ||
-                         Name.startswith("avx2.pblendd."))) {
+    } else if (IsX86 &&
+               (Name == "sse41.pblendw" || Name.startswith("sse41.blendp") ||
+                Name.startswith("avx.blend.p") || Name == "avx2.pblendw" ||
+                Name.startswith("avx2.pblendd."))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name == "sse41.pblendw" ||…
Name.startswith("sse41.blendp") || Name.startswith("sse41.blendp") ||
Name.startswith("avx.blend.p") || Name.startswith("avx.blend.p") ||
Name == "avx2.pblendw" || Name == "avx2.pblendw" ||
Name.startswith("avx2.pblendd."))) { Name.startswith("avx2.pblendd."))) {
Value *Op0 = CI->getArgOperand(0); Value *Op0 = CI->getArgOperand(0);
Value *Op1 = CI->getArgOperand(1); Value *Op1 = CI->getArgOperand(1);
unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue();
VectorType *VecTy = cast<VectorType>(CI->getType()); VectorType *VecTy = cast<VectorType>(CI->getType());
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines if (IsX86 && (Name.startswith("sse2.pcmp") ||
// Permute high half of result. // Permute high half of result.
StartIndex = (Imm & 0x10) ? HalfSize : 0; StartIndex = (Imm & 0x10) ? HalfSize : 0;
for (unsigned i = 0; i < HalfSize; ++i) for (unsigned i = 0; i < HalfSize; ++i)
ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; ShuffleMask[i + HalfSize] = NumElts + StartIndex + i;
Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
} else if (IsX86 && (Name.startswith("avx.vpermil.") || } else if (IsX86 && (Name.startswith("avx.vpermil.") ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name.startswith("avx.vpermil.") ||
-                         Name == "sse2.pshuf.d" ||
-                         Name.startswith("avx512.mask.vpermil.p") ||
-                         Name.startswith("avx512.mask.pshuf.d."))) {
+    } else if (IsX86 &&
+               (Name.startswith("avx.vpermil.") || Name == "sse2.pshuf.d" ||
+                Name.startswith("avx512.mask.vpermil.p") ||
+                Name.startswith("avx512.mask.pshuf.d."))) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name.startswith("avx.
Name == "sse2.pshuf.d" || Name == "sse2.pshuf.d" ||
Name.startswith("avx512.mask.vpermil.p") || Name.startswith("avx512.mask.vpermil.p") ||
Name.startswith("avx512.mask.pshuf.d."))) { Name.startswith("avx512.mask.pshuf.d."))) {
Value *Op0 = CI->getArgOperand(0); Value *Op0 = CI->getArgOperand(0);
unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
VectorType *VecTy = cast<VectorType>(CI->getType()); VectorType *VecTy = cast<VectorType>(CI->getType());
unsigned NumElts = VecTy->getNumElements(); unsigned NumElts = VecTy->getNumElements();
// Calculate the size of each index in the immediate. // Calculate the size of each index in the immediate.
▲ Show 20 Lines • Show All 237 Lines • ▼ Show 20 Lines
Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
{ CI->getArgOperand(0), CI->getArgOperand(1), { CI->getArgOperand(0), CI->getArgOperand(1),
CI->getArgOperand(4) }); CI->getArgOperand(4) });
} else { } else {
Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1));
} }
Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
CI->getArgOperand(2)); CI->getArgOperand(2));
} else if (IsX86 && (Name.startswith("avx512.mask.max.p") || } else if (IsX86 && (Name.startswith("avx512.mask.max.p") ||
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 && (Name.startswith("avx512.mask.max.p") ||
-                         Name.startswith("avx512.mask.min.p")) &&
+    } else if (IsX86 &&
+               (Name.startswith("avx512.mask.max.p") ||
+                Name.startswith("avx512.mask.min.p")) &&
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && (Name.startswith("avx512.
Name.startswith("avx512.mask.min.p")) && Name.startswith("avx512.mask.min.p")) &&
Name.drop_front(18) == ".512") { Name.drop_front(18) == ".512") {
bool IsDouble = Name[17] == 'd'; bool IsDouble = Name[17] == 'd';
bool IsMin = Name[13] == 'i'; bool IsMin = Name[13] == 'i';
static const Intrinsic::ID MinMaxTbl[2][2] = { static const Intrinsic::ID MinMaxTbl[2][2] = {
{ Intrinsic::x86_avx512_max_ps_512, Intrinsic::x86_avx512_max_pd_512 }, { Intrinsic::x86_avx512_max_ps_512, Intrinsic::x86_avx512_max_pd_512 },
{ Intrinsic::x86_avx512_min_ps_512, Intrinsic::x86_avx512_min_pd_512 } { Intrinsic::x86_avx512_min_ps_512, Intrinsic::x86_avx512_min_pd_512 }
}; };
▲ Show 20 Lines • Show All 381 Lines • ▼ Show 20 Lines
Rep = Builder.CreateCall(FMA, { A, B, C }); Rep = Builder.CreateCall(FMA, { A, B, C });
} }
Value *PassThru = IsMaskZ ? llvm::Constant::getNullValue(CI->getType()) : Value *PassThru = IsMaskZ ? llvm::Constant::getNullValue(CI->getType()) :
IsMask3 ? CI->getArgOperand(2) : IsMask3 ? CI->getArgOperand(2) :
CI->getArgOperand(0); CI->getArgOperand(0);
Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru);
} else if (IsX86 && Name.startswith("fma.vfmsubadd.p")) { } else if (IsX86 && Name.startswith("fma.vfmsubadd.p")) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } else if (IsX86 &&  Name.startswith("fma.vfmsubadd.p")) {
+    } else if (IsX86 && Name.startswith("fma.vfmsubadd.p")) {
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } else if (IsX86 && Name.startswith("fma.
unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits();
unsigned EltWidth = CI->getType()->getScalarSizeInBits(); unsigned EltWidth = CI->getType()->getScalarSizeInBits();
Intrinsic::ID IID; Intrinsic::ID IID;
if (VecWidth == 128 && EltWidth == 32) if (VecWidth == 128 && EltWidth == 32)
IID = Intrinsic::x86_fma_vfmaddsub_ps; IID = Intrinsic::x86_fma_vfmaddsub_ps;
else if (VecWidth == 256 && EltWidth == 32) else if (VecWidth == 256 && EltWidth == 32)
IID = Intrinsic::x86_fma_vfmaddsub_ps_256; IID = Intrinsic::x86_fma_vfmaddsub_ps_256;
else if (VecWidth == 128 && EltWidth == 64) else if (VecWidth == 128 && EltWidth == 64)
▲ Show 20 Lines • Show All 456 Lines • ▼ Show 20 Lines SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
CI->arg_operands().end()); CI->arg_operands().end());
// Replace the last argument with a trunc. // Replace the last argument with a trunc.
Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc");
NewCall = Builder.CreateCall(NewFn, Args); NewCall = Builder.CreateCall(NewFn, Args);
break; break;
} }
case Intrinsic::x86_avx512_mask_cmp_pd_128:
case Intrinsic::x86_avx512_mask_cmp_pd_256:
case Intrinsic::x86_avx512_mask_cmp_pd_512:
case Intrinsic::x86_avx512_mask_cmp_ps_128:
case Intrinsic::x86_avx512_mask_cmp_ps_256:
case Intrinsic::x86_avx512_mask_cmp_ps_512: {
SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
CI->arg_operands().end());
unsigned NumElts = cast<VectorType>(Args[0]->getType())->getNumElements();
Args[3] = getX86MaskVec(Builder, Args[3], NumElts);
NewCall = Builder.CreateCall(NewFn, Args);
Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, nullptr);
StringRef Name = CI->getName();
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we use getX86MaskVec here?

craig.topper: Can we use getX86MaskVec here?
pengfeiAuthorUnsubmitted
Done
ReplyInline Actions

Sure. It's more clean now. Thanks.

pengfei: Sure. It's more clean now. Thanks.
if (!Name.empty()) {
CI->setName(Name + ".old");
NewCall->setName(Name);
}
CI->replaceAllUsesWith(Res);
CI->eraseFromParent();
return;
}
case Intrinsic::thread_pointer: { case Intrinsic::thread_pointer: {
NewCall = Builder.CreateCall(NewFn, {}); NewCall = Builder.CreateCall(NewFn, {});
break; break;
} }
case Intrinsic::invariant_start: case Intrinsic::invariant_start:
case Intrinsic::invariant_end: case Intrinsic::invariant_end:
case Intrinsic::masked_load: case Intrinsic::masked_load:
▲ Show 20 Lines • Show All 587 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 507 Lines • ▼ Show 20 Lines#include "X86GenDAGISel.inc"
}; };
} }
// Returns true if this masked compare can be implemented legally with this // Returns true if this masked compare can be implemented legally with this
// type. // type.
static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) { static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {
unsigned Opcode = N->getOpcode(); unsigned Opcode = N->getOpcode();
if (Opcode == X86ISD::CMPM || Opcode == X86ISD::STRICT_CMPM || if (Opcode == X86ISD::CMPM || Opcode == X86ISD::CMPMM ||
Opcode == ISD::SETCC || Opcode == X86ISD::CMPM_SAE || Opcode == X86ISD::STRICT_CMPM || Opcode == ISD::SETCC ||
Opcode == X86ISD::VFPCLASS) { Opcode == X86ISD::CMPMM_SAE || Opcode == X86ISD::VFPCLASS) {
// We can get 256-bit 8 element types here without VLX being enabled. When // We can get 256-bit 8 element types here without VLX being enabled. When
// this happens we will use 512-bit operations and the mask will not be // this happens we will use 512-bit operations and the mask will not be
// zero extended. // zero extended.
EVT OpVT = N->getOperand(0).getValueType(); EVT OpVT = N->getOperand(0).getValueType();
// The first operand of X86ISD::STRICT_CMPM is chain, so we need to get the // The first operand of X86ISD::STRICT_CMPM is chain, so we need to get the
// second operand. // second operand.
if (Opcode == X86ISD::STRICT_CMPM) if (Opcode == X86ISD::STRICT_CMPM)
OpVT = N->getOperand(1).getValueType(); OpVT = N->getOperand(1).getValueType();
▲ Show 20 Lines • Show All 5,193 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ISelLowering.h

//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 370 Lines • ▼ Show 20 Lines enum NodeType : unsigned {
// v8i16 Horizontal minimum and position. // v8i16 Horizontal minimum and position.
PHMINPOS, PHMINPOS,
MULTISHIFT, MULTISHIFT,
/// Vector comparison generating mask bits for fp and /// Vector comparison generating mask bits for fp and
/// integer signed and unsigned data types. /// integer signed and unsigned data types.
CMPM, CMPM,
// Vector comparison with SAE for FP values // Vector mask comparison generating mask bits for FP values.
CMPM_SAE, CMPMM,
// Vector mask comparison with SAE for FP values.
CMPMM_SAE,
// Arithmetic operations with FLAGS results. // Arithmetic operations with FLAGS results.
ADD, ADD,
SUB, SUB,
ADC, ADC,
SBB, SBB,
SMUL, SMUL,
UMUL, UMUL,
▲ Show 20 Lines • Show All 1,306 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
Lint: Lint
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 24,697 Lines • ▼ Show 20 Lines case FPCLASSS: {
DAG.getConstant(0, dl, MVT::v8i1), DAG.getConstant(0, dl, MVT::v8i1),
FPclassMask, DAG.getIntPtrConstant(0, dl)); FPclassMask, DAG.getIntPtrConstant(0, dl));
return DAG.getBitcast(MVT::i8, Ins); return DAG.getBitcast(MVT::i8, Ins);
} }
case CMP_MASK_CC: { case CMP_MASK_CC: {
MVT MaskVT = Op.getSimpleValueType(); MVT MaskVT = Op.getSimpleValueType();
SDValue CC = Op.getOperand(3); SDValue CC = Op.getOperand(3);
SDValue Mask = Op.getOperand(4);
// We specify 2 possible opcodes for intrinsics with rounding modes. // We specify 2 possible opcodes for intrinsics with rounding modes.
// First, we check if the intrinsic may have non-default rounding mode, // First, we check if the intrinsic may have non-default rounding mode,
// (IntrData->Opc1 != 0), then we check the rounding mode operand. // (IntrData->Opc1 != 0), then we check the rounding mode operand.
if (IntrData->Opc1 != 0) { if (IntrData->Opc1 != 0) {
SDValue Sae = Op.getOperand(4); SDValue Sae = Op.getOperand(5);
if (isRoundModeSAE(Sae)) if (isRoundModeSAE(Sae))
return DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1), return DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
Op.getOperand(2), CC, Sae); Op.getOperand(2), CC, Mask, Sae);
if (!isRoundModeCurDirection(Sae)) if (!isRoundModeCurDirection(Sae))
return SDValue(); return SDValue();
} }
//default rounding mode //default rounding mode
return DAG.getNode(IntrData->Opc0, dl, MaskVT, return DAG.getNode(IntrData->Opc0, dl, MaskVT,
{Op.getOperand(1), Op.getOperand(2), CC}); {Op.getOperand(1), Op.getOperand(2), CC, Mask});
} }
case CMP_MASK_SCALAR_CC: { case CMP_MASK_SCALAR_CC: {
SDValue Src1 = Op.getOperand(1); SDValue Src1 = Op.getOperand(1);
SDValue Src2 = Op.getOperand(2); SDValue Src2 = Op.getOperand(2);
SDValue CC = Op.getOperand(3); SDValue CC = Op.getOperand(3);
SDValue Mask = Op.getOperand(4); SDValue Mask = Op.getOperand(4);
SDValue Cmp; SDValue Cmp;
▲ Show 20 Lines • Show All 5,569 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
NODE_NAME_CASE(BT) NODE_NAME_CASE(BT)
NODE_NAME_CASE(CMP) NODE_NAME_CASE(CMP)
NODE_NAME_CASE(FCMP) NODE_NAME_CASE(FCMP)
NODE_NAME_CASE(STRICT_FCMP) NODE_NAME_CASE(STRICT_FCMP)
NODE_NAME_CASE(STRICT_FCMPS) NODE_NAME_CASE(STRICT_FCMPS)
NODE_NAME_CASE(COMI) NODE_NAME_CASE(COMI)
NODE_NAME_CASE(UCOMI) NODE_NAME_CASE(UCOMI)
NODE_NAME_CASE(CMPM) NODE_NAME_CASE(CMPM)
NODE_NAME_CASE(CMPMM)
NODE_NAME_CASE(STRICT_CMPM) NODE_NAME_CASE(STRICT_CMPM)
NODE_NAME_CASE(CMPM_SAE) NODE_NAME_CASE(CMPMM_SAE)
NODE_NAME_CASE(SETCC) NODE_NAME_CASE(SETCC)
NODE_NAME_CASE(SETCC_CARRY) NODE_NAME_CASE(SETCC_CARRY)
NODE_NAME_CASE(FSETCC) NODE_NAME_CASE(FSETCC)
NODE_NAME_CASE(FSETCCM) NODE_NAME_CASE(FSETCCM)
NODE_NAME_CASE(FSETCCM_SAE) NODE_NAME_CASE(FSETCCM_SAE)
NODE_NAME_CASE(CMOV) NODE_NAME_CASE(CMOV)
NODE_NAME_CASE(BRCOND) NODE_NAME_CASE(BRCOND)
NODE_NAME_CASE(RET_FLAG) NODE_NAME_CASE(RET_FLAG)
▲ Show 20 Lines • Show All 20,073 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

//===-- X86InstCombineIntrinsic.cpp - X86 specific InstCombine pass -------===// //===-- X86InstCombineIntrinsic.cpp - X86 specific InstCombine pass -------===//
Lint: Lint
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
▲ Show 20 Lines • Show All 1,136 Lines • ▼ Show 20 Lines if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, 1)) {
IC.replaceOperand(II, 1, V); IC.replaceOperand(II, 1, V);
MadeChange = true; MadeChange = true;
} }
if (MadeChange) { if (MadeChange) {
return &II; return &II;
} }
break; break;
} }
case Intrinsic::x86_avx512_cmp_pd_128:
case Intrinsic::x86_avx512_cmp_pd_256:
case Intrinsic::x86_avx512_cmp_pd_512:
case Intrinsic::x86_avx512_cmp_ps_128:
case Intrinsic::x86_avx512_cmp_ps_256:
case Intrinsic::x86_avx512_cmp_ps_512: {
// Folding cmp(sub(a,b),0) -> cmp(a,b) and cmp(0,sub(a,b)) -> cmp(b,a)
Value *Arg0 = II.getArgOperand(0);
Value *Arg1 = II.getArgOperand(1);
bool Arg0IsZero = match(Arg0, PatternMatch::m_PosZeroFP());
if (Arg0IsZero)
std::swap(Arg0, Arg1);
Value *A, *B;
// This fold requires only the NINF(not +/- inf) since inf minus
// inf is nan.
// NSZ(No Signed Zeros) is not needed because zeros of any sign are
// equal for both compares.
// NNAN is not needed because nans compare the same for both compares.
// The compare intrinsic uses the above assumptions and therefore
// doesn't require additional flags.
if ((match(Arg0,
PatternMatch::m_OneUse(PatternMatch::m_FSub(
PatternMatch::m_Value(A), PatternMatch::m_Value(B)))) &&
match(Arg1, PatternMatch::m_PosZeroFP()) && isa<Instruction>(Arg0) &&
cast<Instruction>(Arg0)->getFastMathFlags().noInfs())) {
if (Arg0IsZero)
std::swap(A, B);
IC.replaceOperand(II, 0, A);
IC.replaceOperand(II, 1, B);
return &II;
}
break;
}
case Intrinsic::x86_avx512_add_ps_512: case Intrinsic::x86_avx512_add_ps_512:
case Intrinsic::x86_avx512_div_ps_512: case Intrinsic::x86_avx512_div_ps_512:
case Intrinsic::x86_avx512_mul_ps_512: case Intrinsic::x86_avx512_mul_ps_512:
case Intrinsic::x86_avx512_sub_ps_512: case Intrinsic::x86_avx512_sub_ps_512:
case Intrinsic::x86_avx512_add_pd_512: case Intrinsic::x86_avx512_add_pd_512:
case Intrinsic::x86_avx512_div_pd_512: case Intrinsic::x86_avx512_div_pd_512:
case Intrinsic::x86_avx512_mul_pd_512: case Intrinsic::x86_avx512_mul_pd_512:
▲ Show 20 Lines • Show All 811 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,488 Lines • ▼ Show 20 Linesdefm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86pcmpum, X86pcmpum_su,
X86pcmpum_commute, X86pcmpum_commute_su, X86pcmpum_commute, X86pcmpum_commute_su,
SchedWriteVecALU, avx512vl_i64_info, SchedWriteVecALU, avx512vl_i64_info,
HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
def X86cmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), def X86cmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc),
(X86cmpm node:$src1, node:$src2, node:$cc), [{ (X86cmpm node:$src1, node:$src2, node:$cc), [{
return N->hasOneUse(); return N->hasOneUse();
}]>; }]>;
def X86cmpmSAE_su : PatFrag<(ops node:$src1, node:$src2, node:$cc),
(X86cmpmSAE node:$src1, node:$src2, node:$cc), [{
return N->hasOneUse();
}]>;
def X86cmpm_imm_commute : SDNodeXForm<timm, [{ def X86cmpm_imm_commute : SDNodeXForm<timm, [{
uint8_t Imm = X86::getSwappedVCMPImm(N->getZExtValue() & 0x1f); uint8_t Imm = X86::getSwappedVCMPImm(N->getZExtValue() & 0x1f);
return getI8Imm(Imm, SDLoc(N)); return getI8Imm(Imm, SDLoc(N));
}]>; }]>;
multiclass avx512_vcmp_common<X86FoldableSchedWrite sched, X86VectorVTInfo _, multiclass avx512_vcmp_common<X86FoldableSchedWrite sched, X86VectorVTInfo _,
string Name> { string Name> {
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines def : Pat<(X86any_cmpm (_.BroadcastLdFrag addr:$src2),
(X86cmpm_imm_commute timm:$cc))>; (X86cmpm_imm_commute timm:$cc))>;
def : Pat<(and _.KRCWM:$mask, (X86cmpm_su (_.BroadcastLdFrag addr:$src2), def : Pat<(and _.KRCWM:$mask, (X86cmpm_su (_.BroadcastLdFrag addr:$src2),
(_.VT _.RC:$src1), (_.VT _.RC:$src1),
timm:$cc)), timm:$cc)),
(!cast<Instruction>(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask, (!cast<Instruction>(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask,
_.RC:$src1, addr:$src2, _.RC:$src1, addr:$src2,
(X86cmpm_imm_commute timm:$cc))>; (X86cmpm_imm_commute timm:$cc))>;
// Patterns for mask intrinsics.
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc,
(_.KVT immAllOnesV)),
(!cast<Instruction>(Name#_.ZSuffix#"rri") _.RC:$src1, _.RC:$src2, timm:$cc)>;
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc, _.KRCWM:$mask),
(!cast<Instruction>(Name#_.ZSuffix#"rrik") _.KRCWM:$mask, _.RC:$src1,
_.RC:$src2, timm:$cc)>;
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)), timm:$cc,
(_.KVT immAllOnesV)),
(!cast<Instruction>(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2, timm:$cc)>;
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)), timm:$cc,
_.KRCWM:$mask),
(!cast<Instruction>(Name#_.ZSuffix#"rmik") _.KRCWM:$mask, _.RC:$src1,
addr:$src2, timm:$cc)>;
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.BroadcastLdFrag addr:$src2)), timm:$cc,
(_.KVT immAllOnesV)),
(!cast<Instruction>(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2, timm:$cc)>;
def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.BroadcastLdFrag addr:$src2)), timm:$cc,
_.KRCWM:$mask),
(!cast<Instruction>(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask, _.RC:$src1,
addr:$src2, timm:$cc)>;
// Patterns for mask intrinsics with loads in other operand.
def : Pat<(X86cmpmm (_.VT (_.LdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
(_.KVT immAllOnesV)),
(!cast<Instruction>(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
(X86cmpm_imm_commute timm:$cc))>;
def : Pat<(X86cmpmm (_.VT (_.LdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
_.KRCWM:$mask),
(!cast<Instruction>(Name#_.ZSuffix#"rmik") _.KRCWM:$mask,
_.RC:$src1, addr:$src2,
(X86cmpm_imm_commute timm:$cc))>;
def : Pat<(X86cmpmm (_.VT (_.BroadcastLdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
(_.KVT immAllOnesV)),
(!cast<Instruction>(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2,
(X86cmpm_imm_commute timm:$cc))>;
def : Pat<(X86cmpmm (_.VT (_.BroadcastLdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
_.KRCWM:$mask),
(!cast<Instruction>(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask,
_.RC:$src1, addr:$src2,
(X86cmpm_imm_commute timm:$cc))>;
} }
multiclass avx512_vcmp_sae<X86FoldableSchedWrite sched, X86VectorVTInfo _> { multiclass avx512_vcmp_sae<X86FoldableSchedWrite sched, X86VectorVTInfo _> {
// comparison code form (VCMP[EQ/LT/LE/...] // comparison code form (VCMP[EQ/LT/LE/...]
let Uses = [MXCSR] in let Uses = [MXCSR] in
defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, defm rrib : AVX512_maskable_custom_cmp<0xC2, MRMSrcReg, (outs _.KRC:$dst),
(outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, u8imm:$cc), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
(ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2, u8imm:$cc),
"vcmp"#_.Suffix, "vcmp"#_.Suffix,
"$cc, {sae}, $src2, $src1", "$cc, {sae}, $src2, $src1",
"$src1, $src2, {sae}, $cc", "$src1, $src2, {sae}, $cc",
(X86cmpmSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc), [(set _.KRC:$dst, (X86cmpmmSAE (_.VT _.RC:$src1),
(X86cmpmSAE_su (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT _.RC:$src2), timm:$cc, (_.KVT immAllOnesV)))],
timm:$cc)>, [(set _.KRC:$dst, (X86cmpmmSAE (_.VT _.RC:$src1),
(_.VT _.RC:$src2), timm:$cc, _.KRCWM:$mask))]>,
EVEX_B, Sched<[sched]>; EVEX_B, Sched<[sched]>;
} }
multiclass avx512_vcmp<X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> { multiclass avx512_vcmp<X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> {
let Predicates = [HasAVX512] in { let Predicates = [HasAVX512] in {
defm Z : avx512_vcmp_common<sched.ZMM, _.info512, NAME>, defm Z : avx512_vcmp_common<sched.ZMM, _.info512, NAME>,
avx512_vcmp_sae<sched.ZMM, _.info512>, EVEX_V512; avx512_vcmp_sae<sched.ZMM, _.info512>, EVEX_V512;
▲ Show 20 Lines • Show All 10,086 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3), def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[(X86strict_cmpp node:$src1, node:$src2, node:$src3), [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
(X86cmpp node:$src1, node:$src2, node:$src3)]>; (X86cmpp node:$src1, node:$src2, node:$src3)]>;
def X86CmpMaskCC : def X86CmpMaskCC :
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisSameAs<2, 1>, SDTCisVec<1>, SDTCisSameAs<2, 1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
def X86MaskCmpMaskCC :
SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisSameAs<2, 1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>, SDTCisSameAs<4, 0>]>;
def X86CmpMaskCCScalar : def X86CmpMaskCCScalar :
SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>]>; SDTCisVT<3, i8>]>;
def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
def X86cmpmm : SDNode<"X86ISD::CMPMM", X86MaskCmpMaskCC>;
def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>; def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>;
def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3), def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[(X86strict_cmpm node:$src1, node:$src2, node:$src3), [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
(X86cmpm node:$src1, node:$src2, node:$src3)]>; (X86cmpm node:$src1, node:$src2, node:$src3)]>;
def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>; def X86cmpmmSAE : SDNode<"X86ISD::CMPMM_SAE", X86MaskCmpMaskCC>;
def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>;
def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>; def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>;
def X86phminpos: SDNode<"X86ISD::PHMINPOS", def X86phminpos: SDNode<"X86ISD::PHMINPOS",
SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
SDTCisVec<2>, SDTCisInt<0>, SDTCisVec<2>, SDTCisInt<0>,
▲ Show 20 Lines • Show All 960 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86IntrinsicsInfo.h

//===-- X86IntrinsicsInfo.h - X86 Intrinsics ------------*- C++ -*-===// //===-- X86IntrinsicsInfo.h - X86 Intrinsics ------------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 322 Lines • ▼ Show 20 Lines if (Data != std::end(IntrinsicsWithChain) && Data->Id == IntNo)
return Data; return Data;
return nullptr; return nullptr;
} }
/* /*
* IntrinsicsWithoutChain - the table should be sorted by Intrinsic ID - in * IntrinsicsWithoutChain - the table should be sorted by Intrinsic ID - in
* the alphabetical order. * the alphabetical order.
*/ */
static const IntrinsicData IntrinsicsWithoutChain[] = { static const IntrinsicData IntrinsicsWithoutChain[] = {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-static const IntrinsicData  IntrinsicsWithoutChain[] = {
-  X86_INTRINSIC_DATA(addcarry_32,       ADX, X86ISD::ADC, X86ISD::ADD),
-  X86_INTRINSIC_DATA(addcarry_64,       ADX, X86ISD::ADC, X86ISD::ADD),
-  X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
-  X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
-  X86_INTRINSIC_DATA(avx_blendv_pd_256, BLENDV, X86ISD::BLENDV, 0),
-  X86_INTRINSIC_DATA(avx_blendv_ps_256, BLENDV, X86ISD::BLENDV, 0),
-  X86_INTRINSIC_DATA(avx_cmp_pd_256,    INTR_TYPE_3OP, X86ISD::CMPP, 0),
-  X86_INTRINSIC_DATA(avx_cmp_ps_256,    INTR_TYPE_3OP, X86ISD::CMPP, 0),
-  X86_INTRINSIC_DATA(avx_cvt_pd2_ps_256,INTR_TYPE_1OP, X86ISD::VFPROUND, 0),

299 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -static const IntrinsicData IntrinsicsWithoutChain…
X86_INTRINSIC_DATA(addcarry_32, ADX, X86ISD::ADC, X86ISD::ADD), X86_INTRINSIC_DATA(addcarry_32, ADX, X86ISD::ADC, X86ISD::ADD),
X86_INTRINSIC_DATA(addcarry_64, ADX, X86ISD::ADC, X86ISD::ADD), X86_INTRINSIC_DATA(addcarry_64, ADX, X86ISD::ADC, X86ISD::ADD),
X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0), X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0), X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
X86_INTRINSIC_DATA(avx_blendv_pd_256, BLENDV, X86ISD::BLENDV, 0), X86_INTRINSIC_DATA(avx_blendv_pd_256, BLENDV, X86ISD::BLENDV, 0),
X86_INTRINSIC_DATA(avx_blendv_ps_256, BLENDV, X86ISD::BLENDV, 0), X86_INTRINSIC_DATA(avx_blendv_ps_256, BLENDV, X86ISD::BLENDV, 0),
X86_INTRINSIC_DATA(avx_cmp_pd_256, INTR_TYPE_3OP, X86ISD::CMPP, 0), X86_INTRINSIC_DATA(avx_cmp_pd_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
X86_INTRINSIC_DATA(avx_cmp_ps_256, INTR_TYPE_3OP, X86ISD::CMPP, 0), X86_INTRINSIC_DATA(avx_cmp_ps_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesstatic const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx2_psrli_q, VSHIFT, X86ISD::VSRLI, 0), X86_INTRINSIC_DATA(avx2_psrli_q, VSHIFT, X86ISD::VSRLI, 0),
X86_INTRINSIC_DATA(avx2_psrli_w, VSHIFT, X86ISD::VSRLI, 0), X86_INTRINSIC_DATA(avx2_psrli_w, VSHIFT, X86ISD::VSRLI, 0),
X86_INTRINSIC_DATA(avx2_psrlv_d, INTR_TYPE_2OP, X86ISD::VSRLV, 0), X86_INTRINSIC_DATA(avx2_psrlv_d, INTR_TYPE_2OP, X86ISD::VSRLV, 0),
X86_INTRINSIC_DATA(avx2_psrlv_d_256, INTR_TYPE_2OP, X86ISD::VSRLV, 0), X86_INTRINSIC_DATA(avx2_psrlv_d_256, INTR_TYPE_2OP, X86ISD::VSRLV, 0),
X86_INTRINSIC_DATA(avx2_psrlv_q, INTR_TYPE_2OP, X86ISD::VSRLV, 0), X86_INTRINSIC_DATA(avx2_psrlv_q, INTR_TYPE_2OP, X86ISD::VSRLV, 0),
X86_INTRINSIC_DATA(avx2_psrlv_q_256, INTR_TYPE_2OP, X86ISD::VSRLV, 0), X86_INTRINSIC_DATA(avx2_psrlv_q_256, INTR_TYPE_2OP, X86ISD::VSRLV, 0),
X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND), X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND), X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
X86_INTRINSIC_DATA(avx512_cmp_pd_128, CMP_MASK_CC, X86ISD::CMPM, 0),
X86_INTRINSIC_DATA(avx512_cmp_pd_256, CMP_MASK_CC, X86ISD::CMPM, 0),
X86_INTRINSIC_DATA(avx512_cmp_pd_512, CMP_MASK_CC, X86ISD::CMPM, X86ISD::CMPM_SAE),
X86_INTRINSIC_DATA(avx512_cmp_ps_128, CMP_MASK_CC, X86ISD::CMPM, 0),
X86_INTRINSIC_DATA(avx512_cmp_ps_256, CMP_MASK_CC, X86ISD::CMPM, 0),
X86_INTRINSIC_DATA(avx512_cmp_ps_512, CMP_MASK_CC, X86ISD::CMPM, X86ISD::CMPM_SAE),
X86_INTRINSIC_DATA(avx512_conflict_d_128, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_d_128, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_conflict_d_256, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_d_256, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_conflict_d_512, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_d_512, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_conflict_q_128, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_q_128, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_conflict_q_256, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_q_256, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_conflict_q_512, INTR_TYPE_1OP, X86ISD::CONFLICT, 0), X86_INTRINSIC_DATA(avx512_conflict_q_512, INTR_TYPE_1OP, X86ISD::CONFLICT, 0),
X86_INTRINSIC_DATA(avx512_cvtsi2sd64, INTR_TYPE_2OP, X86ISD::SCALAR_SINT_TO_FP, X86ISD::SCALAR_SINT_TO_FP_RND), X86_INTRINSIC_DATA(avx512_cvtsi2sd64, INTR_TYPE_2OP, X86ISD::SCALAR_SINT_TO_FP, X86ISD::SCALAR_SINT_TO_FP_RND),
X86_INTRINSIC_DATA(avx512_cvtsi2ss32, INTR_TYPE_2OP, X86ISD::SCALAR_SINT_TO_FP, X86ISD::SCALAR_SINT_TO_FP_RND), X86_INTRINSIC_DATA(avx512_cvtsi2ss32, INTR_TYPE_2OP, X86ISD::SCALAR_SINT_TO_FP, X86ISD::SCALAR_SINT_TO_FP_RND),
Show All 25 Linesstatic const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx512_kadd_b, INTR_TYPE_2OP, X86ISD::KADD, 0), X86_INTRINSIC_DATA(avx512_kadd_b, INTR_TYPE_2OP, X86ISD::KADD, 0),
X86_INTRINSIC_DATA(avx512_kadd_d, INTR_TYPE_2OP, X86ISD::KADD, 0), X86_INTRINSIC_DATA(avx512_kadd_d, INTR_TYPE_2OP, X86ISD::KADD, 0),
X86_INTRINSIC_DATA(avx512_kadd_q, INTR_TYPE_2OP, X86ISD::KADD, 0), X86_INTRINSIC_DATA(avx512_kadd_q, INTR_TYPE_2OP, X86ISD::KADD, 0),
X86_INTRINSIC_DATA(avx512_kadd_w, INTR_TYPE_2OP, X86ISD::KADD, 0), X86_INTRINSIC_DATA(avx512_kadd_w, INTR_TYPE_2OP, X86ISD::KADD, 0),
X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK, X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK,
X86ISD::FADDS, X86ISD::FADDS_RND), X86ISD::FADDS, X86ISD::FADDS_RND),
X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK, X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK,
X86ISD::FADDS, X86ISD::FADDS_RND), X86ISD::FADDS, X86ISD::FADDS_RND),
X86_INTRINSIC_DATA(avx512_mask_cmp_pd_128, CMP_MASK_CC, X86ISD::CMPMM, 0),
X86_INTRINSIC_DATA(avx512_mask_cmp_pd_256, CMP_MASK_CC, X86ISD::CMPMM, 0),
X86_INTRINSIC_DATA(avx512_mask_cmp_pd_512, CMP_MASK_CC, X86ISD::CMPMM, X86ISD::CMPMM_SAE),
X86_INTRINSIC_DATA(avx512_mask_cmp_ps_128, CMP_MASK_CC, X86ISD::CMPMM, 0),
X86_INTRINSIC_DATA(avx512_mask_cmp_ps_256, CMP_MASK_CC, X86ISD::CMPMM, 0),
X86_INTRINSIC_DATA(avx512_mask_cmp_ps_512, CMP_MASK_CC, X86ISD::CMPMM, X86ISD::CMPMM_SAE),
X86_INTRINSIC_DATA(avx512_mask_cmp_sd, CMP_MASK_SCALAR_CC, X86_INTRINSIC_DATA(avx512_mask_cmp_sd, CMP_MASK_SCALAR_CC,
X86ISD::FSETCCM, X86ISD::FSETCCM_SAE), X86ISD::FSETCCM, X86ISD::FSETCCM_SAE),
X86_INTRINSIC_DATA(avx512_mask_cmp_ss, CMP_MASK_SCALAR_CC, X86_INTRINSIC_DATA(avx512_mask_cmp_ss, CMP_MASK_SCALAR_CC,
X86ISD::FSETCCM, X86ISD::FSETCCM_SAE), X86ISD::FSETCCM, X86ISD::FSETCCM_SAE),
X86_INTRINSIC_DATA(avx512_mask_compress, COMPRESS_EXPAND_IN_REG, X86_INTRINSIC_DATA(avx512_mask_compress, COMPRESS_EXPAND_IN_REG,
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(avx512_mask_compress,        COMPRESS_EXPAND_IN_REG,
-                     X86ISD::COMPRESS, 0),
-  X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2DQ_MASK,
-                     X86ISD::CVTP2SI, X86ISD::MCVTP2SI),
-  X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
-                     X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
-  X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps,     CVTPD2PS_MASK,
-                     X86ISD::VFPROUND, X86ISD::VMFPROUND),
-  X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, INTR_TYPE_1OP_MASK,
-                     X86ISD::VFPROUND, X86ISD::VFPROUND_RND),

664 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(avx512_mask_compress…
X86ISD::COMPRESS, 0), X86ISD::COMPRESS, 0),
X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2DQ_MASK, X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2DQ_MASK,
X86ISD::CVTP2SI, X86ISD::MCVTP2SI), X86ISD::CVTP2SI, X86ISD::MCVTP2SI),
X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK, X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND), X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, CVTPD2PS_MASK, X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, CVTPD2PS_MASK,
X86ISD::VFPROUND, X86ISD::VMFPROUND), X86ISD::VFPROUND, X86ISD::VMFPROUND),
X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, INTR_TYPE_1OP_MASK, X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, INTR_TYPE_1OP_MASK,
▲ Show 20 Lines • Show All 306 Lines • ▼ Show 20 Lines X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_512, INTR_TYPE_1OP_MASK_SAE,
X86ISD::CVTPH2PS, X86ISD::CVTPH2PS_SAE), X86ISD::CVTPH2PS, X86ISD::CVTPH2PS_SAE),
X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_128, CVTPS2PH_MASK, X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_128, CVTPS2PH_MASK,
X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH), X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH),
X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_256, CVTPS2PH_MASK, X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_256, CVTPS2PH_MASK,
X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH), X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH),
X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_512, CVTPS2PH_MASK, X86_INTRINSIC_DATA(avx512_mask_vcvtps2ph_512, CVTPS2PH_MASK,
X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH), X86ISD::CVTPS2PH, X86ISD::MCVTPS2PH),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128, FIXUPIMM_MASKZ,
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128, FIXUPIMM_MASKZ,
-                     X86ISD::VFIXUPIMM, 0),
-  X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_256, FIXUPIMM_MASKZ,
-                     X86ISD::VFIXUPIMM, 0),
-  X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_512, FIXUPIMM_MASKZ,
-                     X86ISD::VFIXUPIMM, X86ISD::VFIXUPIMM_SAE),
-  X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_128, FIXUPIMM_MASKZ,
-                     X86ISD::VFIXUPIMM, 0),
-  X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_256, FIXUPIMM_MASKZ,
-                     X86ISD::VFIXUPIMM, 0),

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_128…
X86ISD::VFIXUPIMM, 0), X86ISD::VFIXUPIMM, 0),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_256, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_256, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMM, 0), X86ISD::VFIXUPIMM, 0),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_512, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_pd_512, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMM, X86ISD::VFIXUPIMM_SAE), X86ISD::VFIXUPIMM, X86ISD::VFIXUPIMM_SAE),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_128, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_128, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMM, 0), X86ISD::VFIXUPIMM, 0),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_256, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_256, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMM, 0), X86ISD::VFIXUPIMM, 0),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_512, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ps_512, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMM, X86ISD::VFIXUPIMM_SAE), X86ISD::VFIXUPIMM, X86ISD::VFIXUPIMM_SAE),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_sd, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_sd, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMMS, X86ISD::VFIXUPIMMS_SAE), X86ISD::VFIXUPIMMS, X86ISD::VFIXUPIMMS_SAE),
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ss, FIXUPIMM_MASKZ, X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ss, FIXUPIMM_MASKZ,
X86ISD::VFIXUPIMMS, X86ISD::VFIXUPIMMS_SAE), X86ISD::VFIXUPIMMS, X86ISD::VFIXUPIMMS_SAE),
X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE), X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
-  X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
-  X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
-  X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
-  X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
-  X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
-  X86_INTRINSIC_DATA(avx512_packssdw_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
-  X86_INTRINSIC_DATA(avx512_packsswb_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
-  X86_INTRINSIC_DATA(avx512_packusdw_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
-  X86_INTRINSIC_DATA(avx512_packuswb_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0),

302 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(avx512_max_pd_512…
X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE), X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE), X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE), X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND), X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND), X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
X86_INTRINSIC_DATA(avx512_packssdw_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0), X86_INTRINSIC_DATA(avx512_packssdw_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
X86_INTRINSIC_DATA(avx512_packsswb_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0), X86_INTRINSIC_DATA(avx512_packsswb_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
X86_INTRINSIC_DATA(avx512_packusdw_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0), X86_INTRINSIC_DATA(avx512_packusdw_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Linesstatic const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
X86_INTRINSIC_DATA(avx512_vfmaddsub_pd_512, INTR_TYPE_3OP, X86ISD::FMADDSUB, X86_INTRINSIC_DATA(avx512_vfmaddsub_pd_512, INTR_TYPE_3OP, X86ISD::FMADDSUB,
X86ISD::FMADDSUB_RND), X86ISD::FMADDSUB_RND),
X86_INTRINSIC_DATA(avx512_vfmaddsub_ps_512, INTR_TYPE_3OP, X86ISD::FMADDSUB, X86_INTRINSIC_DATA(avx512_vfmaddsub_ps_512, INTR_TYPE_3OP, X86ISD::FMADDSUB,
X86ISD::FMADDSUB_RND), X86ISD::FMADDSUB_RND),
X86_INTRINSIC_DATA(avx512_vpdpbusd_128, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0), X86_INTRINSIC_DATA(avx512_vpdpbusd_128, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(avx512_vpdpbusd_128,  INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpbusd_256,  INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpbusd_512,  INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpbusds_128, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpbusds_256, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpbusds_512, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpwssd_128,  INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpwssd_256,  INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpwssd_512,  INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
-  X86_INTRINSIC_DATA(avx512_vpdpwssds_128, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0),

20 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(avx512_vpdpbusd_128…
X86_INTRINSIC_DATA(avx512_vpdpbusd_256, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0), X86_INTRINSIC_DATA(avx512_vpdpbusd_256, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
X86_INTRINSIC_DATA(avx512_vpdpbusd_512, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0), X86_INTRINSIC_DATA(avx512_vpdpbusd_512, INTR_TYPE_3OP, X86ISD::VPDPBUSD, 0),
X86_INTRINSIC_DATA(avx512_vpdpbusds_128, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpbusds_128, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
X86_INTRINSIC_DATA(avx512_vpdpbusds_256, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpbusds_256, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
X86_INTRINSIC_DATA(avx512_vpdpbusds_512, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpbusds_512, INTR_TYPE_3OP, X86ISD::VPDPBUSDS, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssd_128, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0), X86_INTRINSIC_DATA(avx512_vpdpwssd_128, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssd_256, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0), X86_INTRINSIC_DATA(avx512_vpdpwssd_256, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssd_512, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0), X86_INTRINSIC_DATA(avx512_vpdpwssd_512, INTR_TYPE_3OP, X86ISD::VPDPWSSD, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssds_128, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpwssds_128, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssds_256, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpwssds_256, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0),
X86_INTRINSIC_DATA(avx512_vpdpwssds_512, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0), X86_INTRINSIC_DATA(avx512_vpdpwssds_512, INTR_TYPE_3OP, X86ISD::VPDPWSSDS, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_d_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_d_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(avx512_vpermi2var_d_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_d_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_d_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_hi_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_hi_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_hi_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_pd_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_pd_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_pd_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
-  X86_INTRINSIC_DATA(avx512_vpermi2var_ps_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),

349 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(avx512_vpermi2var_d_128…
X86_INTRINSIC_DATA(avx512_vpermi2var_d_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_d_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_d_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_d_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_hi_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_hi_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_hi_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_hi_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_hi_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_hi_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_pd_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_pd_128, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_pd_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_pd_256, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
X86_INTRINSIC_DATA(avx512_vpermi2var_pd_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0), X86_INTRINSIC_DATA(avx512_vpermi2var_pd_512, INTR_TYPE_3OP, X86ISD::VPERMV3, 0),
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Linesstatic const IntrinsicData IntrinsicsWithoutChain[] = {
X86_INTRINSIC_DATA(ssse3_pshuf_b_128, INTR_TYPE_2OP, X86ISD::PSHUFB, 0), X86_INTRINSIC_DATA(ssse3_pshuf_b_128, INTR_TYPE_2OP, X86ISD::PSHUFB, 0),
X86_INTRINSIC_DATA(subborrow_32, ADX, X86ISD::SBB, X86ISD::SUB), X86_INTRINSIC_DATA(subborrow_32, ADX, X86ISD::SBB, X86ISD::SUB),
X86_INTRINSIC_DATA(subborrow_64, ADX, X86ISD::SBB, X86ISD::SUB), X86_INTRINSIC_DATA(subborrow_64, ADX, X86ISD::SBB, X86ISD::SUB),
X86_INTRINSIC_DATA(tbm_bextri_u32, BEXTRI, X86ISD::BEXTR, 0), X86_INTRINSIC_DATA(tbm_bextri_u32, BEXTRI, X86ISD::BEXTR, 0),
X86_INTRINSIC_DATA(tbm_bextri_u64, BEXTRI, X86ISD::BEXTR, 0), X86_INTRINSIC_DATA(tbm_bextri_u64, BEXTRI, X86ISD::BEXTR, 0),
X86_INTRINSIC_DATA(vcvtps2ph_128, INTR_TYPE_2OP, X86ISD::CVTPS2PH, 0), X86_INTRINSIC_DATA(vcvtps2ph_128, INTR_TYPE_2OP, X86ISD::CVTPS2PH, 0),
X86_INTRINSIC_DATA(vcvtps2ph_256, INTR_TYPE_2OP, X86ISD::CVTPS2PH, 0), X86_INTRINSIC_DATA(vcvtps2ph_256, INTR_TYPE_2OP, X86ISD::CVTPS2PH, 0),
X86_INTRINSIC_DATA(vgf2p8affineinvqb_128, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineinvqb_128, INTR_TYPE_3OP,
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(vgf2p8affineinvqb_128, INTR_TYPE_3OP,
-                     X86ISD::GF2P8AFFINEINVQB, 0),
-  X86_INTRINSIC_DATA(vgf2p8affineinvqb_256, INTR_TYPE_3OP,
-                     X86ISD::GF2P8AFFINEINVQB, 0),
-  X86_INTRINSIC_DATA(vgf2p8affineinvqb_512, INTR_TYPE_3OP,
-                     X86ISD::GF2P8AFFINEINVQB, 0),
-  X86_INTRINSIC_DATA(vgf2p8affineqb_128, INTR_TYPE_3OP,
-                     X86ISD::GF2P8AFFINEQB, 0),
-  X86_INTRINSIC_DATA(vgf2p8affineqb_256, INTR_TYPE_3OP,
-                     X86ISD::GF2P8AFFINEQB, 0),

23 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(vgf2p8affineinvqb_128…
X86ISD::GF2P8AFFINEINVQB, 0), X86ISD::GF2P8AFFINEINVQB, 0),
X86_INTRINSIC_DATA(vgf2p8affineinvqb_256, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineinvqb_256, INTR_TYPE_3OP,
X86ISD::GF2P8AFFINEINVQB, 0), X86ISD::GF2P8AFFINEINVQB, 0),
X86_INTRINSIC_DATA(vgf2p8affineinvqb_512, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineinvqb_512, INTR_TYPE_3OP,
X86ISD::GF2P8AFFINEINVQB, 0), X86ISD::GF2P8AFFINEINVQB, 0),
X86_INTRINSIC_DATA(vgf2p8affineqb_128, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineqb_128, INTR_TYPE_3OP,
X86ISD::GF2P8AFFINEQB, 0), X86ISD::GF2P8AFFINEQB, 0),
X86_INTRINSIC_DATA(vgf2p8affineqb_256, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineqb_256, INTR_TYPE_3OP,
X86ISD::GF2P8AFFINEQB, 0), X86ISD::GF2P8AFFINEQB, 0),
X86_INTRINSIC_DATA(vgf2p8affineqb_512, INTR_TYPE_3OP, X86_INTRINSIC_DATA(vgf2p8affineqb_512, INTR_TYPE_3OP,
X86ISD::GF2P8AFFINEQB, 0), X86ISD::GF2P8AFFINEQB, 0),
X86_INTRINSIC_DATA(vgf2p8mulb_128, INTR_TYPE_2OP, X86_INTRINSIC_DATA(vgf2p8mulb_128, INTR_TYPE_2OP,
X86ISD::GF2P8MULB, 0), X86ISD::GF2P8MULB, 0),
X86_INTRINSIC_DATA(vgf2p8mulb_256, INTR_TYPE_2OP, X86_INTRINSIC_DATA(vgf2p8mulb_256, INTR_TYPE_2OP,
X86ISD::GF2P8MULB, 0), X86ISD::GF2P8MULB, 0),
X86_INTRINSIC_DATA(vgf2p8mulb_512, INTR_TYPE_2OP, X86_INTRINSIC_DATA(vgf2p8mulb_512, INTR_TYPE_2OP,
X86ISD::GF2P8MULB, 0), X86ISD::GF2P8MULB, 0),
X86_INTRINSIC_DATA(xop_vpermil2pd, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0), X86_INTRINSIC_DATA(xop_vpermil2pd, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  X86_INTRINSIC_DATA(xop_vpermil2pd,     INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
-  X86_INTRINSIC_DATA(xop_vpermil2pd_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
-  X86_INTRINSIC_DATA(xop_vpermil2ps,     INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
-  X86_INTRINSIC_DATA(xop_vpermil2ps_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
-  X86_INTRINSIC_DATA(xop_vpperm,        INTR_TYPE_3OP, X86ISD::VPPERM, 0),
-  X86_INTRINSIC_DATA(xop_vpshab,        INTR_TYPE_2OP, X86ISD::VPSHA, 0),
-  X86_INTRINSIC_DATA(xop_vpshad,        INTR_TYPE_2OP, X86ISD::VPSHA, 0),
-  X86_INTRINSIC_DATA(xop_vpshaq,        INTR_TYPE_2OP, X86ISD::VPSHA, 0),
-  X86_INTRINSIC_DATA(xop_vpshaw,        INTR_TYPE_2OP, X86ISD::VPSHA, 0),
-  X86_INTRINSIC_DATA(xop_vpshlb,        INTR_TYPE_2OP, X86ISD::VPSHL, 0),

17 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86_INTRINSIC_DATA(xop_vpermil2pd…
X86_INTRINSIC_DATA(xop_vpermil2pd_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0), X86_INTRINSIC_DATA(xop_vpermil2pd_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
X86_INTRINSIC_DATA(xop_vpermil2ps, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0), X86_INTRINSIC_DATA(xop_vpermil2ps, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
X86_INTRINSIC_DATA(xop_vpermil2ps_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0), X86_INTRINSIC_DATA(xop_vpermil2ps_256, INTR_TYPE_4OP, X86ISD::VPERMIL2, 0),
X86_INTRINSIC_DATA(xop_vpperm, INTR_TYPE_3OP, X86ISD::VPPERM, 0), X86_INTRINSIC_DATA(xop_vpperm, INTR_TYPE_3OP, X86ISD::VPPERM, 0),
X86_INTRINSIC_DATA(xop_vpshab, INTR_TYPE_2OP, X86ISD::VPSHA, 0), X86_INTRINSIC_DATA(xop_vpshab, INTR_TYPE_2OP, X86ISD::VPSHA, 0),
X86_INTRINSIC_DATA(xop_vpshad, INTR_TYPE_2OP, X86ISD::VPSHA, 0), X86_INTRINSIC_DATA(xop_vpshad, INTR_TYPE_2OP, X86ISD::VPSHA, 0),
X86_INTRINSIC_DATA(xop_vpshaq, INTR_TYPE_2OP, X86ISD::VPSHA, 0), X86_INTRINSIC_DATA(xop_vpshaq, INTR_TYPE_2OP, X86ISD::VPSHA, 0),
X86_INTRINSIC_DATA(xop_vpshaw, INTR_TYPE_2OP, X86ISD::VPSHA, 0), X86_INTRINSIC_DATA(xop_vpshaw, INTR_TYPE_2OP, X86ISD::VPSHA, 0),
Show All 34 Lines

llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll

Show All 16 Lines
; CHECK-NEXT: vcmpgeps %zmm4, %zmm2, %k1 ; CHECK-NEXT: vcmpgeps %zmm4, %zmm2, %k1
; CHECK-NEXT: vcmpgeps %zmm4, %zmm3, %k2 ; CHECK-NEXT: vcmpgeps %zmm4, %zmm3, %k2
; CHECK-NEXT: korw %k2, %k1, %k1 ; CHECK-NEXT: korw %k2, %k1, %k1
; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, i32 4) %0 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%1 = bitcast <16 x i1> %0 to i16 %1 = bitcast <16 x i1> %0 to i16
%2 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %b, <16 x float> %x, i32 13, i32 4) %2 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %b, <16 x float> %x, i32 13, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%3 = bitcast <16 x i1> %2 to i16 %3 = bitcast <16 x i1> %2 to i16
%4 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %c, <16 x float> %x, i32 13, i32 4) %4 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %c, <16 x float> %x, i32 13, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%5 = bitcast <16 x i1> %4 to i16 %5 = bitcast <16 x i1> %4 to i16
%6 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %d, <16 x float> %x, i32 13, i32 4) %6 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %d, <16 x float> %x, i32 13, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%7 = bitcast <16 x i1> %6 to i16 %7 = bitcast <16 x i1> %6 to i16
%8 = bitcast i16 %1 to <16 x i1> %8 = bitcast i16 %1 to <16 x i1>
%9 = bitcast i16 %3 to <16 x i1> %9 = bitcast i16 %3 to <16 x i1>
%10 = or <16 x i1> %8, %9 %10 = or <16 x i1> %8, %9
%11 = bitcast <16 x i1> %10 to i16 %11 = bitcast <16 x i1> %10 to i16
%12 = bitcast i16 %5 to <16 x i1> %12 = bitcast i16 %5 to <16 x i1>
%13 = bitcast i16 %7 to <16 x i1> %13 = bitcast i16 %7 to <16 x i1>
%14 = or <16 x i1> %12, %13 %14 = or <16 x i1> %12, %13
%15 = bitcast <16 x i1> %14 to i16 %15 = bitcast <16 x i1> %14 to i16
%16 = bitcast i16 %11 to <16 x i1> %16 = bitcast i16 %11 to <16 x i1>
%17 = bitcast i16 %15 to <16 x i1> %17 = bitcast i16 %15 to <16 x i1>
%18 = or <16 x i1> %16, %17 %18 = or <16 x i1> %16, %17
%19 = bitcast <16 x i1> %18 to i16 %19 = bitcast <16 x i1> %18 to i16
ret i16 %19 ret i16 %19
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32) #1 declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32) #1
attributes #0 = { nounwind readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="knl" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512er,+avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind readnone uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="knl" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512er,+avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/X86/avx512-cmp-mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512VL
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512DQ
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512vl,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512DQVL ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512vl,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512DQVL
define <4 x i64> @PR32546(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) { define <4 x i64> @PR32546(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) {
; AVX512F-LABEL: PR32546: ; AVX512VL-LABEL: PR32546:
; AVX512F: ## %bb.0: ## %entry ; AVX512VL: ## %bb.0: ## %entry
; AVX512F-NEXT: ## kill: def $ymm3 killed $ymm3 def $zmm3 ; AVX512VL-NEXT: vcmpltps %ymm1, %ymm0, %k0
; AVX512F-NEXT: ## kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512VL-NEXT: vcmpltps %ymm3, %ymm2, %k1
; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512VL-NEXT: kandw %k0, %k1, %k0
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512VL-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: vcmpltps %zmm3, %zmm2, %k1 ; AVX512VL-NEXT: movzbl %al, %eax
; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k0 {%k1} ; AVX512VL-NEXT: vpbroadcastd %eax, %ymm0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512VL-NEXT: retq
; AVX512F-NEXT: movzbl %al, %eax
; AVX512F-NEXT: vmovd %eax, %xmm0
; AVX512F-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512DQ-LABEL: PR32546:
; AVX512DQ: ## %bb.0: ## %entry
; AVX512DQ-NEXT: ## kill: def $ymm3 killed $ymm3 def $zmm3
; AVX512DQ-NEXT: ## kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512DQ-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512DQ-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512DQ-NEXT: vcmpltps %zmm3, %zmm2, %k1
; AVX512DQ-NEXT: vcmpltps %zmm1, %zmm0, %k0 {%k1}
; AVX512DQ-NEXT: kmovb %k0, %eax
; AVX512DQ-NEXT: vmovd %eax, %xmm0
; AVX512DQ-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX512DQ-NEXT: retq
; ;
; AVX512DQVL-LABEL: PR32546: ; AVX512DQVL-LABEL: PR32546:
; AVX512DQVL: ## %bb.0: ## %entry ; AVX512DQVL: ## %bb.0: ## %entry
; AVX512DQVL-NEXT: vcmpltps %ymm1, %ymm0, %k0
; AVX512DQVL-NEXT: vcmpltps %ymm3, %ymm2, %k1 ; AVX512DQVL-NEXT: vcmpltps %ymm3, %ymm2, %k1
; AVX512DQVL-NEXT: vcmpltps %ymm1, %ymm0, %k0 {%k1} ; AVX512DQVL-NEXT: kandb %k0, %k1, %k0
; AVX512DQVL-NEXT: kmovb %k0, %eax ; AVX512DQVL-NEXT: kmovb %k0, %eax
; AVX512DQVL-NEXT: vpbroadcastd %eax, %ymm0 ; AVX512DQVL-NEXT: vpbroadcastd %eax, %ymm0
; AVX512DQVL-NEXT: retq ; AVX512DQVL-NEXT: retq
entry: entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1) %0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1) %1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
%and17 = and i8 %1, %0 %and17 = and i8 %1, %0
%and = zext i8 %and17 to i32 %and = zext i8 %and17 to i32
%2 = insertelement <8 x i32> undef, i32 %and, i32 0 %2 = insertelement <8 x i32> undef, i32 %and, i32 0
%vecinit7.i = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> zeroinitializer %vecinit7.i = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> zeroinitializer
%3 = bitcast <8 x i32> %vecinit7.i to <4 x i64> %3 = bitcast <8 x i32> %vecinit7.i to <4 x i64>
ret <4 x i64> %3 ret <4 x i64> %3
} }
define void @PR32547(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
; CHECK-LABEL: PR32547:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vcmpltps %ymm1, %ymm0, %k0
; CHECK-NEXT: vcmpltps %ymm3, %ymm2, %k1
; CHECK-NEXT: kunpckbw %k1, %k0, %k1
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
%conv.i = zext i8 %0 to i16
%conv.i18 = zext i8 %1 to i16
%shl = shl nuw i16 %conv.i, 8
%or = or i16 %shl, %conv.i18
%2 = bitcast float* %p to <16 x float>*
%3 = bitcast i16 %or to <16 x i1>
tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3)
ret void
}
define void @PR32547_swap(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
; CHECK-LABEL: PR32547_swap:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vcmpltps %ymm1, %ymm0, %k0
; CHECK-NEXT: vcmpltps %ymm3, %ymm2, %k1
; CHECK-NEXT: kunpckbw %k1, %k0, %k1
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
%conv.i = zext i8 %0 to i16
%conv.i18 = zext i8 %1 to i16
%shl = shl nuw i16 %conv.i, 8
%or = or i16 %conv.i18, %shl
%2 = bitcast float* %p to <16 x float>*
%3 = bitcast i16 %or to <16 x i1>
tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3)
ret void
}
define void @mask_cmp_128(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* %p) {
; AVX512VL-LABEL: mask_cmp_128:
; AVX512VL: ## %bb.0: ## %entry
; AVX512VL-NEXT: vcmpltps %xmm1, %xmm0, %k0
; AVX512VL-NEXT: kmovw %k0, %eax
; AVX512VL-NEXT: vcmpltps %xmm3, %xmm2, %k0
; AVX512VL-NEXT: shlb $4, %al
; AVX512VL-NEXT: kmovw %eax, %k1
; AVX512VL-NEXT: korw %k1, %k0, %k1
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovaps %ymm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
; AVX512DQVL-LABEL: mask_cmp_128:
; AVX512DQVL: ## %bb.0: ## %entry
; AVX512DQVL-NEXT: vcmpltps %xmm1, %xmm0, %k0
; AVX512DQVL-NEXT: vcmpltps %xmm3, %xmm2, %k1
; AVX512DQVL-NEXT: kshiftlb $4, %k0, %k0
; AVX512DQVL-NEXT: korb %k0, %k1, %k1
; AVX512DQVL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512DQVL-NEXT: vmovaps %ymm0, (%rdi) {%k1}
; AVX512DQVL-NEXT: vzeroupper
; AVX512DQVL-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %c, <4 x float> %d, i32 1, i8 -1)
%shl = shl nuw i8 %0, 4
%or = or i8 %1, %shl
%2 = bitcast float* %p to <8 x float>*
%3 = bitcast i8 %or to <8 x i1>
tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> zeroinitializer, <8 x float>* %2, i32 64, <8 x i1> %3)
ret void
}
define <16 x float> @mask_cmp_512(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x float> %d, float* %p) {
; CHECK-LABEL: mask_cmp_512:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vcmpltps {sae}, %zmm1, %zmm0, %k0
; CHECK-NEXT: vcmpltps %zmm3, %zmm2, %k1
; CHECK-NEXT: kxnorw %k1, %k0, %k1
; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} {z}
; CHECK-NEXT: retq
entry:
%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 1, i16 -1, i32 8)
%1 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %c, <16 x float> %d, i32 1, i16 -1, i32 4)
%2 = bitcast float* %p to <16 x float>*
%3 = load <16 x float>, <16 x float>* %2
%4 = xor i16 %0, %1
%5 = bitcast i16 %4 to <16 x i1>
%6 = select <16 x i1> %5, <16 x float> zeroinitializer, <16 x float> %3
ret <16 x float> %6
}
declare i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, i8)
declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8) declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8)
declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, i16, i32)
declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)

llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,864 Lines • ▼ Show 20 Lines
; X64-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; X64-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
; X64-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x89,0xc0] ; X64-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x89,0xc0]
; X64-NEXT: retq ## encoding: [0xc3] ; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i32> @llvm.x86.avx512.mask.expand.d.512(<16 x i32> %data, <16 x i32> zeroinitializer, i16 %mask) %res = call <16 x i32> @llvm.x86.avx512.mask.expand.d.512(<16 x i32> %data, <16 x i32> zeroinitializer, i16 %mask)
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <16 x i32> @llvm.x86.avx512.mask.expand.d.512(<16 x i32> %data, <16 x i32> %src0, i16 %mask) declare <16 x i32> @llvm.x86.avx512.mask.expand.d.512(<16 x i32> %data, <16 x i32> %src0, i16 %mask)
define <16 x float> @test_cmp_512(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x float> %d, float* %p) {
; X86-LABEL: test_cmp_512:
; X86: ## %bb.0: ## %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vcmpltps {sae}, %zmm1, %zmm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x01]
; X86-NEXT: vcmpltps %zmm3, %zmm2, %k1 ## encoding: [0x62,0xf1,0x6c,0x48,0xc2,0xcb,0x01]
; X86-NEXT: kxnorw %k1, %k0, %k1 ## encoding: [0xc5,0xfc,0x46,0xc9]
; X86-NEXT: vmovaps (%eax), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x28,0x00]
; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_cmp_512:
; X64: ## %bb.0: ## %entry
; X64-NEXT: vcmpltps {sae}, %zmm1, %zmm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x01]
; X64-NEXT: vcmpltps %zmm3, %zmm2, %k1 ## encoding: [0x62,0xf1,0x6c,0x48,0xc2,0xcb,0x01]
; X64-NEXT: kxnorw %k1, %k0, %k1 ## encoding: [0xc5,0xfc,0x46,0xc9]
; X64-NEXT: vmovaps (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x28,0x07]
; X64-NEXT: retq ## encoding: [0xc3]
entry:
%0 = tail call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 1, i32 8)
%1 = tail call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %c, <16 x float> %d, i32 1, i32 4)
%2 = bitcast float* %p to <16 x float>*
%3 = load <16 x float>, <16 x float>* %2
%4 = xor <16 x i1> %0, %1
%5 = select <16 x i1> %4, <16 x float> zeroinitializer, <16 x float> %3
ret <16 x float> %5
}
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32)

llvm/test/CodeGen/X86/avx512-intrinsics.ll

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Show First 20 Lines • Show All 1,040 Lines • ▼ Show 20 Lines
define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) { define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
; CHECK-LABEL: test_cmpps: ; CHECK-LABEL: test_cmpps:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i32 8) %res = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%1 = bitcast <16 x i1> %res to i16 %1 = bitcast <16 x i1> %res to i16
ret i16 %1 ret i16 %1
} }
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32) declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32)
define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) { define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) {
; CHECK-LABEL: test_cmppd: ; CHECK-LABEL: test_cmppd:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpneqpd %zmm1, %zmm0, %k0 ; CHECK-NEXT: vcmpneqpd %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i32 4) %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%1 = bitcast <8 x i1> %res to i8 %1 = bitcast <8 x i1> %res to i8
ret i8 %1 ret i8 %1
} }
declare <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double>, <8 x double>, i32, i32) declare <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, <8 x i1>, i32)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
; fp min - max ; fp min - max
define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) { define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
; CHECK-LABEL: test_vmaxpd: ; CHECK-LABEL: test_vmaxpd:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmaxpd %zmm1, %zmm0, %zmm0 ; CHECK-NEXT: vmaxpd %zmm1, %zmm0, %zmm0
▲ Show 20 Lines • Show All 6,440 Lines • ▼ Show 20 Lines
; X86-NEXT: kunpckbw %k0, %k1, %k1 ; X86-NEXT: kunpckbw %k0, %k1, %k1
; X86-NEXT: vmovaps 136(%ebp), %zmm3 {%k1} ; X86-NEXT: vmovaps 136(%ebp), %zmm3 {%k1}
; X86-NEXT: vmovaps %zmm3, %zmm0 ; X86-NEXT: vmovaps %zmm3, %zmm0
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: .cfi_def_cfa %esp, 4 ; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%0 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, i32 4) %0 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%1 = bitcast <8 x i1> %0 to i8 %1 = bitcast <8 x i1> %0 to i8
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %c, <8 x double> %d, i32 17, i32 4) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %c, <8 x double> %d, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
%conv = zext i8 %1 to i16 %conv = zext i8 %1 to i16
%conv2 = zext i8 %3 to i16 %conv2 = zext i8 %3 to i16
%4 = bitcast i16 %conv to <16 x i1> %4 = bitcast i16 %conv to <16 x i1>
%5 = bitcast i16 %conv2 to <16 x i1> %5 = bitcast i16 %conv2 to <16 x i1>
%6 = shufflevector <16 x i1> %4, <16 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %6 = shufflevector <16 x i1> %4, <16 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%7 = shufflevector <16 x i1> %5, <16 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %7 = shufflevector <16 x i1> %5, <16 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%8 = shufflevector <8 x i1> %6, <8 x i1> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %8 = shufflevector <8 x i1> %6, <8 x i1> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
Show All 21 Lines
; X86-NEXT: vcmplt_oqpd %zmm1, %zmm0, %k1 ; X86-NEXT: vcmplt_oqpd %zmm1, %zmm0, %k1
; X86-NEXT: vmovaps 136(%ebp), %zmm2 {%k1} ; X86-NEXT: vmovaps 136(%ebp), %zmm2 {%k1}
; X86-NEXT: vmovaps %zmm2, %zmm0 ; X86-NEXT: vmovaps %zmm2, %zmm0
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: .cfi_def_cfa %esp, 4 ; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%0 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, i32 4) %0 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 17, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%1 = bitcast <8 x i1> %0 to i8 %1 = bitcast <8 x i1> %0 to i8
%conv = zext i8 %1 to i16 %conv = zext i8 %1 to i16
%2 = bitcast i16 %conv to <16 x i1> %2 = bitcast i16 %conv to <16 x i1>
%3 = select <16 x i1> %2, <16 x float> %f, <16 x float> %e %3 = select <16 x i1> %2, <16 x float> %f, <16 x float> %e
ret <16 x float> %3 ret <16 x float> %3
} }
declare <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double>, <8 x double>, <8 x i1>) declare <8 x double> @llvm.x86.avx512.mask.compress.v8f64(<8 x double>, <8 x double>, <8 x i1>)
declare <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float>, <16 x float>, <16 x i1>) declare <16 x float> @llvm.x86.avx512.mask.compress.v16f32(<16 x float>, <16 x float>, <16 x i1>)
declare <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64>, <8 x i64>, <8 x i1>) declare <8 x i64> @llvm.x86.avx512.mask.compress.v8i64(<8 x i64>, <8 x i64>, <8 x i1>)
declare <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32>, <16 x i32>, <16 x i1>) declare <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32>, <16 x i32>, <16 x i1>)
declare <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double>, <8 x double>, <8 x i1>) declare <8 x double> @llvm.x86.avx512.mask.expand.v8f64(<8 x double>, <8 x double>, <8 x i1>)
declare <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float>, <16 x float>, <16 x i1>) declare <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float>, <16 x float>, <16 x i1>)
declare <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64>, <8 x i64>, <8 x i1>) declare <8 x i64> @llvm.x86.avx512.mask.expand.v8i64(<8 x i64>, <8 x i64>, <8 x i1>)
declare <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32>, <16 x i32>, <16 x i1>) declare <16 x i32> @llvm.x86.avx512.mask.expand.v16i32(<16 x i32>, <16 x i32>, <16 x i1>)

llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

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; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
; X64-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0xa9,0x89,0xc0] ; X64-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0xa9,0x89,0xc0]
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx512.mask.expand.d.256(<8 x i32> %data, <8 x i32> zeroinitializer, i8 %mask) %res = call <8 x i32> @llvm.x86.avx512.mask.expand.d.256(<8 x i32> %data, <8 x i32> zeroinitializer, i8 %mask)
ret <8 x i32> %res ret <8 x i32> %res
} }
declare <8 x i32> @llvm.x86.avx512.mask.expand.d.256(<8 x i32> %data, <8 x i32> %src0, i8 %mask) declare <8 x i32> @llvm.x86.avx512.mask.expand.d.256(<8 x i32> %data, <8 x i32> %src0, i8 %mask)
define void @test_cmp_128(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* %p) {
; X86-LABEL: test_cmp_128:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp # encoding: [0x55]
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl %esp, %ebp # encoding: [0x89,0xe5]
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-16, %esp # encoding: [0x83,0xe4,0xf0]
; X86-NEXT: subl $16, %esp # encoding: [0x83,0xec,0x10]
; X86-NEXT: movl 24(%ebp), %eax # encoding: [0x8b,0x45,0x18]
; X86-NEXT: vcmpltps %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x01]
; X86-NEXT: vcmpltps 8(%ebp), %xmm2, %k1 # encoding: [0x62,0xf1,0x6c,0x08,0xc2,0x8d,0x08,0x00,0x00,0x00,0x01]
; X86-NEXT: kshiftlw $4, %k1, %k1 # encoding: [0xc4,0xe3,0xf9,0x32,0xc9,0x04]
; X86-NEXT: korw %k1, %k0, %k1 # encoding: [0xc5,0xfc,0x45,0xc9]
; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
; X86-NEXT: vmovaps %ymm0, (%eax) {%k1} # encoding: [0x62,0xf1,0x7c,0x29,0x29,0x00]
; X86-NEXT: movl %ebp, %esp # encoding: [0x89,0xec]
; X86-NEXT: popl %ebp # encoding: [0x5d]
; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_cmp_128:
; X64: # %bb.0: # %entry
; X64-NEXT: vcmpltps %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x01]
; X64-NEXT: vcmpltps %xmm3, %xmm2, %k1 # encoding: [0x62,0xf1,0x6c,0x08,0xc2,0xcb,0x01]
; X64-NEXT: kshiftlw $4, %k1, %k1 # encoding: [0xc4,0xe3,0xf9,0x32,0xc9,0x04]
; X64-NEXT: korw %k1, %k0, %k1 # encoding: [0xc5,0xfc,0x45,0xc9]
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
; X64-NEXT: vmovaps %ymm0, (%rdi) {%k1} # encoding: [0x62,0xf1,0x7c,0x29,0x29,0x07]
; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X64-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 1)
%1 = tail call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %c, <4 x float> %d, i32 1)
%2 = bitcast float* %p to <8 x float>*
%3 = shufflevector <4 x i1> %0, <4 x i1> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> zeroinitializer, <8 x float>* %2, i32 64, <8 x i1> %3)
ret void
}
define void @test_cmp_256(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
; X86-LABEL: test_cmp_256:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp # encoding: [0x55]
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl %esp, %ebp # encoding: [0x89,0xe5]
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-32, %esp # encoding: [0x83,0xe4,0xe0]
; X86-NEXT: subl $32, %esp # encoding: [0x83,0xec,0x20]
; X86-NEXT: movl 40(%ebp), %eax # encoding: [0x8b,0x45,0x28]
; X86-NEXT: vcmpltps %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x01]
; X86-NEXT: vcmpltps 8(%ebp), %ymm2, %k1 # encoding: [0x62,0xf1,0x6c,0x28,0xc2,0x8d,0x08,0x00,0x00,0x00,0x01]
; X86-NEXT: kunpckbw %k0, %k1, %k1 # encoding: [0xc5,0xf5,0x4b,0xc8]
; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
; X86-NEXT: vmovaps %zmm0, (%eax) {%k1} # encoding: [0x62,0xf1,0x7c,0x49,0x29,0x00]
; X86-NEXT: movl %ebp, %esp # encoding: [0x89,0xec]
; X86-NEXT: popl %ebp # encoding: [0x5d]
; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_cmp_256:
; X64: # %bb.0: # %entry
; X64-NEXT: vcmpltps %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x01]
; X64-NEXT: vcmpltps %ymm3, %ymm2, %k1 # encoding: [0x62,0xf1,0x6c,0x28,0xc2,0xcb,0x01]
; X64-NEXT: kunpckbw %k0, %k1, %k1 # encoding: [0xc5,0xf5,0x4b,0xc8]
; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc0]
; X64-NEXT: vmovaps %zmm0, (%rdi) {%k1} # encoding: [0x62,0xf1,0x7c,0x49,0x29,0x07]
; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X64-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1)
%1 = tail call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1)
%2 = bitcast float* %p to <16 x float>*
%3 = shufflevector <8 x i1> %0, <8 x i1> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3)
ret void
}
declare <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float>, <4 x float>, i32)
declare <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float>, <8 x float>, i32)
declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)

llvm/test/CodeGen/X86/avx512vl-intrinsics.ll

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define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) { define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: test_cmpps_256: ; CHECK-LABEL: test_cmpps_256:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x02] ; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2) %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
%1 = bitcast <8 x i1> %res to i8 %1 = bitcast <8 x i1> %res to i8
ret i8 %1 ret i8 %1
} }
declare <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float>, <8 x float>, i32) declare <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, <8 x i1>)
define i8 @test_cmpps_128(<4 x float> %a, <4 x float> %b) { define i8 @test_cmpps_128(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: test_cmpps_128: ; CHECK-LABEL: test_cmpps_128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmpleps %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x02] ; CHECK-NEXT: vcmpleps %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2) %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
%1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = bitcast <8 x i1> %1 to i8 %2 = bitcast <8 x i1> %1 to i8
ret i8 %2 ret i8 %2
} }
declare <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float>, <4 x float>, i32) declare <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, <4 x i1>)
define i8 @test_cmppd_256(<4 x double> %a, <4 x double> %b) { define i8 @test_cmppd_256(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: test_cmppd_256: ; CHECK-LABEL: test_cmppd_256:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmplepd %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0xfd,0x28,0xc2,0xc1,0x02] ; CHECK-NEXT: vcmplepd %ymm1, %ymm0, %k0 # encoding: [0x62,0xf1,0xfd,0x28,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2) %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
%1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = bitcast <8 x i1> %1 to i8 %2 = bitcast <8 x i1> %1 to i8
ret i8 %2 ret i8 %2
} }
declare <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double>, <4 x double>, i32) declare <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>, i32, <4 x i1>)
define i8 @test_cmppd_128(<2 x double> %a, <2 x double> %b) { define i8 @test_cmppd_128(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: test_cmppd_128: ; CHECK-LABEL: test_cmppd_128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vcmplepd %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0xfd,0x08,0xc2,0xc1,0x02] ; CHECK-NEXT: vcmplepd %xmm1, %xmm0, %k0 # encoding: [0x62,0xf1,0xfd,0x08,0xc2,0xc1,0x02]
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2) %res = call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2, <2 x i1> <i1 true, i1 true>)
%1 = shufflevector <2 x i1> %res, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> %1 = shufflevector <2 x i1> %res, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%2 = bitcast <8 x i1> %1 to i8 %2 = bitcast <8 x i1> %1 to i8
ret i8 %2 ret i8 %2
} }
declare <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double>, <2 x double>, i32) declare <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double>, <2 x double>, i32, <2 x i1>)
define <8 x float> @test_mm512_maskz_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) { define <8 x float> @test_mm512_maskz_max_ps_256(<8 x float> %a0, <8 x float> %a1, i8 %mask) {
; X86-LABEL: test_mm512_maskz_max_ps_256: ; X86-LABEL: test_mm512_maskz_max_ps_256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04] ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8] ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
; X86-NEXT: vmaxps %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf1,0x7c,0xa9,0x5f,0xc1] ; X86-NEXT: vmaxps %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf1,0x7c,0xa9,0x5f,0xc1]
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
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llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

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%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%4 = and <8 x i1> %3, %2 %4 = and <8 x i1> %3, %2
%5 = shufflevector <8 x i1> %4, <8 x i1> zeroinitializer, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %5 = shufflevector <8 x i1> %4, <8 x i1> zeroinitializer, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%6 = bitcast <64 x i1> %5 to i64 %6 = bitcast <64 x i1> %5 to i64
ret i64 %6 ret i64 %6
} }
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32) declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32)
define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr { define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask: ; VLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: # kill: def $al killed $al killed $eax ; VLX-NEXT: # kill: def $al killed $al killed $eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <16 x float> %0 = bitcast <8 x i64> %__a to <16 x float>
%1 = bitcast <8 x i64> %__b to <16 x float> %1 = bitcast <8 x i64> %__b to <16 x float>
%2 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, i32 8) %2 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast <16 x i1> %2 to i16 %3 = bitcast <16 x i1> %2 to i16
%4 = zext i16 %3 to i32 %4 = zext i16 %3 to i32
ret i32 %4 ret i32 %4
} }
define zeroext i32 @test_masked_vcmpoeqps_v16i1_v32i1_sae_mask(i16 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr { define zeroext i32 @test_masked_vcmpoeqps_v16i1_v32i1_sae_mask(i16 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_sae_mask: ; VLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_sae_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: andl %edi, %eax ; VLX-NEXT: andl %edi, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_sae_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v32i1_sae_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andl %edi, %eax ; NoVLX-NEXT: andl %edi, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <16 x float> %0 = bitcast <8 x i64> %__a to <16 x float>
%1 = bitcast <8 x i64> %__b to <16 x float> %1 = bitcast <8 x i64> %__b to <16 x float>
%2 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, i32 8) %2 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast i16 %__u to <16 x i1> %3 = bitcast i16 %__u to <16 x i1>
%4 = and <16 x i1> %2, %3 %4 = and <16 x i1> %2, %3
%5 = bitcast <16 x i1> %4 to i16 %5 = bitcast <16 x i1> %4 to i16
%6 = zext i16 %5 to i32 %6 = zext i16 %5 to i32
ret i32 %6 ret i32 %6
} }
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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <16 x float> %0 = bitcast <8 x i64> %__a to <16 x float>
%1 = bitcast <8 x i64> %__b to <16 x float> %1 = bitcast <8 x i64> %__b to <16 x float>
%2 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, i32 8) %2 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast <16 x i1> %2 to i16 %3 = bitcast <16 x i1> %2 to i16
%4 = zext i16 %3 to i64 %4 = zext i16 %3 to i64
ret i64 %4 ret i64 %4
} }
define zeroext i64 @test_masked_vcmpoeqps_v16i1_v64i1_sae_mask(i16 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr { define zeroext i64 @test_masked_vcmpoeqps_v16i1_v64i1_sae_mask(i16 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_sae_mask: ; VLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_sae_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: andl %edi, %eax ; VLX-NEXT: andl %edi, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_sae_mask: ; NoVLX-LABEL: test_masked_vcmpoeqps_v16i1_v64i1_sae_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andl %edi, %eax ; NoVLX-NEXT: andl %edi, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <16 x float> %0 = bitcast <8 x i64> %__a to <16 x float>
%1 = bitcast <8 x i64> %__b to <16 x float> %1 = bitcast <8 x i64> %__b to <16 x float>
%2 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, i32 8) %2 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %0, <16 x float> %1, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast i16 %__u to <16 x i1> %3 = bitcast i16 %__u to <16 x i1>
%4 = and <16 x i1> %2, %3 %4 = and <16 x i1> %2, %3
%5 = bitcast <16 x i1> %4 to i16 %5 = bitcast <16 x i1> %4 to i16
%6 = zext i16 %5 to i64 %6 = zext i16 %5 to i64
ret i64 %6 ret i64 %6
} }
declare <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double>, <8 x double>, i32, i32) declare <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, <8 x i1>, i32)
define zeroext i4 @test_vcmpoeqpd_v2i1_v4i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr { define zeroext i4 @test_vcmpoeqpd_v2i1_v4i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask: ; VLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0
; VLX-NEXT: kmovb %k0, %eax ; VLX-NEXT: kmovb %k0, %eax
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask:
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; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: # kill: def $ax killed $ax killed $eax ; NoVLX-NEXT: # kill: def $ax killed $ax killed $eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
%4 = zext i8 %3 to i16 %4 = zext i8 %3 to i16
ret i16 %4 ret i16 %4
} }
define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr { define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask: ; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
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; NoVLX-NEXT: andb %dil, %al ; NoVLX-NEXT: andb %dil, %al
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: # kill: def $ax killed $ax killed $eax ; NoVLX-NEXT: # kill: def $ax killed $ax killed $eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%4 = and <8 x i1> %2, %3 %4 = and <8 x i1> %2, %3
%5 = bitcast <8 x i1> %4 to i8 %5 = bitcast <8 x i1> %4 to i8
%6 = zext i8 %5 to i16 %6 = zext i8 %5 to i16
ret i16 %6 ret i16 %6
} }
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; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
%4 = zext i8 %3 to i32 %4 = zext i8 %3 to i32
ret i32 %4 ret i32 %4
} }
define zeroext i32 @test_masked_vcmpoeqpd_v8i1_v32i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr { define zeroext i32 @test_masked_vcmpoeqpd_v8i1_v32i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_sae_mask: ; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v32i1_sae_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
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; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb %dil, %al ; NoVLX-NEXT: andb %dil, %al
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%4 = and <8 x i1> %2, %3 %4 = and <8 x i1> %2, %3
%5 = bitcast <8 x i1> %4 to i8 %5 = bitcast <8 x i1> %4 to i8
%6 = zext i8 %5 to i32 %6 = zext i8 %5 to i32
ret i32 %6 ret i32 %6
} }
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; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
%4 = zext i8 %3 to i64 %4 = zext i8 %3 to i64
ret i64 %4 ret i64 %4
} }
define zeroext i64 @test_masked_vcmpoeqpd_v8i1_v64i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr { define zeroext i64 @test_masked_vcmpoeqpd_v8i1_v64i1_sae_mask(i8 zeroext %__u, <8 x i64> %__a, <8 x i64> %__b) local_unnamed_addr {
; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_sae_mask: ; VLX-LABEL: test_masked_vcmpoeqpd_v8i1_v64i1_sae_mask:
; VLX: # %bb.0: # %entry ; VLX: # %bb.0: # %entry
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; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb %dil, %al ; NoVLX-NEXT: andb %dil, %al
; NoVLX-NEXT: movzbl %al, %eax ; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <8 x i64> %__a to <8 x double> %0 = bitcast <8 x i64> %__a to <8 x double>
%1 = bitcast <8 x i64> %__b to <8 x double> %1 = bitcast <8 x i64> %__b to <8 x double>
%2 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, i32 8) %2 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %0, <8 x double> %1, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%4 = and <8 x i1> %2, %3 %4 = and <8 x i1> %2, %3
%5 = bitcast <8 x i1> %4 to i8 %5 = bitcast <8 x i1> %4 to i8
%6 = zext i8 %5 to i64 %6 = zext i8 %5 to i64
ret i64 %6 ret i64 %6
} }
; Test that we understand that cmpps with rounding zeros the upper bits of the mask register. ; Test that we understand that cmpps with rounding zeros the upper bits of the mask register.
define i32 @test_cmpm_rnd_zero(<16 x float> %a, <16 x float> %b) { define i32 @test_cmpm_rnd_zero(<16 x float> %a, <16 x float> %b) {
; VLX-LABEL: test_cmpm_rnd_zero: ; VLX-LABEL: test_cmpm_rnd_zero:
; VLX: # %bb.0: ; VLX: # %bb.0:
; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; VLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: kmovd %k0, %eax
; VLX-NEXT: vzeroupper ; VLX-NEXT: vzeroupper
; VLX-NEXT: retq ; VLX-NEXT: retq
; ;
; NoVLX-LABEL: test_cmpm_rnd_zero: ; NoVLX-LABEL: test_cmpm_rnd_zero:
; NoVLX: # %bb.0: ; NoVLX: # %bb.0:
; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
%res = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i32 8) %res = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 8)
%1 = bitcast <16 x i1> %res to i16 %1 = bitcast <16 x i1> %res to i16
%cast = bitcast i16 %1 to <16 x i1> %cast = bitcast i16 %1 to <16 x i1>
%shuffle = shufflevector <16 x i1> %cast, <16 x i1> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %shuffle = shufflevector <16 x i1> %cast, <16 x i1> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%cast2 = bitcast <32 x i1> %shuffle to i32 %cast2 = bitcast <32 x i1> %shuffle to i32
ret i32 %cast2 ret i32 %cast2
} }
define i8 @mask_zero_lower(<4 x i32> %a) { define i8 @mask_zero_lower(<4 x i32> %a) {
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llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll

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; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload ; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %a0, <8 x double> %a1, i32 0, i32 4) %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a0, <8 x double> %a1, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%2 = bitcast <8 x i1> %res to i8 %2 = bitcast <8 x i1> %res to i8
ret i8 %2 ret i8 %2
} }
declare <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double>, <8 x double>, i32, i32) declare <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, <8 x i1>, i32)
define <8 x double> @stack_fold_cmppd_mask(<8 x double> %a0, <8 x double> %a1, <8 x double>* %a2, i8 %mask, <8 x double> %b0, <8 x double> %b1) { define <8 x double> @stack_fold_cmppd_mask(<8 x double> %a0, <8 x double> %a1, <8 x double>* %a2, i8 %mask, <8 x double> %b0, <8 x double> %b1) {
; CHECK-LABEL: stack_fold_cmppd_mask: ; CHECK-LABEL: stack_fold_cmppd_mask:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $184, %rsp ; CHECK-NEXT: subq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 192 ; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vaddpd (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vaddpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k1 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: kandb %k0, %k1, %k1
; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vblendmpd (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: vblendmpd (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload
; CHECK-NEXT: addq $184, %rsp ; CHECK-NEXT: addq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load ; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load
%2 = load <8 x double>, <8 x double>* %a2 %2 = load <8 x double>, <8 x double>* %a2
%3 = fadd <8 x double> %a1, %2 %3 = fadd <8 x double> %a1, %2
%4 = bitcast i8 %mask to <8 x i1> %4 = bitcast i8 %mask to <8 x i1>
%5 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %3, <8 x double> %a0, i32 0, i32 4) %5 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %3, <8 x double> %a0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%6 = and <8 x i1> %4, %5 %6 = and <8 x i1> %4, %5
%7 = select <8 x i1> %6, <8 x double> %b0, <8 x double> %b1 %7 = select <8 x i1> %6, <8 x double> %b0, <8 x double> %b1
ret <8 x double> %7 ret <8 x double> %7
} }
define <8 x double> @stack_fold_cmppd_mask_commuted(<8 x double> %a0, <8 x double> %a1, <8 x double>* %a2, i8 %mask, <8 x double> %b0, <8 x double> %b1) { define <8 x double> @stack_fold_cmppd_mask_commuted(<8 x double> %a0, <8 x double> %a1, <8 x double>* %a2, i8 %mask, <8 x double> %b0, <8 x double> %b1) {
; CHECK-LABEL: stack_fold_cmppd_mask_commuted: ; CHECK-LABEL: stack_fold_cmppd_mask_commuted:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $184, %rsp ; CHECK-NEXT: subq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 192 ; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vaddpd (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vaddpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k1 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: kandb %k0, %k1, %k1
; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovupd {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vblendmpd (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: vblendmpd (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload
; CHECK-NEXT: addq $184, %rsp ; CHECK-NEXT: addq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load ; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load
%2 = load <8 x double>, <8 x double>* %a2 %2 = load <8 x double>, <8 x double>* %a2
%3 = fadd <8 x double> %a1, %2 %3 = fadd <8 x double> %a1, %2
%4 = bitcast i8 %mask to <8 x i1> %4 = bitcast i8 %mask to <8 x i1>
%5 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %a0, <8 x double> %3, i32 0, i32 4) %5 = call <8 x i1> @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a0, <8 x double> %3, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%6 = and <8 x i1> %4, %5 %6 = and <8 x i1> %4, %5
%7 = select <8 x i1> %6, <8 x double> %b0, <8 x double> %b1 %7 = select <8 x i1> %6, <8 x double> %b0, <8 x double> %b1
ret <8 x double> %7 ret <8 x double> %7
} }
define i16 @stack_fold_cmpps(<16 x float> %a0, <16 x float> %a1) { define i16 @stack_fold_cmpps(<16 x float> %a0, <16 x float> %a1) {
; CHECK-LABEL: stack_fold_cmpps: ; CHECK-LABEL: stack_fold_cmpps:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload ; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a0, <16 x float> %a1, i32 0, i32 4) %res = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a0, <16 x float> %a1, i32 0, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%2 = bitcast <16 x i1> %res to i16 %2 = bitcast <16 x i1> %res to i16
ret i16 %2 ret i16 %2
} }
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32) declare <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, <16 x i1>, i32)
define <16 x float> @stack_fold_cmpps_mask(<16 x float> %a0, <16 x float> %a1, <16 x float>* %a2, i16 %mask, <16 x float> %b0, <16 x float> %b1) { define <16 x float> @stack_fold_cmpps_mask(<16 x float> %a0, <16 x float> %a1, <16 x float>* %a2, i16 %mask, <16 x float> %b0, <16 x float> %b1) {
; CHECK-LABEL: stack_fold_cmpps_mask: ; CHECK-LABEL: stack_fold_cmpps_mask:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $184, %rsp ; CHECK-NEXT: subq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 192 ; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vaddps (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vaddps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k1 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: kandw %k0, %k1, %k1
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vblendmps (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: vblendmps (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload
; CHECK-NEXT: addq $184, %rsp ; CHECK-NEXT: addq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load ; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load
%2 = load <16 x float>, <16 x float>* %a2 %2 = load <16 x float>, <16 x float>* %a2
%3 = fadd <16 x float> %a1, %2 %3 = fadd <16 x float> %a1, %2
%4 = bitcast i16 %mask to <16 x i1> %4 = bitcast i16 %mask to <16 x i1>
%5 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %3, <16 x float> %a0, i32 0, i32 4) %5 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %3, <16 x float> %a0, i32 0, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%6 = and <16 x i1> %4, %5 %6 = and <16 x i1> %4, %5
%7 = select <16 x i1> %6, <16 x float> %b0, <16 x float> %b1 %7 = select <16 x i1> %6, <16 x float> %b0, <16 x float> %b1
ret <16 x float> %7 ret <16 x float> %7
} }
define <16 x float> @stack_fold_cmpps_mask_commuted(<16 x float> %a0, <16 x float> %a1, <16 x float>* %a2, i16 %mask, <16 x float> %b0, <16 x float> %b1) { define <16 x float> @stack_fold_cmpps_mask_commuted(<16 x float> %a0, <16 x float> %a1, <16 x float>* %a2, i16 %mask, <16 x float> %b0, <16 x float> %b1) {
; CHECK-LABEL: stack_fold_cmpps_mask_commuted: ; CHECK-LABEL: stack_fold_cmpps_mask_commuted:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $184, %rsp ; CHECK-NEXT: subq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 192 ; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm2, (%rsp) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill ; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vaddps (%rdi), %zmm0, %zmm0 ; CHECK-NEXT: vaddps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k0 # 64-byte Folded Reload
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kmovw %esi, %k1
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %k1 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: kandw %k0, %k1, %k1
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload ; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; CHECK-NEXT: vblendmps (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload ; CHECK-NEXT: vblendmps (%rsp), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload
; CHECK-NEXT: addq $184, %rsp ; CHECK-NEXT: addq $184, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load ; load and fadd are here to keep the operations below the side effecting block and to avoid folding the wrong load
%2 = load <16 x float>, <16 x float>* %a2 %2 = load <16 x float>, <16 x float>* %a2
%3 = fadd <16 x float> %a1, %2 %3 = fadd <16 x float> %a1, %2
%4 = bitcast i16 %mask to <16 x i1> %4 = bitcast i16 %mask to <16 x i1>
%5 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %a0, <16 x float> %3, i32 0, i32 4) %5 = call <16 x i1> @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a0, <16 x float> %3, i32 0, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i32 4)
%6 = and <16 x i1> %4, %5 %6 = and <16 x i1> %4, %5
%7 = select <16 x i1> %6, <16 x float> %b0, <16 x float> %b1 %7 = select <16 x i1> %6, <16 x float> %b0, <16 x float> %b1
ret <16 x float> %7 ret <16 x float> %7
} }
define <2 x double> @stack_fold_divsd_int(<2 x double> %a0, <2 x double> %a1) { define <2 x double> @stack_fold_divsd_int(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: stack_fold_divsd_int: ; CHECK-LABEL: stack_fold_divsd_int:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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llvm/test/CodeGen/X86/stack-folding-fp-avx512vl.ll

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; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 # 16-byte Folded Reload ; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 # 16-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %a0, <2 x double> %a1, i32 0) %res = call <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a0, <2 x double> %a1, i32 0, <2 x i1> <i1 true, i1 true>)
%2 = shufflevector <2 x i1> %res, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> %2 = shufflevector <2 x i1> %res, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
ret i8 %3 ret i8 %3
} }
declare <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double>, <2 x double>, i32) declare <2 x i1> @llvm.x86.avx512.mask.cmp.pd.128(<2 x double>, <2 x double>, i32, <2 x i1>)
define i8 @stack_fold_cmppd_ymm(<4 x double> %a0, <4 x double> %a1) { define i8 @stack_fold_cmppd_ymm(<4 x double> %a0, <4 x double> %a1) {
; CHECK-LABEL: stack_fold_cmppd_ymm: ; CHECK-LABEL: stack_fold_cmppd_ymm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 # 32-byte Folded Reload ; CHECK-NEXT: vcmpeqpd {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 # 32-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0) %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
%2 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
ret i8 %3 ret i8 %3
} }
declare <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double>, <4 x double>, i32) declare <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>, i32, <4 x i1>)
define i8 @stack_fold_cmpps(<4 x float> %a0, <4 x float> %a1) { define i8 @stack_fold_cmpps(<4 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: stack_fold_cmpps: ; CHECK-LABEL: stack_fold_cmpps:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 # 16-byte Folded Reload ; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %k0 # 16-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %a0, <4 x float> %a1, i32 0) %res = call <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a0, <4 x float> %a1, i32 0, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
%2 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <4 x i1> %res, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = bitcast <8 x i1> %2 to i8 %3 = bitcast <8 x i1> %2 to i8
ret i8 %3 ret i8 %3
} }
declare <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float>, <4 x float>, i32) declare <4 x i1> @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, <4 x i1>)
define i8 @stack_fold_cmpps_ymm(<8 x float> %a0, <8 x float> %a1) { define i8 @stack_fold_cmpps_ymm(<8 x float> %a0, <8 x float> %a1) {
; CHECK-LABEL: stack_fold_cmpps_ymm: ; CHECK-LABEL: stack_fold_cmpps_ymm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 # 32-byte Folded Reload ; CHECK-NEXT: vcmpeqps {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %k0 # 32-byte Folded Reload
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
%res = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0) %res = call <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
%2 = bitcast <8 x i1> %res to i8 %2 = bitcast <8 x i1> %res to i8
ret i8 %2 ret i8 %2
} }
declare <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float>, <8 x float>, i32) declare <8 x i1> @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, <8 x i1>)
define <2 x double> @stack_fold_divpd(<2 x double> %a0, <2 x double> %a1) { define <2 x double> @stack_fold_divpd(<2 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: stack_fold_divpd: ; CHECK-LABEL: stack_fold_divpd:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
▲ Show 20 Lines • Show All 1,073 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-v1.ll

Show First 20 Lines • Show All 875 Lines • ▼ Show 20 Lines
; VL_BW_DQ-NEXT: kmovq %k0, %rax ; VL_BW_DQ-NEXT: kmovq %k0, %rax
; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: vzeroupper
; VL_BW_DQ-NEXT: retq ; VL_BW_DQ-NEXT: retq
%b = bitcast i64 %a to <64 x i1> %b = bitcast i64 %a to <64 x i1>
%c = shufflevector < 64 x i1> %b, <64 x i1> undef, <64 x i32> zeroinitializer %c = shufflevector < 64 x i1> %b, <64 x i1> undef, <64 x i32> zeroinitializer
%d = bitcast <64 x i1> %c to i64 %d = bitcast <64 x i1> %c to i64
ret i64 %d ret i64 %d
} }
; OR(KSHIFTL(X,8),Y) -> KUNPCKBW
define void @PR32547(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
; AVX512F-LABEL: PR32547:
; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k0
; AVX512F-NEXT: vcmpltps %zmm3, %zmm2, %k1
; AVX512F-NEXT: kunpckbw %k1, %k0, %k1
; AVX512F-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: PR32547:
; AVX512VL: # %bb.0: # %entry
; AVX512VL-NEXT: vcmpltps %ymm1, %ymm0, %k0
; AVX512VL-NEXT: vcmpltps %ymm3, %ymm2, %k1
; AVX512VL-NEXT: kunpckbw %k1, %k0, %k1
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
; VL_BW_DQ-LABEL: PR32547:
; VL_BW_DQ: # %bb.0: # %entry
; VL_BW_DQ-NEXT: vcmpltps %ymm1, %ymm0, %k0
; VL_BW_DQ-NEXT: vcmpltps %ymm3, %ymm2, %k1
; VL_BW_DQ-NEXT: kunpckbw %k1, %k0, %k1
; VL_BW_DQ-NEXT: vxorps %xmm0, %xmm0, %xmm0
; VL_BW_DQ-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; VL_BW_DQ-NEXT: vzeroupper
; VL_BW_DQ-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
%conv.i = zext i8 %0 to i16
%conv.i18 = zext i8 %1 to i16
%shl = shl nuw i16 %conv.i, 8
%or = or i16 %shl, %conv.i18
%2 = bitcast float* %p to <16 x float>*
%3 = bitcast i16 %or to <16 x i1>
tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3) #4
ret void
}
; OR(X, KSHIFTL(Y,8)) -> KUNPCKBW
define void @PR32547_swap(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d, float* %p) {
; AVX512F-LABEL: PR32547_swap:
; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3
; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k0
; AVX512F-NEXT: vcmpltps %zmm3, %zmm2, %k1
; AVX512F-NEXT: kunpckbw %k1, %k0, %k1
; AVX512F-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: PR32547_swap:
; AVX512VL: # %bb.0: # %entry
; AVX512VL-NEXT: vcmpltps %ymm1, %ymm0, %k0
; AVX512VL-NEXT: vcmpltps %ymm3, %ymm2, %k1
; AVX512VL-NEXT: kunpckbw %k1, %k0, %k1
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
; VL_BW_DQ-LABEL: PR32547_swap:
; VL_BW_DQ: # %bb.0: # %entry
; VL_BW_DQ-NEXT: vcmpltps %ymm1, %ymm0, %k0
; VL_BW_DQ-NEXT: vcmpltps %ymm3, %ymm2, %k1
; VL_BW_DQ-NEXT: kunpckbw %k1, %k0, %k1
; VL_BW_DQ-NEXT: vxorps %xmm0, %xmm0, %xmm0
; VL_BW_DQ-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; VL_BW_DQ-NEXT: vzeroupper
; VL_BW_DQ-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %c, <8 x float> %d, i32 1, i8 -1)
%conv.i = zext i8 %0 to i16
%conv.i18 = zext i8 %1 to i16
%shl = shl nuw i16 %conv.i, 8
%or = or i16 %conv.i18, %shl
%2 = bitcast float* %p to <16 x float>*
%3 = bitcast i16 %or to <16 x i1>
tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> zeroinitializer, <16 x float>* %2, i32 64, <16 x i1> %3) #4
ret void
}
define void @mask_cmp_128(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* %p) {
; AVX512F-LABEL: mask_cmp_128:
; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3
; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vcmpltps %zmm1, %zmm0, %k0
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: vcmpltps %zmm3, %zmm2, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k0
; AVX512F-NEXT: shlb $4, %al
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: korw %k1, %k0, %k0
; AVX512F-NEXT: kshiftlw $8, %k0, %k0
; AVX512F-NEXT: kshiftrw $8, %k0, %k1
; AVX512F-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512F-NEXT: vmovaps %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: mask_cmp_128:
; AVX512VL: # %bb.0: # %entry
; AVX512VL-NEXT: vcmpltps %xmm1, %xmm0, %k0
; AVX512VL-NEXT: kmovw %k0, %eax
; AVX512VL-NEXT: vcmpltps %xmm3, %xmm2, %k0
; AVX512VL-NEXT: shlb $4, %al
; AVX512VL-NEXT: kmovw %eax, %k1
; AVX512VL-NEXT: korw %k1, %k0, %k1
; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovaps %ymm0, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
; VL_BW_DQ-LABEL: mask_cmp_128:
; VL_BW_DQ: # %bb.0: # %entry
; VL_BW_DQ-NEXT: vcmpltps %xmm1, %xmm0, %k0
; VL_BW_DQ-NEXT: vcmpltps %xmm3, %xmm2, %k1
; VL_BW_DQ-NEXT: kshiftlb $4, %k0, %k0
; VL_BW_DQ-NEXT: korb %k0, %k1, %k1
; VL_BW_DQ-NEXT: vxorps %xmm0, %xmm0, %xmm0
; VL_BW_DQ-NEXT: vmovaps %ymm0, (%rdi) {%k1}
; VL_BW_DQ-NEXT: vzeroupper
; VL_BW_DQ-NEXT: retq
entry:
%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 1, i8 -1)
%1 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %c, <4 x float> %d, i32 1, i8 -1)
%shl = shl nuw i8 %0, 4
%or = or i8 %1, %shl
%2 = bitcast float* %p to <8 x float>*
%3 = bitcast i8 %or to <8 x i1>
tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> zeroinitializer, <8 x float>* %2, i32 64, <8 x i1> %3)
ret void
}
declare i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, i8)
declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8)
declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)

llvm/test/Transforms/InstCombine/X86/X86FsubCmpCombine.ll

  • This file was deleted.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
; The test checks the folding of cmp(sub(a,b),0) into cmp(a,b).
define i8 @sub_compare_foldingPD128_safe(<2 x double> %a, <2 x double> %b){
; CHECK-LABEL: @sub_compare_foldingPD128_safe(
; CHECK-NEXT: [[SUB_SAFE:%.*]] = fsub <2 x double> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[T0:%.*]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> [[SUB_SAFE]], <2 x double> zeroinitializer, i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i1> [[T0]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.safe = fsub <2 x double> %a, %b
%t0 = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %sub.safe, <2 x double> zeroinitializer, i32 5)
%t1 = shufflevector <2 x i1> %t0, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_foldingPD128(<2 x double> %a, <2 x double> %b){
; CHECK-LABEL: @sub_compare_foldingPD128(
; CHECK-NEXT: [[T0:%.*]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i1> [[T0]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i = fsub ninf <2 x double> %a, %b
%t0 = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %sub.i, <2 x double> zeroinitializer, i32 5)
%t1 = shufflevector <2 x i1> %t0, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_foldingPD128_undef_elt(<2 x double> %a, <2 x double> %b){
; CHECK-LABEL: @sub_compare_foldingPD128_undef_elt(
; CHECK-NEXT: [[T0:%.*]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i1> [[T0]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i = fsub ninf <2 x double> %a, %b
%t0 = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> %sub.i, <2 x double> <double 0.0, double undef>, i32 5)
%t1 = shufflevector <2 x i1> %t0, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_foldingPD256(<4 x double> %a, <4 x double> %b){
; CHECK-LABEL: @sub_compare_foldingPD256(
; CHECK-NEXT: [[T0:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> [[A:%.*]], <4 x double> [[B:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <4 x i1> [[T0]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i1 = fsub ninf <4 x double> %a, %b
%t0 = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %sub.i1, <4 x double> zeroinitializer, i32 5)
%t1 = shufflevector <4 x i1> %t0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_foldingPD512(<8 x double> %a, <8 x double> %b){
; CHECK-LABEL: @sub_compare_foldingPD512(
; CHECK-NEXT: [[T0:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 11, i32 4)
; CHECK-NEXT: [[T1:%.*]] = bitcast <8 x i1> [[T0]] to i8
; CHECK-NEXT: ret i8 [[T1]]
;
%sub.i2 = fsub ninf <8 x double> %a, %b
%t0 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> %sub.i2, <8 x double> zeroinitializer, i32 11, i32 4)
%t1 = bitcast <8 x i1> %t0 to i8
ret i8 %t1
}
define i8 @sub_compare_foldingPS128(<4 x float> %a, <4 x float> %b){
; CHECK-LABEL: @sub_compare_foldingPS128(
; CHECK-NEXT: [[T0:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], i32 12)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <4 x i1> [[T0]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i3 = fsub ninf <4 x float> %a, %b
%t0 = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> %sub.i3, <4 x float> zeroinitializer, i32 12)
%t1 = shufflevector <4 x i1> %t0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_foldingPS256(<8 x float> %a, <8 x float> %b){
; CHECK-LABEL: @sub_compare_foldingPS256(
; CHECK-NEXT: [[T0:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> [[A:%.*]], <8 x float> [[B:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = bitcast <8 x i1> [[T0]] to i8
; CHECK-NEXT: ret i8 [[T1]]
;
%sub.i4 = fsub ninf <8 x float> %a, %b
%t0 = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> %sub.i4, <8 x float> zeroinitializer, i32 5)
%t1 = bitcast <8 x i1> %t0 to i8
ret i8 %t1
}
define i16 @sub_compare_foldingPS512(<16 x float> %a, <16 x float> %b){
; CHECK-LABEL: @sub_compare_foldingPS512(
; CHECK-NEXT: [[T0:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 11, i32 4)
; CHECK-NEXT: [[T1:%.*]] = bitcast <16 x i1> [[T0]] to i16
; CHECK-NEXT: ret i16 [[T1]]
;
%sub.i5 = fsub ninf <16 x float> %a, %b
%t0 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> %sub.i5, <16 x float> zeroinitializer, i32 11, i32 4)
%t1 = bitcast <16 x i1> %t0 to i16
ret i16 %t1
}
define i8 @sub_compare_folding_swapPD128(<2 x double> %a, <2 x double> %b){
; CHECK-LABEL: @sub_compare_folding_swapPD128(
; CHECK-NEXT: [[T0:%.*]] = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> [[B:%.*]], <2 x double> [[A:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i1> [[T0]], <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i = fsub ninf <2 x double> %a, %b
%t0 = call <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double> zeroinitializer, <2 x double> %sub.i, i32 5)
%t1 = shufflevector <2 x i1> %t0, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_folding_swapPD256(<4 x double> %a, <4 x double> %b){
; CHECK-LABEL: @sub_compare_folding_swapPD256(
; CHECK-NEXT: [[T0:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> [[B:%.*]], <4 x double> [[A:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <4 x i1> [[T0]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i = fsub ninf <4 x double> %a, %b
%t0 = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> %sub.i, i32 5)
%t1 = shufflevector <4 x i1> %t0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_folding_swapPD256_undef(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: @sub_compare_folding_swapPD256_undef(
; CHECK-NEXT: [[TMP:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> undef, <4 x double> zeroinitializer, i32 5)
; CHECK-NEXT: [[T0:%.*]] = shufflevector <4 x i1> [[TMP]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T1:%.*]] = bitcast <8 x i1> [[T0]] to i8
; CHECK-NEXT: ret i8 [[T1]]
;
%sub.i1 = fsub ninf <4 x double> undef, undef
%tmp = call <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double> %sub.i1, <4 x double> zeroinitializer, i32 5)
%t0 = shufflevector <4 x i1> %tmp, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t1 = bitcast <8 x i1> %t0 to i8
ret i8 %t1
}
define i8 @sub_compare_folding_swapPD512(<8 x double> %a, <8 x double> %b){
; CHECK-LABEL: @sub_compare_folding_swapPD512(
; CHECK-NEXT: [[T0:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> [[B:%.*]], <8 x double> [[A:%.*]], i32 11, i32 4)
; CHECK-NEXT: [[T1:%.*]] = bitcast <8 x i1> [[T0]] to i8
; CHECK-NEXT: ret i8 [[T1]]
;
%sub.i = fsub ninf <8 x double> %a, %b
%t0 = call <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double> zeroinitializer, <8 x double> %sub.i, i32 11, i32 4)
%t1 = bitcast <8 x i1> %t0 to i8
ret i8 %t1
}
define i8 @sub_compare_folding_swapPS128(<4 x float> %a, <4 x float> %b){
; CHECK-LABEL: @sub_compare_folding_swapPS128(
; CHECK-NEXT: [[T0:%.*]] = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> [[B:%.*]], <4 x float> [[A:%.*]], i32 12)
; CHECK-NEXT: [[T1:%.*]] = shufflevector <4 x i1> [[T0]], <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T2:%.*]] = bitcast <8 x i1> [[T1]] to i8
; CHECK-NEXT: ret i8 [[T2]]
;
%sub.i = fsub ninf <4 x float> %a, %b
%t0 = call <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float> zeroinitializer, <4 x float> %sub.i, i32 12)
%t1 = shufflevector <4 x i1> %t0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = bitcast <8 x i1> %t1 to i8
ret i8 %t2
}
define i8 @sub_compare_folding_swapPS256(<8 x float> %a, <8 x float> %b){
; CHECK-LABEL: @sub_compare_folding_swapPS256(
; CHECK-NEXT: [[T0:%.*]] = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> [[B:%.*]], <8 x float> [[A:%.*]], i32 5)
; CHECK-NEXT: [[T1:%.*]] = bitcast <8 x i1> [[T0]] to i8
; CHECK-NEXT: ret i8 [[T1]]
;
%sub.i = fsub ninf <8 x float> %a, %b
%t0 = call <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> %sub.i, i32 5)
%t1 = bitcast <8 x i1> %t0 to i8
ret i8 %t1
}
define i16 @sub_compare_folding_swapPS512(<16 x float> %a, <16 x float> %b){
; CHECK-LABEL: @sub_compare_folding_swapPS512(
; CHECK-NEXT: [[T0:%.*]] = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> [[B:%.*]], <16 x float> [[A:%.*]], i32 11, i32 4)
; CHECK-NEXT: [[T1:%.*]] = bitcast <16 x i1> [[T0]] to i16
; CHECK-NEXT: ret i16 [[T1]]
;
%sub.i = fsub ninf <16 x float> %a, %b
%t0 = call <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float> zeroinitializer, <16 x float> %sub.i, i32 11, i32 4)
%t1 = bitcast <16 x i1> %t0 to i16
ret i16 %t1
}
declare <2 x i1> @llvm.x86.avx512.cmp.pd.128(<2 x double>, <2 x double>, i32)
declare <4 x i1> @llvm.x86.avx512.cmp.pd.256(<4 x double>, <4 x double>, i32)
declare <8 x i1> @llvm.x86.avx512.cmp.pd.512(<8 x double>, <8 x double>, i32, i32)
declare <4 x i1> @llvm.x86.avx512.cmp.ps.128(<4 x float>, <4 x float>, i32)
declare <8 x i1> @llvm.x86.avx512.cmp.ps.256(<8 x float>, <8 x float>, i32)
declare <16 x i1> @llvm.x86.avx512.cmp.ps.512(<16 x float>, <16 x float>, i32, i32)
llvm/test/CodeGen/X86/vector-shuffle-v1.ll