Remove TwoAddressInstructinoPass::sink3AddrInstruction.

[jyknight]

Summary

This function has a bug which will incorrectly reschedule instructions
after an INLINEASM_BR (which can branch). (The bug may also allow
scheduling past a throwing-CALL, I'm not certain.)

I could fix that bug, but, as the removed FIXME noted, attempting to
move instructions _before_ converting to 3-addr, so as to avoid
needing to make the conversion in the first place is a better
idea. And, in fact, the code to do such reodering was added to this
pass in 2011, via the addition of the function rescheduleMIBelowKill,
only a few months after the FIXME was added. That reschedule code
does not contain the same bug.

The removal of this funciton is not a no-op: in some cases
sink3AddrInstruction would move an instruction after converting it to
3-addr form, when rescheduleMIBelowKill would not move before
converison. However, this does not appear to be important: the
machine instruction scheduler can reorder the after-conversion
instructions, in any case.

[nickdesaulniers]

LGTM; tests pass and kernel panic is fixed. Just minor nits on things we might be able to simplify further in the test.

llvm/test/CodeGen/X86/callbr-asm-sink.ll

9

Looks like we only access the third element of this struct in the GEP, IIUC the GEP correctly?

25

I think you can drop the constant i32 1 from the callbr and its er, flags.

35

ret void?

llvm/test/CodeGen/X86/reverse_branches.ll

69

This move into %rdi after the call to _memchr is curious to me. Doesn't the x86_64 ABI that darwin uses use %rdi as the first parameter to a function call? Before hand, it looks like we're setting up the registers for the call as part of the calling convention. After, it looks like we're maybe misplacing the mov into %rdi?

If we jump to LBB0_5, we kill %rdi immediately.

Ah, LBB0_1 will have loaded %r15 into %rdi for LBB0_3.

Ok, I think this is correct, but would appreciate others to pay careful attention to this case.

[nickdesaulniers]

I could fix that bug, but, as the removed FIXME noted, attempting to
move instructions _before_ converting to 3-addr, so as to avoid
needing to make the conversion in the first place is a better
idea.

Also, that sentence has more than the legally allowed number of commas. Please consider breaking it up into multiple sentences. Maybe:

I could fix that bug but as the removed FIXME noted, attempting to
move instructions _before_ converting to 3-addr so as to avoid
needing to make the conversion in the first place, is a better
idea.

[craig.topper]

llvm/test/CodeGen/X86/twoaddr-lea.ll

71–73

What's happening here? Previously the two instructions used the same register, but now they don't?

[jyknight]

llvm/test/CodeGen/X86/twoaddr-lea.ll

71–73

Correct.

 _ham:                                   ## @ham
        .cfi_startproc
 ## %bb.0:                               ## %bb
        xorl    %r8d, %r8d
        movq    _global@GOTPCREL(%rip), %rdx
        movq    _global2@GOTPCREL(%rip), %rsi
        xorl    %eax, %eax
        cmpl    $10, %eax
        jle     LBB3_2
 LBB3_6:                                 ## %bb2
                                         ## =>This Loop Header: Depth=1
                                         ##     Child Loop BB3_7 Depth 2
        movl    (%rdx), %edi
        leal    (%rdi,%rax), %ecx
        movslq  %ecx, %rcx
 LBB3_7:                                 ## %bb6
                                         ##   Parent Loop BB3_6 Depth=1
                                         ## =>  This Inner Loop Header: Depth=2
        movq    %rax, (%rsi)
        movq    %rcx, (%rsi)
        movl    %edi, (%rdx)
        testb   %r8b, %r8b
        jne     LBB3_7
 ## %bb.8:                               ## %bb9
                                         ##   in Loop: Header=BB3_6 Depth=1
        addq    $4, %rax
        cmpl    $10, %eax
        jg      LBB3_6
 LBB3_2:                                 ## %bb3.preheader
        xorl    %ecx, %ecx
 LBB3_3:                                 ## %bb3
                                         ## =>This Loop Header: Depth=1
                                         ##     Child Loop BB3_4 Depth 2
-       movl    %eax, %edx
-       subl    %ecx, %edx
-       movq    %rcx, %rsi
+       movq    %rcx, %rdx
        addq    $4, %rcx
+       movl    %eax, %esi
+       subl    %edx, %esi
 LBB3_4:                                 ## %bb4
                                         ##   Parent Loop BB3_3 Depth=1
                                         ## =>  This Inner Loop Header: Depth=2
-       testl   %edx, %edx
+       testl   %esi, %esi
        jne     LBB3_9
 ## %bb.5:                               ## %bb5
                                         ##   in Loop: Header=BB3_4 Depth=2
-       incq    %rsi
-       cmpq    %rcx, %rsi
+       incq    %rdx
+       cmpq    %rcx, %rdx
        jge     LBB3_3
        jmp     LBB3_4
 LBB3_9:                                 ## %bb8
        ud2

[jyknight]

Improve commit message wording
Simplify added test a bit

llvm/test/CodeGen/X86/callbr-asm-sink.ll

9

Yeah. Needs to be a non-zero offset but other than that doesn't matter; I can get rid of the middle elements.

[nickdesaulniers]

llvm/test/CodeGen/X86/callbr-asm-sink.ll

24

what is $2 in this case if there's only 2 parameters explicitly passed into the asm? Maybe you can drop that here and in the CHECK-NEXT above?

[jyknight]

llvm/test/CodeGen/X86/callbr-asm-sink.ll

24

Oops, that was an oversight, I'll fix before pushing. I'm rather surprised this isn't an error -- who knew you could index into the clobber arguments (other than "memory"), in LLVM asm!

[nickdesaulniers]

please don't forget to remove the $2

[void]

LGTM

[hans]

This might be a good candidate for release/11.x. What do you think?

[hans]

In D83708#2157707, @hans wrote:

This might be a good candidate for release/11.x. What do you think?

James pushed it to 11.x as 8a438096ffa48dadeb73b78844c53a7428aaec20

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "twoaddressinstruction"
 
 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
 STATISTIC(NumCommuted        , "Number of instructions commuted to coalesce");
 STATISTIC(NumAggrCommuted    , "Number of instructions aggressively commuted");
 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
-STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
 STATISTIC(NumReSchedUps,       "Number of instructions re-scheduled up");
 STATISTIC(NumReSchedDowns,     "Number of instructions re-scheduled down");
 
 // Temporary flag to disable rescheduling.
 static cl::opt<bool>
 EnableRescheduling("twoaddr-reschedule",
                    cl::desc("Coalesce copies by rescheduling (default=true)"),
                    cl::init(true), cl::Hidden);
class TwoAddressInstructionPass : public MachineFunctionPass {
   MachineBasicBlock *MBB;
 
   // Keep track the distance of a MI from the start of the current basic block.
   DenseMap<MachineInstr*, unsigned> DistanceMap;
 
   // Set of already processed instructions in the current block.
   SmallPtrSet<MachineInstr*, 8> Processed;
 
-  // Set of instructions converted to three-address by target and then sunk
-  // down current basic block.
-  SmallPtrSet<MachineInstr*, 8> SunkInstrs;
-
   // A map from virtual registers to physical registers which are likely targets
   // to be coalesced to due to copies from physical registers to virtual
   // registers. e.g. v1024 = move r0.
   DenseMap<unsigned, unsigned> SrcRegMap;
 
   // A map from virtual registers to physical registers which are likely targets
   // to be coalesced to due to copies to physical registers from virtual
   // registers. e.g. r1 = move v1024.
   DenseMap<unsigned, unsigned> DstRegMap;
 
-  bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
-                            MachineBasicBlock::iterator OldPos);
-
   bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
 
   bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
 
   bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
                              MachineInstr *MI, unsigned Dist);
 
   bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,

 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
                 "Two-Address instruction pass", false, false)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
                 "Two-Address instruction pass", false, false)
 
 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
 
-/// A two-address instruction has been converted to a three-address instruction
-/// to avoid clobbering a register. Try to sink it past the instruction that
-/// would kill the above mentioned register to reduce register pressure.
-bool TwoAddressInstructionPass::
-sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
-                     MachineBasicBlock::iterator OldPos) {
-  // FIXME: Shouldn't we be trying to do this before we three-addressify the
-  // instruction?  After this transformation is done, we no longer need
-  // the instruction to be in three-address form.
-
-  // Check if it's safe to move this instruction.
-  bool SeenStore = true; // Be conservative.
-  if (!MI->isSafeToMove(AA, SeenStore))
-    return false;
-
-  unsigned DefReg = 0;
-  SmallSet<unsigned, 4> UseRegs;
-
-  for (const MachineOperand &MO : MI->operands()) {
-    if (!MO.isReg())
-      continue;
-    Register MOReg = MO.getReg();
-    if (!MOReg)
-      continue;
-    if (MO.isUse() && MOReg != SavedReg)
-      UseRegs.insert(MO.getReg());
-    if (!MO.isDef())
-      continue;
-    if (MO.isImplicit())
-      // Don't try to move it if it implicitly defines a register.
-      return false;
-    if (DefReg)
-      // For now, don't move any instructions that define multiple registers.
-      return false;
-    DefReg = MO.getReg();
-  }
-
-  // Find the instruction that kills SavedReg.
-  MachineInstr *KillMI = nullptr;
-  if (LIS) {
-    LiveInterval &LI = LIS->getInterval(SavedReg);
-    assert(LI.end() != LI.begin() &&
-           "Reg should not have empty live interval.");
-
-    SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
-    LiveInterval::const_iterator I = LI.find(MBBEndIdx);
-    if (I != LI.end() && I->start < MBBEndIdx)
-      return false;
-
-    --I;
-    KillMI = LIS->getInstructionFromIndex(I->end);
-  }
-  if (!KillMI) {
-    for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
-      if (!UseMO.isKill())
-        continue;
-      KillMI = UseMO.getParent();
-      break;
-    }
-  }
-
-  // If we find the instruction that kills SavedReg, and it is in an
-  // appropriate location, we can try to sink the current instruction
-  // past it.
-  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
-      MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
-    return false;
-
-  // If any of the definitions are used by another instruction between the
-  // position and the kill use, then it's not safe to sink it.
-  //
-  // FIXME: This can be sped up if there is an easy way to query whether an
-  // instruction is before or after another instruction. Then we can use
-  // MachineRegisterInfo def / use instead.
-  MachineOperand *KillMO = nullptr;
-  MachineBasicBlock::iterator KillPos = KillMI;
-  ++KillPos;
-
-  unsigned NumVisited = 0;
-  for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
-    // Debug instructions cannot be counted against the limit.
-    if (OtherMI.isDebugInstr())
-      continue;
-    if (NumVisited > 30)  // FIXME: Arbitrary limit to reduce compile time cost.
-      return false;
-    ++NumVisited;
-    for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = OtherMI.getOperand(i);
-      if (!MO.isReg())
-        continue;
-      Register MOReg = MO.getReg();
-      if (!MOReg)
-        continue;
-      if (DefReg == MOReg)
-        return false;
-
-      if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
-        if (&OtherMI == KillMI && MOReg == SavedReg)
-          // Save the operand that kills the register. We want to unset the kill
-          // marker if we can sink MI past it.
-          KillMO = &MO;
-        else if (UseRegs.count(MOReg))
-          // One of the uses is killed before the destination.
-          return false;
-      }
-    }
-  }
-  assert(KillMO && "Didn't find kill");
-
-  if (!LIS) {
-    // Update kill and LV information.
-    KillMO->setIsKill(false);
-    KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
-    KillMO->setIsKill(true);
-
-    if (LV)
-      LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
-  }
-
-  // Move instruction to its destination.
-  MBB->remove(MI);
-  MBB->insert(KillPos, MI);
-
-  if (LIS)
-    LIS->handleMove(*MI);
-
-  ++Num3AddrSunk;
-  return true;
-}
-
 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
 static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
                                   const MachineRegisterInfo *MRI) {
   MachineInstr *Ret = nullptr;
   for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
     if (DefMI.getParent() != BB || DefMI.isDebugValue())
       continue;
     if (!Ret)
TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
   MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
   assert(MBB->getIterator() == MFI &&
          "convertToThreeAddress changed iterator reference");
   if (!NewMI)
     return false;
 
   LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
   LLVM_DEBUG(dbgs() << "2addr:         TO 3-ADDR: " << *NewMI);
-  bool Sunk = false;
 
   if (LIS)
     LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
 
-  if (NewMI->findRegisterUseOperand(RegB, false, TRI))
-    // FIXME: Temporary workaround. If the new instruction doesn't
-    // uses RegB, convertToThreeAddress must have created more
-    // then one instruction.
-    Sunk = sink3AddrInstruction(NewMI, RegB, mi);
-
   MBB->erase(mi); // Nuke the old inst.
 
-  if (!Sunk) {
-    DistanceMap.insert(std::make_pair(NewMI, Dist));
-    mi = NewMI;
-    nmi = std::next(mi);
-  }
-  else
-    SunkInstrs.insert(NewMI);
 
   // Update source and destination register maps.
   SrcRegMap.erase(RegA);
   DstRegMap.erase(RegB);
   return true;
 }
 
 /// Scan forward recursively for only uses, update maps if the use is a copy or
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
        MBBI != MBBE; ++MBBI) {
     MBB = &*MBBI;
     unsigned Dist = 0;
     DistanceMap.clear();
     SrcRegMap.clear();
     DstRegMap.clear();
     Processed.clear();
-    SunkInstrs.clear();
     for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
          mi != me; ) {
       MachineBasicBlock::iterator nmi = std::next(mi);
-      // Don't revisit an instruction previously converted by target. It may
-      // contain undef register operands (%noreg), which are not handled.
-      if (mi->isDebugInstr() || SunkInstrs.count(&*mi)) {
+      // Skip debug instructions.
+      if (mi->isDebugInstr()) {
         mi = nmi;
         continue;
       }
 
       // Expand REG_SEQUENCE instructions. This will position mi at the first
       // expanded instruction.
       if (mi->isRegSequence())
         eliminateRegSequence(mi);

llvm/test/CodeGen/X86/callbr-asm-sink.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+;; Verify that the machine instructions generated from the first
+;; getelementptr don't get sunk below the callbr. (Reduced from a bug
+;; report.)
+
+%struct1 = type { i8*, i32 }
+
+define void @klist_dec_and_del(%struct1*) {
+; CHECK-LABEL: klist_dec_and_del:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    leaq 8(%rdi), %rax
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    # 8(%rdi) .Ltmp0 %dirflag
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .Ltmp0: # Block address taken
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    movq $0, -8(%rax)
+; CHECK-NEXT:    retq
+  %2 = getelementptr inbounds %struct1, %struct1* %0, i64 0, i32 1
+  callbr void asm sideeffect "# $0 $1 $2", "*m,X,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %2, i8* blockaddress(@klist_dec_and_del, %3))
+          to label %6 [label %3]
+
+3:
+  %4 = getelementptr i32, i32* %2, i64 -2
+  %5 = bitcast i32* %4 to i8**
+  store i8* null, i8** %5, align 8
+  br label %6
+
+6:
+  ret void
+}

llvm/test/CodeGen/X86/masked-iv-unsafe.ll

 
 return:
         ret void
 }
 
 define void @another_count_down_signed(double* %d, i64 %n) nounwind {
 ; CHECK-LABEL: another_count_down_signed:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    shlq $24, %rax
-; CHECK-NEXT:    leaq -10(%rsi), %rcx
+; CHECK-NEXT:    leaq -10(%rsi), %rax
+; CHECK-NEXT:    movq %rsi, %rcx
+; CHECK-NEXT:    shlq $24, %rcx
 ; CHECK-NEXT:    shlq $8, %rsi
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB7_1: # %loop
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movq %rsi, %rdx
 ; CHECK-NEXT:    sarq $8, %rdx
 ; CHECK-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
 ; CHECK-NEXT:    mulsd %xmm0, %xmm3
 ; CHECK-NEXT:    movsd %xmm3, (%rdi,%rdx,8)
-; CHECK-NEXT:    movq %rax, %rdx
+; CHECK-NEXT:    movq %rcx, %rdx
 ; CHECK-NEXT:    sarq $24, %rdx
 ; CHECK-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
 ; CHECK-NEXT:    mulsd %xmm1, %xmm3
 ; CHECK-NEXT:    movsd %xmm3, (%rdi,%rdx,8)
 ; CHECK-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
 ; CHECK-NEXT:    mulsd %xmm2, %xmm3
-; CHECK-NEXT:    movsd %xmm3, 80(%rdi,%rcx,8)
-; CHECK-NEXT:    addq $-16777216, %rax # imm = 0xFF000000
+; CHECK-NEXT:    movsd %xmm3, 80(%rdi,%rax,8)
+; CHECK-NEXT:    addq $-16777216, %rcx # imm = 0xFF000000
 ; CHECK-NEXT:    addq $-256, %rsi
-; CHECK-NEXT:    decq %rcx
+; CHECK-NEXT:    decq %rax
 ; CHECK-NEXT:    jne .LBB7_1
 ; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    retq
 entry:
         br label %loop
 
 loop:
         %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]

llvm/test/CodeGen/X86/reverse_branches.ll

 ; CHECK-NEXT:    incl %r12d
 ; CHECK-NEXT:  LBB0_1: ## %for.cond
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_3 Depth 2
 ; CHECK-NEXT:    cmpl $999, %r12d ## imm = 0x3E7
 ; CHECK-NEXT:    jg LBB0_7
 ; CHECK-NEXT:  ## %bb.2: ## %for.cond1.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_1 Depth=1
-; CHECK-NEXT:    movl $-1, %r13d
-; CHECK-NEXT:    movq %r15, %rbx
-; CHECK-NEXT:    movq %r14, %rbp
+; CHECK-NEXT:    movl $-1, %ebp
+; CHECK-NEXT:    movq %r15, %rdi
+; CHECK-NEXT:    movq %r14, %rbx
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_3: ## %for.cond1
 ; CHECK-NEXT:    ## Parent Loop BB0_1 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    incl %r13d
-; CHECK-NEXT:    cmpl $999, %r13d ## imm = 0x3E7
+; CHECK-NEXT:    incl %ebp
+; CHECK-NEXT:    cmpl $999, %ebp ## imm = 0x3E7
 ; CHECK-NEXT:    jg LBB0_6
 ; CHECK-NEXT:  ## %bb.4: ## %for.body3
 ; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=2
-; CHECK-NEXT:    addq $1002, %rbp ## imm = 0x3EA
-; CHECK-NEXT:    movq %rbx, %rdi
-; CHECK-NEXT:    addq $1001, %rbx ## imm = 0x3E9
+; CHECK-NEXT:    addq $1002, %rbx ## imm = 0x3EA
+; CHECK-NEXT:    leaq 1001(%rdi), %r13
 ; CHECK-NEXT:    movl $1000, %edx ## imm = 0x3E8
 ; CHECK-NEXT:    movl $120, %esi
 ; CHECK-NEXT:    callq _memchr
-; CHECK-NEXT:    cmpq %rax, %rbp
+; CHECK-NEXT:    cmpq %rax, %rbx
+; CHECK-NEXT:    movq %r13, %rdi
 ; CHECK-NEXT:    je LBB0_3
 ; CHECK-NEXT:    jmp LBB0_5
 ; CHECK-NEXT:  LBB0_7: ## %for.end11
 ; CHECK-NEXT:    leaq {{.*}}(%rip), %rdi
 ; CHECK-NEXT:    callq _puts
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    movq %rsp, %rcx
 ; CHECK-NEXT:    jmp LBB0_8

llvm/test/CodeGen/X86/rotate-extract.ll

; X64-NEXT:    retq
   %lhs = lshr i32 %i, 31
   %out = or i32 %lhs, %ii
   ret i32 %out
 }
 
 define i32 @no_extract_add_1(i32 %i) nounwind {
 ; X86-LABEL: no_extract_add_1:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    leal (%ecx,%ecx), %eax
-; X86-NEXT:    shrl $27, %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    leal (%eax,%eax), %ecx
+; X86-NEXT:    shrl $27, %eax
 ; X86-NEXT:    orl %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: no_extract_add_1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-NEXT:    leal (%rdi,%rdi), %eax
 ; X64-NEXT:    shrl $27, %edi
 ; X64-NEXT:    orl %edi, %eax
 ; X64-NEXT:    retq
   %ii = add i32 %i, %i
   %rhs = lshr i32 %i, 27
   %out = or i32 %ii, %rhs
   ret i32 %out
 }

llvm/test/CodeGen/X86/twoaddr-lea.ll

 
 bb2:
   %tmp6 = load i32, i32* @global, align 4
   %tmp8 = add nsw i32 %tmp6, %tmp2
   %tmp9 = sext i32 %tmp8 to i64
   br label %bb6
 
 bb3:
-; CHECK: subl %e[[REG0:[a-z0-9]+]],
-; CHECK: addq $4, %r[[REG0]]
+; CHECK: LBB3_3:
+; CHECK: addq $4, %r
+; CHECK: subl %e
   %tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
   %tmp15 = add nuw i64 %tmp14, 4
   %tmp16 = trunc i64 %tmp14 to i32
   %tmp17 = sub i32 %tmp2, %tmp16
   br label %bb4
 
 bb4:
   %tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]

llvm/test/CodeGen/X86/twoaddr-pass-sink.ll

-; REQUIRES: asserts
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -stats 2>&1 | grep "Number of 3-address instructions sunk"
-
-define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind  {
-entry:
-  %tmp25 = bitcast <2 x i64> %a1 to <8 x i16>    ; <<8 x i16>> [#uses=1]
-  br label %bb
-bb:   ; preds = %bb, %entry
-  %skiplist_addr.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]    ; <i32> [#uses=3]
-  %vYp_addr.0.rec = shl i32 %skiplist_addr.0.rec, 3    ; <i32> [#uses=3]
-  %vDct_addr.0 = getelementptr <2 x i64>, <2 x i64>* %vDct, i32 %vYp_addr.0.rec    ; <<2 x i64>*> [#uses=1]
-  %vYp_addr.0 = getelementptr <2 x i64>, <2 x i64>* %vYp, i32 %vYp_addr.0.rec    ; <<2 x i64>*> [#uses=1]
-  %skiplist_addr.0 = getelementptr i8, i8* %skiplist, i32 %skiplist_addr.0.rec    ; <i8*> [#uses=1]
-  %vDct_addr.0.sum43 = or i32 %vYp_addr.0.rec, 1    ; <i32> [#uses=1]
-  %tmp7 = getelementptr <2 x i64>, <2 x i64>* %vDct, i32 %vDct_addr.0.sum43    ; <<2 x i64>*> [#uses=1]
-  %tmp8 = load <2 x i64>, <2 x i64>* %tmp7, align 16    ; <<2 x i64>> [#uses=1]
-  %tmp11 = load <2 x i64>, <2 x i64>* %vDct_addr.0, align 16    ; <<2 x i64>> [#uses=1]
-  %tmp13 = bitcast <2 x i64> %tmp8 to <8 x i16>    ; <<8 x i16>> [#uses=1]
-  %tmp15 = bitcast <2 x i64> %tmp11 to <8 x i16>    ; <<8 x i16>> [#uses=1]
-  %tmp16 = shufflevector <8 x i16> %tmp15, <8 x i16> %tmp13, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 >    ; <<8 x i16>> [#uses=1]
-  %tmp26 = mul <8 x i16> %tmp25, %tmp16    ; <<8 x i16>> [#uses=1]
-  %tmp27 = bitcast <8 x i16> %tmp26 to <2 x i64>    ; <<2 x i64>> [#uses=1]
-  store <2 x i64> %tmp27, <2 x i64>* %vYp_addr.0, align 16
-  %tmp37 = load i8, i8* %skiplist_addr.0, align 1    ; <i8> [#uses=1]
-  %tmp38 = icmp eq i8 %tmp37, 0    ; <i1> [#uses=1]
-  %indvar.next = add i32 %skiplist_addr.0.rec, 1    ; <i32> [#uses=1]
-  br i1 %tmp38, label %return, label %bb
-return:   ; preds = %bb
-  ret void
-}