[PowerPC] Support constrained fp operation for scalar fptosi/fptoui

[qiucf]

Summary

This patch adds support for constrained conversion operation (fptoui/fptosi) from f32/f64 to i32/i64.

Vector support will be done in following patches. For targets older than ISA 2.06, we need to make strict_fsetcc/strict_fsetccs work well first.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8144

The parameter SDLoc is not needed. And can we change the function like: getFpNode() or something else ? You don't need to have the strict in the function name as it is already one of the function parameter.

8148

!Strict is not needed.

8172

This is not good code practice. Please use: Strict ? 1 : 0 or seeking some API in the SDValue.

8196

The logic between LowerFP_TO_INTForReuse and LowerFP_TO_INTDirectMove is nearly the same between line 8168 ~ 8196. And that is expected as the difference between the two is how to move the data from FPR to GPR. So, can we add another function to do the convert ? Something like:

LowerFP_TO_INTDirectMove:
  V = convertToFp()
  MFVSR V

LowerFP_TO_INTForReuse:
 V = convertToFp()
 Store V
 Load V

8278

This could be something that we can improve later. We should mark it as legal instead of checking it here if I understand the intention correctly.

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

8

Add run for SPE target.

10

A a test for fp128

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8150

Please give the default initializer to avoid uninitialized local variable if llvm_unreachable is off.

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

171

Does this attribute need ?

[qiucf]

Address Steven's comments.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8148

If Strict is false, we can allow Chain to be null.

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

171

All function calls done in a function that uses constrained floating point intrinsics must have the strictfp attribute.

Although output won't change if we remove this attr. It's better to keep it according to langref.

[qiucf]

Remove redundant chain logic.

[steven.zhang]

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

15 ↗

(On Diff #270027)

So, what is it if it is ppcfp128 ?

[steven.zhang]

Some code style comments.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8269–8270

Don't use Tmp but with some meaningful name.

8270

Op.getValueType() ?

[steven.zhang]

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

3 ↗

(On Diff #270027)

Please specify option -enable-ppc-quad-precision to enable the quad precision support in powerpc.

[qiucf]

Rebase after D81818 and add f128 support

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8145

The Strict parameter is not needed as you can check the value of the Chain to know it.

8174

IsStrict, IsSigned

llvm/lib/Target/PowerPC/PPCInstrVSX.td

3278

Please move them into some group has the semantics of truncating. It is not bitconvert.

[qiucf]

Address some style-related comments

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

Don’t do this for spe target and remove the test for spe. Sorry about the back and forth.

8158

You don't need this assertion now.

8203

So, do we have problem if it is strict opcode in this code path?

8261

move the assertion into concertFPToInt

8428

ConvertIntToFP and ConvertFPToInt should have the same parameters.

8533

Please remove such kind of change as it is not part of your change.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

I would defer to @jhibbits @chmeee (not sure which of Justin's ID's is active) regarding SPE bits.

8150

This function appears to just take a node and produce a strict version of that node. It seems like there isn't anything target dependent about such an operation so it is very suspicious to me why this is in the PPC back end.
If for some reason it has to be here, please explain why in a comment. If the only target specific part of this is the STRICT_MFVSR node, then at least the rest can be handled by target independent code, can't it?

8153

This seems dangerous to me. You are deciding whether to return a strict node based on whether a valid Chain is provided. I am personally against making decisions based on orthogonal concerns.
If the caller wants a strict node, that should be explicit rather than this strange implicit contract of "If you want a strict node, provide a valid chain."

llvm/lib/Target/PowerPC/PPCISelLowering.h

435

Why? The instruction simply moves bits around. It does not cause any exceptions, it is not subject to rounding, etc. If this is necessary, it needs to be clear from the comment why.

[jhibbits]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

What are the semantic differences between STRICT_FP_TO_UINT and FP_TO_UINT? EFDCTUIZ/EFSCTUIZ and their signed counterparts, which we currently use for the FP_TO_{U,S}INT, saturate if they can't be represented as a 32-bit integer, and round toward zero always (the non-Z variants round via the current rounding mode).

[uweigand]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

FP_TO_UINT assumes the current rounding mode is default, and exception conditions can be ignored. With STRICT_FP_TO_UINT those assumptions no longer apply, so it would appear that those instructions you mention should not be used there.

[uweigand]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

Ah -- my last comment was incorrect, sorry for any confusion.

STRICT_FP_TO_UINT/SINT are in fact an exception to most "STRICT" operations in that they do not use the current rounding mode, but always round towards zero. (Following the C standard as well as the LLVM IR specification.)

So for these operations the only difference between strict and non-strict variants is whether exception conditions can be ignored or not.

[jhibbits]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

Ah, okay. So, if I understand correctly, EF{S,D}CT{S,U}I should be used for fp_to_{s,u}int, and the current 'Z' variants should be used for the strict_fp_to_*int.

[uweigand]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

Hmm, if I'm reading the SPE_PEM correctly, I think the "Z" variants are in fact correct for both strict and non-strict variants: they round towards zero (which both variants do), and they handle exceptions (which the strict variant requires, while the non-strict variant doesn't care).

The non-"Z" variants seem wrong either way since they use the current rounding mode, which is incorrect for both strict and non-strict variants.

[jhibbits]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

Thanks for that explanation @uweigand now I understand. So the change here looks fine to me.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

The reason why I asked to remove the spe here is to split this patch into two, one for PowerPC and another one for spe which need some inputs from spe experts. Does it make sense ?

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8150

Thanks for the comments. The method (including some overloads) doesn't help much. So I removed it and wrote a simple helper method to get strict version of ppc-specific opcode.

There's method mutateStrictFPToFP doing similar things but maybe not suitable here. I'll send an NFC to make opcode conversion a hook so that each target can benefit from it.

8203

Do you mean these PPC-specific opcodes are not strict? But the result is either load/store or direct moved. What we do here is to keep operands of value consistent. So changing these opcodes to strict may be unnecessary.

8428

FPToInt is round-then-move, while IntToFP is move-then-round. So when IntToFP we need extra information from original Op besides the moved Src.

llvm/lib/Target/PowerPC/PPCISelLowering.h

435

Because (1) this prevents it being combined somewhere unexpectedly; (2) all strict nodes have extra operand for their chains, so replacing original strict_* node with non-strict one will cause operands mismatch. I added necessary comments. Thanks.

[qiucf]

• Removed SPE logic from this revision.
• Add some comments for strict nodes.
• Removed getFPNode method.
• Addressed other minor comments.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

582

I split D82747 out from this. It's much clearer and independent from this.

[qiucf]

Reflect changes after strict conversion for SPE and enable-ppc-quad-precision's removal.

[qiucf]

Ping..

[steven.zhang]

LGTM now. Please hold on for several days to see if @nemanjai or @uweigand have comments.

[uweigand]

This doesn't look correct. As far as I can see, none of the conversion functions were actually changed to handle strict operations. For one, you'll need strict variants of all the PowerPC-specific conversion operations, use them in all the conversion subroutines, and consistently track their chain nodes.

The patch only adds a strict variant of the direct move, which seems to me the only operation where actually a strict version is not required ...

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8230

This doesn't look right. The Chain produced by this strict node just vanishes, this cannot be correct.

8247

And you need strict versions of all these conversion operations, I'd assume.

8258

Nothing in the function actually handles strict nodes, that cannot be right.

8307

Why do we need a strict version of a plain move?

8312

Again, nothing in this function actually handles strict nodes ...

[qiucf]

In D81537#2193216, @uweigand wrote:

This doesn't look correct. As far as I can see, none of the conversion functions were actually changed to handle strict operations. For one, you'll need strict variants of all the PowerPC-specific conversion operations, use them in all the conversion subroutines, and consistently track their chain nodes.

The patch only adds a strict variant of the direct move, which seems to me the only operation where actually a strict version is not required ...

Thanks for pointing them out! I have something unclear about chains:

(1) If a constrained operation is expanded into several FP nodes a-b-c, they should all have chain set to former operation (b's chain is a, c's chain is b) even if they have def relationship?

(2) In MachineInstr emitting after ISel, chains are identified just by operand type (countOperand), so some chains are not ignored and assert hit. Is this expected?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8307

Yes, a strict move doesn't look reasonable. But the original strict_fptosi node will be replaced by the result. So if directly return the move, operands will not match (no chain in mfvsr). Is there a better way here?

[uweigand]

In D81537#2207249, @qiucf wrote:

In D81537#2193216, @uweigand wrote:

This doesn't look correct. As far as I can see, none of the conversion functions were actually changed to handle strict operations. For one, you'll need strict variants of all the PowerPC-specific conversion operations, use them in all the conversion subroutines, and consistently track their chain nodes.

The patch only adds a strict variant of the direct move, which seems to me the only operation where actually a strict version is not required ...

Thanks for pointing them out! I have something unclear about chains:

(1) If a constrained operation is expanded into several FP nodes a-b-c, they should all have chain set to former operation (b's chain is a, c's chain is b) even if they have def relationship?

That may depend on the specific semantics on which of those nodes may or may not trap. In some cases, the original sequence may in fact not be valid at all for strict mode. But if it is, then they'll need to be chained up properly. If they have data dependencies, then it usually makes sense for the chain to follow that dependency. In other cases, the may be an option for more flexibility by allowing certain operations to be re-scheduled. In those cases you'd give the same input chain to all operations and collect all output chains via a TokenFactor.

(2) In MachineInstr emitting after ISel, chains are identified just by operand type (countOperand), so some chains are not ignored and assert hit. Is this expected?

I'm not sure I understand what specific case you're refering to. But in any case, a chain should *never* be simply ignored, that would always be a bug.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8307

So this gets expanded to a PPCISD::FCTI... variant (inside convertFPToInt) followed by the MFVSR. Now, with proper chain handling, the input chain of the strict_fptosi is consumed by a strict variant of FCTI..., and the output chain of that STRICT_FCTI... is then the correct output chain for the whole operation. The data output (only) of the STRICT_FCTI... acts then as the input of the MFVSR, and the output of the MFVSR is the correct value output of the whole operation.

So if short, you need to replace

(out-val, out-chain) = strict_fptosi (in-val, in-chain)

by

(tmp-val, out-chain) = STRICT_FCTI... (in-val, in-chain)
out-val = MFVSR (tmp-val)

This probably will require some ReplaceAllUses... instead of just returning a result, as is already done elsewhere with chain output instructions.

[qiucf]

Thanks for the detailed explanation!

• Remove strict mfvsr
• Update tests
• Add strict fc*
• Add chains to some expanded operation

[uweigand]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8068

This looks still wrong to me. I think you should replace the *chain* with the one from Conv, and return the value (i.e. Mov). Something like:

SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 1), Conv.getValue(1));
return Mov;

(Actually, returning the value is then the same in strict and non-strict cases, so this can be merged.)

Or, another possible approach would be to not use ReplaceAllUses at all but reconstruct the multi-output value via DAG.getMergeValues. Something like;

SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
return DAG.getMergeValues({Mov, Conv.getValue(1)}, dl);

llvm/lib/Target/PowerPC/PPCInstrVSX.td

3772

This also doesn't look quite correct. The XSCVQP... instructions are not (yet?) marked as mayRaiseFPException, instead they're marked as hasSideEffects. This means that the exception flag is probably not going to be automatically transferred over to the MI level.

I think if the instructions are changed to set mayRaiseFPException, that should work correctly. But it would be best to have a test case that validates that the "nofpexcept" marker is transferred depending on the value of the "fpexect." metadata in the strict intrinsic (in LLVM IR).

[qiucf]

• Return a merge_value for round and move.
• Set fp exception bit for f128 round instructions.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

3772

Thanks for the reminder. The FP exception bits in PPC instruction definition files need to be carefully re-examined with more tests..

[uweigand]

This LGTM now. Thanks!

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// lower (IDX=1) half of v4f32 to v2f64.
     FP_EXTEND_HALF,
 
     /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
     /// either through an add like PADDI or through a PC Relative load like
     /// PLD.
     MAT_PCREL_ADDR,
 
+    /// Constrained direct move from VSR instruction.
+    STRICT_MFVSR = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+
     /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
     /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
     /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
     /// i32.
     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 
     /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
     /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

   // PowerPC does not have BRCOND which requires SetCC
   if (!Subtarget.useCRBits())
     setOperationAction(ISD::BRCOND, MVT::Other, Expand);
 
   setOperationAction(ISD::BR_JT,  MVT::Other, Expand);
 
   if (Subtarget.hasSPE()) {
     // SPE has built-in conversions
+    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
     setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
   } else {
     // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
 
     // PowerPC does not have [U|S]INT_TO_FP
     setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
   }
 
   if (Subtarget.hasDirectMove() && isPPC64) {
     setOperationAction(ISD::BITCAST, MVT::f32, Legal);

   setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
   setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
   setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
   setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
 
   if (Subtarget.has64BitSupport()) {
     // They also have instructions for converting between i64 and fp.
+    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
+    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
     setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
     setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
     // This is just the low 32 bits of a (signed) fp->i64 conversion.
     // We cannot do this with Promote because i64 is not a legal type.
+    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 
     if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
       setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
   } else {
     // PowerPC does not have FP_TO_UINT on 32-bit implementations.
-    if (Subtarget.hasSPE())
+    if (Subtarget.hasSPE()) {
+      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
-    else
+    } else {
+      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
+    }
   }
 
   // With the instructions enabled under FPCVT, we can do everything.
   if (Subtarget.hasFPCVT()) {
     if (Subtarget.has64BitSupport()) {
+      setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
+      setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
       setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
       setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
       setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
       setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
     }
 
+    setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
+    setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
   }
 
   if (Subtarget.use64BitRegs()) {
     // 64-bit PowerPC implementations can support i64 types directly

   case PPCISD::FADDRTZ:         return "PPCISD::FADDRTZ";
   case PPCISD::TC_RETURN:       return "PPCISD::TC_RETURN";
   case PPCISD::CR6SET:          return "PPCISD::CR6SET";
   case PPCISD::CR6UNSET:        return "PPCISD::CR6UNSET";
   case PPCISD::PPC32_GOT:       return "PPCISD::PPC32_GOT";
   case PPCISD::PPC32_PICGOT:    return "PPCISD::PPC32_PICGOT";
   case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
   case PPCISD::LD_GOT_TPREL_L:  return "PPCISD::LD_GOT_TPREL_L";
   case PPCISD::ADD_TLS:         return "PPCISD::ADD_TLS";
   case PPCISD::ADDIS_TLSGD_HA:  return "PPCISD::ADDIS_TLSGD_HA";
   case PPCISD::ADDI_TLSGD_L:    return "PPCISD::ADDI_TLSGD_L";
   case PPCISD::GET_TLS_ADDR:    return "PPCISD::GET_TLS_ADDR";
   case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
   case PPCISD::ADDIS_TLSLD_HA:  return "PPCISD::ADDIS_TLSLD_HA";
   case PPCISD::ADDI_TLSLD_L:    return "PPCISD::ADDI_TLSLD_L";
   case PPCISD::GET_TLSLD_ADDR:  return "PPCISD::GET_TLSLD_ADDR";
   case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";

   case PPCISD::BUILD_SPE64:     return "PPCISD::BUILD_SPE64";
   case PPCISD::EXTRACT_SPE:     return "PPCISD::EXTRACT_SPE";
   case PPCISD::EXTSWSLI:        return "PPCISD::EXTSWSLI";
   case PPCISD::LD_VSX_LH:       return "PPCISD::LD_VSX_LH";
   case PPCISD::FP_EXTEND_HALF:  return "PPCISD::FP_EXTEND_HALF";
   case PPCISD::MAT_PCREL_ADDR:  return "PPCISD::MAT_PCREL_ADDR";
   case PPCISD::LD_SPLAT:        return "PPCISD::LD_SPLAT";
   case PPCISD::FNMSUB:          return "PPCISD::FNMSUB";
+  case PPCISD::STRICT_MFVSR:    return "PPCISD::STRICT_MFVSR";
   }
   return nullptr;
 }
 
 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
                                           EVT VT) const {
   if (!VT.isVector())
     return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;

       (!DAG.getTarget().Options.NoNaNsFPMath && !Flags.hasNoNaNs()))
     return Op;
 
   // If the RHS of the comparison is a 0.0, we don't need to do the
   // subtraction at all.
   SDValue Sel1;
   if (isFloatingPointZero(RHS))
     switch (CC) {
     default: break;       // SETUO etc aren't handled by fsel.
     case ISD::SETNE:
       std::swap(TV, FV);
       LLVM_FALLTHROUGH;
     case ISD::SETEQ:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
         LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
       Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
       if (Sel1.getValueType() == MVT::f32)   // Comparison is always 64-bits

   switch (CC) {
   default: break;       // SETUO etc aren't handled by fsel.
   case ISD::SETNE:
     std::swap(TV, FV);
     LLVM_FALLTHROUGH;
   case ISD::SETEQ:
     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
     Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
     if (Sel1.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
     return DAG.getNode(PPCISD::FSEL, dl, ResVT,
                        DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
   case ISD::SETULT:
   case ISD::SETLT:
     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
     return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
   case ISD::SETOGE:
   case ISD::SETGE:
     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
     return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
   case ISD::SETUGT:
   case ISD::SETGT:
     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
     return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
   case ISD::SETOLE:
   case ISD::SETLE:
     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
     return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
   }
   return Op;
 }
 
+static SDValue getMayStrictNode(unsigned Opc, const SDLoc &dl, EVT VT, SDValue Op,
+                                SDValue Chain, SelectionDAG &DAG, bool Strict) {
+  if (!Strict)
+    return DAG.getNode(Opc, dl, VT, Op);
+  assert((!Strict || Chain) && "Missing chain for creating strict nodes");
+
+  unsigned NewOpc;
+  switch (Opc) {
+  default:
+    llvm_unreachable("mutateStrictFPToFP called with unexpected opcode!");
+  case PPCISD::MFVSR: NewOpc = PPCISD::STRICT_MFVSR; break;
+#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
+  case ISD::DAGN: NewOpc = ISD::STRICT_##DAGN; break;
+#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)
+#include "llvm/IR/ConstrainedOps.def"
+#undef DAG_INSTRUCTION
+#undef CMP_INSTRUCTION
+  }
+  return DAG.getNode(NewOpc, dl, {VT, MVT::Other}, {Chain, Op});
+}
+
 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
                                                SelectionDAG &DAG,
                                                const SDLoc &dl) const {
-  assert(Op.getOperand(0).getValueType().isFloatingPoint());
-  SDValue Src = Op.getOperand(0);
+  bool Strict = Op->isStrictFPOpcode();
+  bool Signed = Op.getOpcode() == ISD::FP_TO_SINT ||
+                Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
+  // For strict nodes, source is the second operand.
+  SDValue Src = Op.getOperand((int)Strict);
+  SDValue FPChain;
+  if (Strict)
+    FPChain = Op.getOperand(0);
+  assert(Src.getValueType().isFloatingPoint());
+
   if (Src.getValueType() == MVT::f32)
-    Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
+    Src = getMayStrictNode(ISD::FP_EXTEND, dl, MVT::f64, Src, FPChain, DAG, Strict);
 
   SDValue Tmp;
   switch (Op.getSimpleValueType().SimpleTy) {
   default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
   case MVT::i32:
     Tmp = DAG.getNode(
-        Op.getOpcode() == ISD::FP_TO_SINT
-            ? PPCISD::FCTIWZ
-            : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
+        Signed ? PPCISD::FCTIWZ
+               : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
         dl, MVT::f64, Src);
     break;
   case MVT::i64:
-    assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
+    assert((Signed || Subtarget.hasFPCVT()) &&
            "i64 FP_TO_UINT is supported only with FPCVT");
-    Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
-                                                        PPCISD::FCTIDUZ,
-                      dl, MVT::f64, Src);
+    Tmp = DAG.getNode(Signed ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ, dl, MVT::f64,
+                      Src);
     break;
   }
 
   // Convert the FP value to an int value through memory.
   bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
-    (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
+                  (Signed || Subtarget.hasFPCVT());
   SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
   int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
   MachinePointerInfo MPI =
       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
 
   // Emit a store to the stack slot.
   SDValue Chain;
   Align Alignment(DAG.getEVTAlign(Tmp.getValueType()));
   if (i32Stack) {
     MachineFunction &MF = DAG.getMachineFunction();
     Alignment = Align(4);
     MachineMemOperand *MMO =
         MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Alignment);
     SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
     Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
               DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
   } else
     Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, MPI, Alignment);
 
   // Result is a load from the stack slot.  If loading 4 bytes, make sure to
   // add in a bias on big endian.
   if (Op.getValueType() == MVT::i32 && !i32Stack) {
     FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
                         DAG.getConstant(4, dl, FIPtr.getValueType()));
     MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4);
   }
 
   RLI.Chain = Chain;
   RLI.Ptr = FIPtr;
   RLI.MPI = MPI;
   RLI.Alignment = Alignment;
 }
 
 /// Custom lowers floating point to integer conversions to use
 /// the direct move instructions available in ISA 2.07 to avoid the
 /// need for load/store combinations.
 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
                                                     SelectionDAG &DAG,
                                                     const SDLoc &dl) const {
-  assert(Op.getOperand(0).getValueType().isFloatingPoint());
-  SDValue Src = Op.getOperand(0);
+  bool Strict = Op->isStrictFPOpcode();
+  bool Signed = Op.getOpcode() == ISD::FP_TO_SINT ||
+                Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
+  SDValue Src = Op.getOperand((int)Strict);
+  assert(Src.getValueType().isFloatingPoint());
+  SDValue Chain;
+  if (Strict)
+    Chain = Op.getOperand(0);
 
   if (Src.getValueType() == MVT::f32)
-    Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
+    Src = getMayStrictNode(ISD::FP_EXTEND, dl, MVT::f64, Src, Chain, DAG, Strict);
 
   SDValue Tmp;
-  switch (Op.getSimpleValueType().SimpleTy) {
+  MVT::SimpleValueType SimpleTy = Op.getSimpleValueType().SimpleTy;
+  switch (SimpleTy) {
   default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
   case MVT::i32:
     Tmp = DAG.getNode(
-        Op.getOpcode() == ISD::FP_TO_SINT
-            ? PPCISD::FCTIWZ
-            : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
+        Signed ? PPCISD::FCTIWZ
+               : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
         dl, MVT::f64, Src);
-    Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
     break;
   case MVT::i64:
-    assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
+    assert((Signed || Subtarget.hasFPCVT()) &&
            "i64 FP_TO_UINT is supported only with FPCVT");
-    Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
-                                                        PPCISD::FCTIDUZ,
-                      dl, MVT::f64, Src);
-    Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
+    Tmp = DAG.getNode(Signed ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ, dl, MVT::f64,
+                      Src);
     break;
   }
-  return Tmp;
+
+  return getMayStrictNode(PPCISD::MFVSR, dl, SimpleTy, Tmp, Chain, DAG, Strict);
 }
 
 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
                                           const SDLoc &dl) const {
-
+  bool Strict = Op->isStrictFPOpcode();
+  SDValue Src = Op.getOperand((int)Strict);
   // FP to INT conversions are legal for f128.
-  if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128))
+  if (EnableQuadPrecision && (Src.getValueType() == MVT::f128))
     return Op;
 
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).
-  if (Op.getOperand(0).getValueType() == MVT::ppcf128) {
+  if (Src.getValueType() == MVT::ppcf128) {
     if (Op.getValueType() == MVT::i32) {
       if (Op.getOpcode() == ISD::FP_TO_SINT) {
         SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
                                  MVT::f64, Op.getOperand(0),
                                  DAG.getIntPtrConstant(0, dl));
         SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
                                  MVT::f64, Op.getOperand(0),
                                  DAG.getIntPtrConstant(1, dl));
 
         // Add the two halves of the long double in round-to-zero mode.
         SDValue Res = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
 
         // Now use a smaller FP_TO_SINT.
         return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
       }
       if (Op.getOpcode() == ISD::FP_TO_UINT) {
         const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
         APFloat APF = APFloat(APFloat::PPCDoubleDouble(), APInt(128, TwoE31));
         SDValue Tmp = DAG.getConstantFP(APF, dl, MVT::ppcf128);
         //  X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
         // FIXME: generated code sucks.
         // TODO: Are there fast-math-flags to propagate to this FSUB?
         SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128,
                                    Op.getOperand(0), Tmp);
         True = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, True);
         True = DAG.getNode(ISD::ADD, dl, MVT::i32, True,
                            DAG.getConstant(0x80000000, dl, MVT::i32));
         SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
                                     Op.getOperand(0));
         return DAG.getSelectCC(dl, Op.getOperand(0), Tmp, True, False,
                                ISD::SETGE);
       }
     }
 
     return SDValue();
   }
 

 
     // Only look at the users of the loaded value.
     if (UI.getUse().get().getResNo() != 0)
       continue;
 
     if (UI->getOpcode() != ISD::SINT_TO_FP &&
         UI->getOpcode() != ISD::UINT_TO_FP)
       return true;
   }
 
   return false;
 }
 
 /// Custom lowers integer to floating point conversions to use
 /// the direct move instructions available in ISA 2.07 to avoid the
 /// need for load/store combinations.
 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,

                                IntermediateVT.getVectorNumElements());
 
     Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange,
                          DAG.getValueType(ExtVT));
   } else
     Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);
 
   return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
 }
 
 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
                                           SelectionDAG &DAG) const {
   SDLoc dl(Op);
 
   EVT InVT = Op.getOperand(0).getValueType();
   EVT OutVT = Op.getValueType();
   if (OutVT.isVector() && OutVT.isFloatingPoint() &&

   case ISD::EH_DWARF_CFA:       return LowerEH_DWARF_CFA(Op, DAG);
   case ISD::EH_SJLJ_SETJMP:     return lowerEH_SJLJ_SETJMP(Op, DAG);
   case ISD::EH_SJLJ_LONGJMP:    return lowerEH_SJLJ_LONGJMP(Op, DAG);
 
   case ISD::LOAD:               return LowerLOAD(Op, DAG);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
   case ISD::TRUNCATE:           return LowerTRUNCATE(Op, DAG);
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
+  case ISD::STRICT_FP_TO_UINT:
+  case ISD::STRICT_FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT:         return LowerFP_TO_INT(Op, DAG, SDLoc(Op));
   case ISD::UINT_TO_FP:
   case ISD::SINT_TO_FP:         return LowerINT_TO_FP(Op, DAG);
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
 
   // Lower 64-bit shifts.
   case ISD::SHL_PARTS:          return LowerSHL_PARTS(Op, DAG);

 
     Results.push_back(
         DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, RTB, RTB.getValue(1)));
     Results.push_back(RTB.getValue(2));
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
     if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
         Intrinsic::loop_decrement)
       break;
 
     assert(N->getValueType(0) == MVT::i1 &&
            "Unexpected result type for CTR decrement intrinsic");
     EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
                                  N->getValueType(0));
     SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
     SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),

     if (VT == MVT::i64) {
       SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG);
 
       Results.push_back(NewNode);
       Results.push_back(NewNode.getValue(1));
     }
     return;
   }
+  case ISD::STRICT_FP_TO_SINT:
+  case ISD::STRICT_FP_TO_UINT:
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
     // LowerFP_TO_INT() can only handle f32 and f64.
-    if (N->getOperand(0).getValueType() == MVT::ppcf128)
+    if (N->getOperand((int)N->isStrictFPOpcode()).getValueType() == MVT::ppcf128)
       return;
     Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
     return;
   case ISD::TRUNCATE: {
     EVT TrgVT = N->getValueType(0);
     EVT OpVT = N->getOperand(0).getValueType();
     if (TrgVT.isVector() &&
         isOperationCustom(N->getOpcode(), TrgVT) &&

llvm/lib/Target/PowerPC/PPCInstrSPE.td

def EFDCTSI        : EFXForm_2a<757, (outs gprc:$RT), (ins sperc:$RB),
                                 []>;
 
 def EFDCTSIDZ      : EFXForm_2a<747, (outs gprc:$RT), (ins sperc:$RB),
                                 "efdctsidz $RT, $RB", IIC_FPDGeneral,
                                 []>;
 
 def EFDCTSIZ       : EFXForm_2a<762, (outs gprc:$RT), (ins sperc:$RB),
                                 "efdctsiz $RT, $RB", IIC_FPDGeneral,
-                                [(set i32:$RT, (fp_to_sint f64:$RB))]>;
+                                [(set i32:$RT, (any_fp_to_sint f64:$RB))]>;
 
 def EFDCTUF        : EFXForm_2a<758, (outs sperc:$RT), (ins spe4rc:$RB),
                                 "efdctuf $RT, $RB", IIC_FPDGeneral, []>;
 
 def EFDCTUI        : EFXForm_2a<756, (outs gprc:$RT), (ins sperc:$RB),
                                 "efdctui $RT, $RB", IIC_FPDGeneral,
                                 []>;
 
 def EFDCTUIDZ      : EFXForm_2a<746, (outs gprc:$RT), (ins sperc:$RB),
                                 "efdctuidz $RT, $RB", IIC_FPDGeneral,
                                 []>;
 
 def EFDCTUIZ       : EFXForm_2a<760, (outs gprc:$RT), (ins sperc:$RB),
                                 "efdctuiz $RT, $RB", IIC_FPDGeneral,
-                                [(set i32:$RT, (fp_to_uint f64:$RB))]>;
+                                [(set i32:$RT, (any_fp_to_uint f64:$RB))]>;
 
 def EFDDIV         : EFXForm_1<745, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "efddiv $RT, $RA, $RB", IIC_FPDivD,
                                [(set f64:$RT, (fdiv f64:$RA, f64:$RB))]>;
 
 def EFDMUL         : EFXForm_1<744, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
                                "efdmul $RT, $RA, $RB", IIC_FPDGeneral,
                                [(set f64:$RT, (fmul f64:$RA, f64:$RB))]>;
def EFSCTSF        : EFXForm_2a<727, (outs spe4rc:$RT), (ins spe4rc:$RB),
                                 "efsctsf $RT, $RB", IIC_FPSGeneral, []>;
 
 def EFSCTSI        : EFXForm_2a<725, (outs gprc:$RT), (ins spe4rc:$RB),
                                 "efsctsi $RT, $RB", IIC_FPSGeneral,
                                 []>;
 
 def EFSCTSIZ       : EFXForm_2a<730, (outs gprc:$RT), (ins spe4rc:$RB),
                                 "efsctsiz $RT, $RB", IIC_FPSGeneral,
-                                [(set i32:$RT, (fp_to_sint f32:$RB))]>;
+                                [(set i32:$RT, (any_fp_to_sint f32:$RB))]>;
 
 def EFSCTUF        : EFXForm_2a<726, (outs sperc:$RT), (ins spe4rc:$RB),
                                 "efsctuf $RT, $RB", IIC_FPSGeneral, []>;
 
 def EFSCTUI        : EFXForm_2a<724, (outs gprc:$RT), (ins spe4rc:$RB),
                                 "efsctui $RT, $RB", IIC_FPSGeneral,
                                 []>;
 
 def EFSCTUIZ       : EFXForm_2a<728, (outs gprc:$RT), (ins spe4rc:$RB),
                                 "efsctuiz $RT, $RB", IIC_FPSGeneral,
-                                [(set i32:$RT, (fp_to_uint f32:$RB))]>;
+                                [(set i32:$RT, (any_fp_to_uint f32:$RB))]>;
 
 def EFSDIV         : EFXForm_1<713, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
                                "efsdiv $RT, $RA, $RB", IIC_FPDivD,
                                [(set f32:$RT, (fdiv f32:$RA, f32:$RB))]>;
 
 def EFSMUL         : EFXForm_1<712, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
                                "efsmul $RT, $RA, $RB", IIC_FPGeneral,
                                [(set f32:$RT, (fmul f32:$RA, f32:$RB))]>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;
 
 def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;
 def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 
+def PPCstrict_mfvsr : SDNode<"PPCISD::STRICT_MFVSR", SDTUnaryOp, [SDNPHasChain]>;
+
 //-------------------------- Predicate definitions ---------------------------//
 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
 def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
 def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
 def HasOnlySwappingMemOps : Predicate<"!PPCSubTarget->hasP9Vector()">;
 def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
 def NoP9Vector : Predicate<"!PPCSubTarget->hasP9Vector()">;

 def : Pat<(f32 (bitconvert i32:$A)),
           (f32 (XSCVSPDPN
                  (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>;
 
 // bitconvert f64 -> i64
 // (move to GPR, nothing else needed)
 def : Pat<(i64 (bitconvert f64:$S)),
           (i64 (MFVSRD $S))>;
+def : Pat<(i64 (PPCstrict_mfvsr f64:$A)),
+          (i64 (MFVSRD f64:$A))>;
 
 // bitconvert i64 -> f64
 // (move to FPR, nothing else needed)
 def : Pat<(f64 (bitconvert i64:$S)),
           (f64 (MTVSRD $S))>;
 
 // Rounding to integer.
 def : Pat<(i64 (lrint f64:$S)),
           (i64 (MFVSRD (FCTID $S)))>;
 def : Pat<(i64 (lrint f32:$S)),
           (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
 def : Pat<(i64 (llrint f64:$S)),
           (i64 (MFVSRD (FCTID $S)))>;
 def : Pat<(i64 (llrint f32:$S)),
           (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
 def : Pat<(i64 (lround f64:$S)),
           (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
 def : Pat<(i64 (lround f32:$S)),
           (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
 def : Pat<(i64 (llround f64:$S)),
           (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
 def : Pat<(i64 (llround f32:$S)),
           (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
+def : Pat<(i32 (PPCstrict_mfvsr f64:$A)),
+          (i32 (MFVSRWZ f64:$A))>;
 
 // Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead
 // of f64
 def : Pat<(v8i16 (PPCmtvsrz i32:$A)),
           (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
 def : Pat<(v16i8 (PPCmtvsrz i32:$A)),
           (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
 

           (STXSIBX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
 
 // Instructions for store(fptoui).
 def : Pat<(PPCstore_scal_int_from_vsr
             (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xaddrX4:$dst, 8),
           (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
                   xaddrX4:$dst)>;
 def : Pat<(PPCstore_scal_int_from_vsr
             (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), iaddrX4:$dst, 8),
           (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
                  iaddrX4:$dst)>;
 def : Pat<(PPCstore_scal_int_from_vsr
             (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4),
           (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
 def : Pat<(PPCstore_scal_int_from_vsr
             (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 2),
           (STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \
+; RUN:   FileCheck %s -check-prefix=NOVSX
+
+declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
+declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
+declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
+declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
+
+declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
+declare i64 @llvm.experimental.constrained.fptosi.i64.f32(float, metadata)
+declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata)
+declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
+
+define i32 @d_to_i32(double %m) #0 {
+; CHECK-LABEL: d_to_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpsxws f0, f1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: d_to_i32:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiwz f0, f1
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    stfiwx f0, 0, r3
+; NOVSX-NEXT:    lwz r3, -4(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.ignore") #0
+  ret i32 %conv
+}
+
+define i64 @d_to_i64(double %m) #0 {
+; CHECK-LABEL: d_to_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpsxds f0, f1
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: d_to_i64:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctidz f0, f1
+; NOVSX-NEXT:    stfd f0, -8(r1)
+; NOVSX-NEXT:    ld r3, -8(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.ignore") #0
+  ret i64 %conv
+}
+
+define i64 @d_to_u64(double %m) #0 {
+; CHECK-LABEL: d_to_u64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpuxds f0, f1
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: d_to_u64:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiduz f0, f1
+; NOVSX-NEXT:    stfd f0, -8(r1)
+; NOVSX-NEXT:    ld r3, -8(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.ignore") #0
+  ret i64 %conv
+}
+
+define zeroext i32 @d_to_u32(double %m) #0 {
+; CHECK-LABEL: d_to_u32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpuxws f0, f1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: d_to_u32:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiwuz f0, f1
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    stfiwx f0, 0, r3
+; NOVSX-NEXT:    lwz r3, -4(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.ignore") #0
+  ret i32 %conv
+}
+
+define signext i32 @f_to_i32(float %m) #0 {
+; CHECK-LABEL: f_to_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpsxws f0, f1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: f_to_i32:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiwz f0, f1
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    stfiwx f0, 0, r3
+; NOVSX-NEXT:    lwa r3, -4(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.ignore") #0
+  ret i32 %conv
+}
+
+define i64 @f_to_i64(float %m) #0 {
+; CHECK-LABEL: f_to_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpsxds f0, f1
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: f_to_i64:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctidz f0, f1
+; NOVSX-NEXT:    stfd f0, -8(r1)
+; NOVSX-NEXT:    ld r3, -8(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.ignore") #0
+  ret i64 %conv
+}
+
+define i64 @f_to_u64(float %m) #0 {
+; CHECK-LABEL: f_to_u64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpuxds f0, f1
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: f_to_u64:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiduz f0, f1
+; NOVSX-NEXT:    stfd f0, -8(r1)
+; NOVSX-NEXT:    ld r3, -8(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.ignore") #0
+  ret i64 %conv
+}
+
+define zeroext i32 @f_to_u32(float %m) #0 {
+; CHECK-LABEL: f_to_u32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpuxws f0, f1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; NOVSX-LABEL: f_to_u32:
+; NOVSX:       # %bb.0: # %entry
+; NOVSX-NEXT:    fctiwuz f0, f1
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    stfiwx f0, 0, r3
+; NOVSX-NEXT:    lwz r3, -4(r1)
+; NOVSX-NEXT:    blr
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.ignore") #0
+  ret i32 %conv
+}
+
+attributes #0 = { strictfp }