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[PowerPC] Use fcti[dw] instructions in additional cases
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Authored by vddvss on Dec 10 2019, 10:31 AM.

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hfinkel
nemanjai
jsji
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Summary

rG0f0330a78709 added support for lowering lrint and llrint intrinsics to
fcti[dw] instructions on POWER8 and later processors. This patch extends
support for lowering these intrinsics on processors that support these
instruction.

This uses the existing fp-to-int infrastructure, and cleans up some of the logic
in the logic for that.

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vddvss created this revision.Dec 10 2019, 10:31 AM
Jim added a subscriber: Jim.Dec 15 2019, 10:17 PM

Please refer to https://reviews.llvm.org/D69949 that is about to be committed. I haven't looked at this patch but it seems related/overlapping. If there is an unforeseen issue with the other patch, please comment there.

The conflict I see is the other patch uses VSX for the operations, but this uses instructions that have been around as far back as the PPC970.

The conflict I see is the other patch uses VSX for the operations, but this uses instructions that have been around as far back as the PPC970.

Fair enough. I keep forgetting that recent server CPUs are not the only things that matter in the PPC world. I think we should handle lrint and llrint here and handle the rest of the nodes in the other patch. In fact, I think both patches can go in as they don't really conflict each other (save for some test case changes). So I imagine you'll just need to rebase this once I commit the other one.

I have pushed the other patch now. Please rebase this patch against ToT.

vddvss updated this revision to Diff 235917.Jan 2 2020, 12:15 PM
vddvss retitled this revision from [PowerPC] [RFC] exploit fcti[dw] instructions for lrint and llrint to [PowerPC] Use fcti[dw] instructions in additional cases.
vddvss edited the summary of this revision. (Show Details)

Updated differential. This moves the actions to near where D69949 had them, guards them with TM.Options.UnsafeFPMath (I can't believe I didn't do that in the first patch), and changes tests accordingly.

That said, the fc[tf]i* instructions go back to at least ISA 2.02, but the PPC.td file only lists POWER7 and later as having fpcvt instructions, so right now this patch would only add the instructions for POWER7, which has fpcvt but not direct move. I think determining what processors support the instructions would require a bit of archaeology, so I'm wondering if we should even bother with this?