[DAGCombiner] Require ninf for division estimation

[qiucf]

Summary

This is similar to D76853. Current implementation of division estimation isn't correct for 1.0/0.0 (result is nan, not expected inf).

And this change exposes a potential infinite loop: in combineRepeatedFPDivisors, we use isConstOrConstSplatFP to look up if the divisor is some constant. But it doesn't work after legalized on some platforms. This patch restricts the method to act before LegalDAG.

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13101

Do we need to check the target option here? If all tests are updated to use node-level fast-math-flags, then I would prefer not to include legacy/deprecated predicate.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13101

Probably should keep checking the attribute for consistency. Plus the attributes have the nice feature that you can apply them to bitcode functions when linking, but we don't have propagate FMF

[steven.zhang]

I think, this is the right fix. Notice that, even with this fix, we still have issue when the input is denormal floating point. We might have to add some test before doing the software expansion as what we did for sqrt. But this check may hurt the performance.

cat a.C

#include <stdio.h>
double __attribute__((noinline)) foo(double a, double b) {
	return a/b;
}

int main() {
	printf("%g\n", foo(1.0, 2.2250738585072009e-309));
	return 0;
}

clang a.C -Ofast;./a.out

nan

[qiucf]

@steven.zhang : We might have to add some test before doing the software expansion as what we did for sqrt. But this check may hurt the performance.

Yes.. On PowerPC, we have a 'test' instruction to determine whether two numbers are suitable for division estimation or not. (extremely big/small numbers, x is nan/inf, y is nan/inf/zero...) And I think we don't need this flag requirement after such exploitation. (maybe move the check inside BuildDivEstimate and add a hook?)

[spatel]

LGTM - if you want to move the flags check inside BuildDivEstimate() to work better with D80706, either way seems fine to me.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
 SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
   // TODO: Limit this transform based on optsize/minsize - it always creates at
   //       least 1 extra instruction. But the perf win may be substantial enough
   //       that only minsize should restrict this.
   bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath;
   const SDNodeFlags Flags = N->getFlags();
-  if (!UnsafeMath && !Flags.hasAllowReciprocal())
+  if (LegalDAG || (!UnsafeMath && !Flags.hasAllowReciprocal()))
     return SDValue();
 
   // Skip if current node is a reciprocal/fneg-reciprocal.
   SDValue N0 = N->getOperand(0);
   ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true);
   if (N0CFP && (N0CFP->isExactlyValue(1.0) || N0CFP->isExactlyValue(-1.0)))
     return SDValue();
 
SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
   return SDValue(N, 0);  // N was replaced.
 }
 
 SDValue DAGCombiner::visitFDIV(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
   SDNodeFlags Flags = N->getFlags();
 
   if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
     return R;
 
   // fold vector ops
if (N1.getOpcode() == ISD::FSQRT) {
           RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp, Flags);
           AddToWorklist(RV.getNode());
           return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags);
         }
       }
     }
 
     // Fold into a reciprocal estimate and multiply instead of a real divide.
+    if (Options.NoInfsFPMath || Flags.hasNoInfs())
       if (SDValue RV = BuildDivEstimate(N0, N1, Flags))
         return RV;
   }
 
   // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
   TargetLowering::NegatibleCost CostN0 =
       TargetLowering::NegatibleCost::Expensive;
   TargetLowering::NegatibleCost CostN1 =
       TargetLowering::NegatibleCost::Expensive;
   SDValue NegN0 =

llvm/test/CodeGen/AMDGPU/fdiv.ll

 ; GCN: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
 ; GCN: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
 ; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX10: s_denorm_mode 12
 ; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
 ; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
 define amdgpu_kernel void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) #0 {
 entry:
-  %fdiv = fdiv float %a, %b
+  %fdiv = fdiv ninf float %a, %b
   store float %fdiv, float addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}fdiv_f32_denormals:
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
 

 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
 
 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
 ; GCN-NOT: [[RESULT]]
 ; GCN: buffer_store_dword [[RESULT]]
 define amdgpu_kernel void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) #0 {
 entry:
-  %fdiv = fdiv arcp float %a, %b
+  %fdiv = fdiv arcp ninf float %a, %b
   store float %fdiv, float addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}fdiv_v2f32:
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS

 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[3].X,
 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].W,
 
 ; GCN: v_rcp_f32
 ; GCN: v_rcp_f32
 define amdgpu_kernel void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
 entry:
-  %fdiv = fdiv arcp <2 x float> %a, %b
+  %fdiv = fdiv arcp ninf <2 x float> %a, %b
   store <2 x float> %fdiv, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}fdiv_v4f32:
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

 ; GCN: v_rcp_f32
 ; GCN: v_rcp_f32
 ; GCN: v_rcp_f32
 ; GCN: v_rcp_f32
 define amdgpu_kernel void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
   %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
   %a = load <4 x float>, <4 x float> addrspace(1) * %in
   %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr
-  %result = fdiv arcp <4 x float> %a, %b
+  %result = fdiv arcp ninf <4 x float> %a, %b
   store <4 x float> %result, <4 x float> addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}fdiv_f32_correctly_rounded_divide_sqrt:
 
 ; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
 ; GCN-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; CHECK-NEXT:    xvnmsubadp 1, 0, 2
 ; CHECK-NEXT:    xvnmaddadp 2, 2, 1
 ; CHECK-NEXT:    xvmuldp 34, 34, 2
 ; CHECK-NEXT:    xvmuldp 35, 35, 2
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
-  %div = fdiv reassoc nsz arcp <4 x double> %a1, %splat.splat
+  %div = fdiv reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
   %sub = fsub reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/fdiv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
 
+define dso_local float @foo_nosw(float %0, float %1) local_unnamed_addr {
+; CHECK-LABEL: foo_nosw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xsdivsp 1, 1, 2
+; CHECK-NEXT:    blr
+  %3 = fdiv reassoc arcp nsz float %0, %1
+  ret float %3
+}
+
 define dso_local float @foo(float %0, float %1) local_unnamed_addr {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsresp 3, 2
 ; CHECK-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-NEXT:    xsnmsubasp 1, 2, 0
 ; CHECK-NEXT:    xsmaddasp 0, 3, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
-  %3 = fdiv reassoc arcp nsz float %0, %1
+  %3 = fdiv reassoc arcp nsz ninf float %0, %1
   ret float %3
 }

llvm/test/CodeGen/PowerPC/qpx-recipest.ll

 ; CHECK-NEXT:    qvlfdx 0, 0, 3
 ; CHECK-NEXT:    qvfmadd 0, 2, 3, 0
 ; CHECK-NEXT:    qvfnmsub 0, 3, 0, 3
 ; CHECK-NEXT:    qvfmul 3, 1, 0
 ; CHECK-NEXT:    qvfnmsub 1, 2, 3, 1
 ; CHECK-NEXT:    qvfmadd 1, 0, 1, 3
 ; CHECK-NEXT:    blr
 entry:
-  %r = fdiv arcp reassoc nsz <4 x double> %a, %b
+  %r = fdiv arcp reassoc nsz ninf <4 x double> %a, %b
   ret <4 x double> %r
 }
 
 define <4 x double> @foo2_safe(<4 x double> %a, <4 x double> %b) nounwind {
 ; CHECK-LABEL: foo2_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    qvesplati 3, 2, 3
 ; CHECK-NEXT:    qvesplati 4, 1, 3

 ; CHECK-LABEL: goo2_fmf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvfres 0, 2
 ; CHECK-NEXT:    qvfmuls 3, 1, 0
 ; CHECK-NEXT:    qvfnmsubs 1, 2, 3, 1
 ; CHECK-NEXT:    qvfmadds 1, 0, 1, 3
 ; CHECK-NEXT:    blr
 entry:
-  %r = fdiv arcp reassoc <4 x float> %a, %b
+  %r = fdiv arcp reassoc ninf <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @goo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-LABEL: goo2_safe:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    qvesplati 3, 2, 3
 ; CHECK-NEXT:    qvesplati 4, 1, 3

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P9-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P9-NEXT:    blr
   %x = call reassoc arcp nsz float @llvm.sqrt.f32(float %a)
   %y = fmul reassoc nsz float %x, %b
-  %z = fdiv reassoc arcp nsz float %c, %y
+  %z = fdiv reassoc arcp nsz ninf float %c, %y
   ret float %z
 }
 
 define float @rsqrt_fmul_safe(float %a, float %b, float %c) {
 ; CHECK-P7-LABEL: rsqrt_fmul_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrts 0, 1
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2

 ; CHECK-P9-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz double %a, %b
+  %r = fdiv reassoc arcp nsz ninf double %a, %b
   ret double %r
 }
 
 define double @foo2_safe(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fdiv 1, 1, 2
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-LABEL: goo2_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsresp 3, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubasp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz float %a, %b
+  %r = fdiv reassoc arcp nsz ninf float %a, %b
   ret float %r
 }
 
 define float @goo2_safe(float %a, float %b) nounwind {
 ; CHECK-P7-LABEL: goo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fdivs 1, 1, 2
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-LABEL: hoo2_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvresp 1, 35
 ; CHECK-P9-NEXT:    xvmulsp 0, 34, 1
 ; CHECK-P9-NEXT:    xvnmsubasp 34, 35, 0
 ; CHECK-P9-NEXT:    xvmaddasp 0, 1, 34
 ; CHECK-P9-NEXT:    xxlor 34, 0, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz <4 x float> %a, %b
+  %r = fdiv reassoc arcp nsz ninf <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
 ; CHECK-P7-NEXT:    addi 4, 1, -48

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
 
-define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
-; CHECK-LABEL: repeated_fp_divisor:
+; Check if this causes infinite loop when estimation disabled
+define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
+; CHECK-LABEL: repeated_fp_divisor_noest:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
+; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; CHECK-NEXT:    lvx 3, 0, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
+; CHECK-NEXT:    xxspltw 0, 0, 0
+; CHECK-NEXT:    xvdivsp 0, 35, 0
 ; CHECK-NEXT:    lvx 3, 0, 3
-; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
+; CHECK-NEXT:    xvmulsp 1, 34, 35
+; CHECK-NEXT:    xvmulsp 34, 1, 0
+; CHECK-NEXT:    blr
+  %ins = insertelement <4 x float> undef, float %a, i32 0
+  %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
+  %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
+  %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
+  ret <4 x float> %mul
+}
+
+define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
+; CHECK-LABEL: repeated_fp_divisor:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xscvdpspn 0, 1
+; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
+; CHECK-NEXT:    lvx 3, 0, 3
+; CHECK-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI1_1@toc@l
 ; CHECK-NEXT:    lvx 4, 0, 3
 ; CHECK-NEXT:    xxspltw 0, 0, 0
 ; CHECK-NEXT:    xvresp 1, 0
 ; CHECK-NEXT:    xvnmsubasp 35, 0, 1
 ; CHECK-NEXT:    xvmulsp 0, 34, 36
 ; CHECK-NEXT:    xvmaddasp 1, 1, 35
 ; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
   %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
-  %mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
+  %mul = fdiv reassoc arcp nsz ninf <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 

llvm/test/CodeGen/PowerPC/vsx-recip-est.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
 @a = global float 3.000000e+00, align 4
 @b = global float 4.000000e+00, align 4
 @c = global double 3.000000e+00, align 8
 @d = global double 4.000000e+00, align 8
 
 ; Function Attrs: nounwind
 define float @emit_xsresp() {
 entry:
   %0 = load float, float* @a, align 4
   %1 = load float, float* @b, align 4
-  %div = fdiv arcp float %0, %1
+  %div = fdiv arcp ninf float %0, %1
   ret float %div
 ; CHECK-LABEL: @emit_xsresp
 ; CHECK: xsresp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define float @emit_xsrsqrtesp(float %f) {
 entry:

 ; Function Attrs: nounwind readnone
 declare float @llvm.sqrt.f32(float)
 
 ; Function Attrs: nounwind
 define double @emit_xsredp() {
 entry:
   %0 = load double, double* @c, align 8
   %1 = load double, double* @d, align 8
-  %div = fdiv arcp double %0, %1
+  %div = fdiv arcp ninf double %0, %1
   ret double %div
 ; CHECK-LABEL: @emit_xsredp
 ; CHECK: xsredp {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define double @emit_xsrsqrtedp(double %f) {
 entry:

llvm/test/CodeGen/X86/fdiv-combine-vec.ll

 ; AVX-NEXT:    vsubss %xmm1, %xmm3, %xmm1
 ; AVX-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX-NEXT:    vaddss %xmm1, %xmm2, %xmm1
 ; AVX-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
 ; AVX-NEXT:    vmulps %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %vy = insertelement <4 x float> undef, float %y, i32 0
   %splaty = shufflevector <4 x float> %vy, <4 x float> undef, <4 x i32> zeroinitializer
-  %r = fdiv arcp reassoc <4 x float> %x, %splaty
+  %r = fdiv arcp reassoc ninf <4 x float> %x, %splaty
   ret <4 x float> %r
 }
 
 define <8 x float> @splat_fdiv_v8f32_estimate(<8 x float> %x, float %y) #0 {
 ; SSE-LABEL: splat_fdiv_v8f32_estimate:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    rcpss %xmm2, %xmm3
 ; SSE-NEXT:    mulss %xmm3, %xmm2