[XCOFF][AIX] Emit correct alignment for csect

[jasonliu]

Summary

This patch tries to emit the correct alignment result for both object file generation path and assembly path.

[DiggerLin]

llvm/lib/MC/MCContext.cpp

624 ↗

(On Diff #261024)

how about to define static const expr DefaultAlign=4 ; in the MCSectionXCOFF class ?

llvm/lib/MC/MCXCOFFStreamer.cpp

66

do we need to add safeguard of cast<MCSymbolXCOFF>(Symbol)->hasRepresentedCsect() here ?

[jasonliu]

llvm/lib/MC/MCXCOFFStreamer.cpp

66

No, common symbol must be a csect, so it should have represented csect.

[daltenty]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1723

I'm not clear why we need this check here? Trying to SelectionSectionForGlobal will already give us an error if either Function/Data sections are on. Is there a unique reason that this approach won't work with data-sections? If so, a comment is probably in order.

[jasonliu]

Address comments.

llvm/lib/MC/MCContext.cpp

624 ↗

(On Diff #261024)

Thanks. Just realized I can do this in MCSectionXCOFF constructor as well.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1723

Thanks. Added reasoning in the comment.

[DiggerLin]

LGTM

[daltenty]

LGTM

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

8

Should the style be consistent between .csect and .comm over the use of spaces after the comma?

[hubert.reinterpretcast]

llvm/lib/MC/MCXCOFFStreamer.cpp

63

Suggest newline before the comment.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1724

Even if data sections are used, explicitly-specified sections could be used to group variables together.

1742

s/know csect's alignment upfront/know, up front, the alignment of csects/;
Add "the" before "assembly path".

1743

Add "a" before ".csect directive".

1748

Use the immediate base class even if it does not currently override this function.

llvm/test/CodeGen/PowerPC/test_func_desc.ll

6

It seems we have nothing to verify alignment of functions:

__attribute__((__aligned__(32))) int bar() { return 0; }

[jasonliu]

Add in support for function alignment.
Move the logic from doFinialization to doInitialization because ".text" csect is emitted very early.

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

8

I agree the style should be consistent for the use of spaces after comma.
It seems like for clang, we would have a space after comma (at least for instructions). So looks like .csect directive is following that convention.
We could have a NFC patch later to clean it up for .comm.

[hubert.reinterpretcast]

LGTM with minor nits. Thanks.

llvm/include/llvm/MC/MCSectionXCOFF.h

51

s/Csect/A csect/;
Add "csects" after "undefined symbol".

llvm/lib/MC/MCXCOFFStreamer.cpp

64

s/value/values/;

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1723

LLVM naming convention: Result.

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

8

Okay; thanks.

llvm/test/CodeGen/aix-func-align.ll

2

s/the csect contains/a csect containing/;

11

Indent the FileCheck invocation. From D78929, it looks like two spaces.

[jasonliu]

Fixed a build break introduced by this change in https://github.com/llvm/llvm-project/commit/a1b04aaea210a9a9fbe0cd9dd7f874e12fa97585
I should've put aix-func-align.ll in the PowerPC sub-directive.

llvm/include/llvm/MC/MCSectionXCOFF.h

 //    implemented yet.
 class MCSectionXCOFF final : public MCSection {
   friend class MCContext;
 
   XCOFF::StorageMappingClass MappingClass;
   XCOFF::SymbolType Type;
   XCOFF::StorageClass StorageClass;
   MCSymbolXCOFF *const QualName;
+  static constexpr unsigned DefaultAlignVal = 4;
 
   MCSectionXCOFF(StringRef Name, XCOFF::StorageMappingClass SMC,
                  XCOFF::SymbolType ST, XCOFF::StorageClass SC, SectionKind K,
                  MCSymbolXCOFF *QualName, MCSymbol *Begin)
       : MCSection(SV_XCOFF, Name, K, Begin), MappingClass(SMC), Type(ST),
         StorageClass(SC), QualName(QualName) {
     assert((ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) &&
            "Invalid or unhandled type for csect.");
     assert(QualName != nullptr && "QualName is needed.");
     QualName->setStorageClass(SC);
     QualName->setRepresentedCsect(this);
+    // A csect is 4 byte aligned by default, except for undefined symbol csects.
+    if (Type != XCOFF::XTY_ER)
+      setAlignment(Align(DefaultAlignVal));
   }
 
+  void printCsectDirective(raw_ostream &OS) const;
+
 public:
   ~MCSectionXCOFF();
 
   static bool classof(const MCSection *S) {
     return S->getVariant() == SV_XCOFF;
   }
 
   XCOFF::StorageMappingClass getMappingClass() const { return MappingClass; }

llvm/lib/MC/MCSectionXCOFF.cpp

 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 MCSectionXCOFF::~MCSectionXCOFF() = default;
 
+void MCSectionXCOFF::printCsectDirective(raw_ostream &OS) const {
+  OS << "\t.csect " << QualName->getName() << ", " << Log2_32(getAlignment())
+     << '\n';
+}
 
 void MCSectionXCOFF::PrintSwitchToSection(const MCAsmInfo &MAI, const Triple &T,
                                           raw_ostream &OS,
                                           const MCExpr *Subsection) const {
   if (getKind().isText()) {
     if (getMappingClass() != XCOFF::XMC_PR)
       report_fatal_error("Unhandled storage-mapping class for .text csect");
 
-    OS << "\t.csect " << QualName->getName() << '\n';
+    printCsectDirective(OS);
     return;
   }
 
   if (getKind().isReadOnly()) {
     if (getMappingClass() != XCOFF::XMC_RO)
       report_fatal_error("Unhandled storage-mapping class for .rodata csect.");
-    OS << "\t.csect " << QualName->getName() << '\n';
+    printCsectDirective(OS);
     return;
   }
 
   if (getKind().isData()) {
     switch (getMappingClass()) {
     case XCOFF::XMC_RW:
     case XCOFF::XMC_DS:
-      OS << "\t.csect " << QualName->getName() << '\n';
+      printCsectDirective(OS);
       break;
     case XCOFF::XMC_TC:
       break;
     case XCOFF::XMC_TC0:
       OS << "\t.toc\n";
       break;
     default:
       report_fatal_error(

llvm/lib/MC/MCXCOFFStreamer.cpp

 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCXCOFFStreamer.h"
 #include "llvm/BinaryFormat/XCOFF.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSectionXCOFF.h"
 #include "llvm/MC/MCSymbolXCOFF.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 MCXCOFFStreamer::MCXCOFFStreamer(MCContext &Context,
                                  std::unique_ptr<MCAsmBackend> MAB,
                                  std::unique_ptr<MCObjectWriter> OW,

 }
 
 void MCXCOFFStreamer::emitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
                                        unsigned ByteAlignment) {
   getAssembler().registerSymbol(*Symbol);
   Symbol->setExternal(cast<MCSymbolXCOFF>(Symbol)->getStorageClass() !=
                       XCOFF::C_HIDEXT);
   Symbol->setCommon(Size, ByteAlignment);
 
+  // Default csect align is 4, but common symbols have explicit alignment values
+  // and we should honor it.
+  cast<MCSymbolXCOFF>(Symbol)->getRepresentedCsect()->setAlignment(
+      Align(ByteAlignment));
+
   // Emit the alignment and storage for the variable to the section.
   emitValueToAlignment(ByteAlignment);
   emitZeros(Size);
 }
 
 void MCXCOFFStreamer::emitZerofill(MCSection *Section, MCSymbol *Symbol,
                                    uint64_t Size, unsigned ByteAlignment,
                                    SMLoc Loc) {

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

PPCAIXAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : PPCAsmPrinter(TM, std::move(Streamer)) {
     if (MAI->isLittleEndian())
       report_fatal_error(
           "cannot create AIX PPC Assembly Printer for a little-endian target");
   }
 
   StringRef getPassName() const override { return "AIX PPC Assembly Printer"; }
 
-  bool doInitialization(Module &M) override {
-    if (M.alias_size() > 0u)
-      report_fatal_error(
-          "module has aliases, which LLVM does not yet support for AIX");
-
-    return PPCAsmPrinter::doInitialization(M);
-  }
+  bool doInitialization(Module &M) override;
 
   void SetupMachineFunction(MachineFunction &MF) override;
 
   void emitGlobalVariable(const GlobalVariable *GV) override;
 
   void emitFunctionDescriptor() override;
 
   void emitEndOfAsmFile(Module &) override;
for (auto &I : TOC) {
     OutStreamer->SwitchSection(TCEntry);
 
     OutStreamer->emitLabel(I.second);
     if (TS != nullptr)
       TS->emitTCEntry(*I.first);
   }
 }
 
+bool PPCAIXAsmPrinter::doInitialization(Module &M) {
+  if (M.alias_size() > 0u)
+    report_fatal_error(
+        "module has aliases, which LLVM does not yet support for AIX");
+
+  const bool Result = PPCAsmPrinter::doInitialization(M);
+
+  auto setCsectAlignment = [this](const GlobalObject *GO) {
+    // Declarations have 0 alignment which is set by default.
+    if (GO->isDeclaration())
+      return;
+
+    SectionKind GOKind = getObjFileLowering().getKindForGlobal(GO, TM);
+    MCSectionXCOFF *Csect = cast<MCSectionXCOFF>(
+        getObjFileLowering().SectionForGlobal(GO, GOKind, TM));
+
+    Align GOAlign = getGVAlignment(GO, GO->getParent()->getDataLayout());
+    if (GOAlign > Csect->getAlignment())
+      Csect->setAlignment(GOAlign);
+  };
+
+  // We need to know, up front, the alignment of csects for the assembly path,
+  // because once a .csect directive gets emitted, we could not change the
+  // alignment value on it.
+  for (const auto &G : M.globals())
+    setCsectAlignment(&G);
+
+  for (const auto &F : M)
+    setCsectAlignment(&F);
+
+  return Result;
+}
+
 /// createPPCAsmPrinterPass - Returns a pass that prints the PPC assembly code
 /// for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
 static AsmPrinter *
 createPPCAsmPrinterPass(TargetMachine &tm,
                         std::unique_ptr<MCStreamer> &&Streamer) {
   if (tm.getTargetTriple().isOSAIX())

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load 8 from got)
 ; 64SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $x[[REG1]] :: (load 4 from constant-pool)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
-; 32SMALL-ASM:         .csect .rodata[RO]
+; 32SMALL-ASM:         .csect .rodata[RO], 2
 ; 32SMALL-ASM:         .align  2
 ; 32SMALL-ASM: .LCPI0_0:
 ; 32SMALL-ASM:         .long  0x40b00000
 ; 32SMALL-ASM: .test_float:
 ; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
-; 32LARGE-ASM:         .csect .rodata[RO]
+; 32LARGE-ASM:         .csect .rodata[RO], 2
 ; 32LARGE-ASM:         .align  2
 ; 32LARGE-ASM: .LCPI0_0:
 ; 32LARGE-ASM:         .long   0x40b00000
 ; 32LARGE-ASM: .test_float:
 ; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
-; 64SMALL-ASM:         .csect .rodata[RO]
+; 64SMALL-ASM:         .csect .rodata[RO], 2
 ; 64SMALL-ASM:         .align  2
 ; 64SMALL-ASM: .LCPI0_0:
 ; 64SMALL-ASM:         .long   0x40b00000
 ; 64SMALL-ASM: .test_float:
 ; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
-; 64LARGE-ASM:         .csect .rodata[RO]
+; 64LARGE-ASM:         .csect .rodata[RO], 2
 ; 64LARGE-ASM:         .align  2
 ; 64LARGE-ASM: .LCPI0_0:
 ; 64LARGE-ASM:         .long   0x40b00000
 ; 64LARGE-ASM: .test_float:
 ; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
 ; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; 32SMALL-ASM:      bctr
 ; 32SMALL-ASM: LBB0_2:
 ; 32SMALL-ASM: LBB0_3:
 ; 32SMALL-ASM: LBB0_4:
 ; 32SMALL-ASM: LBB0_5:
 ; 32SMALL-ASM: LBB0_6:
 ; 32SMALL-ASM:      li 3, 0
 ; 32SMALL-ASM:      blr
-; 32SMALL-ASM:      .csect .rodata[RO]
+; 32SMALL-ASM:      .csect .rodata[RO], 2
 ; 32SMALL-ASM:      .align  2
 ; 32SMALL-ASM: .LJTI0_0:
 ; 32SMALL-ASM:      .long   LBB0_2-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_3-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_4-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table

 ; 32LARGE-ASM:      bctr
 ; 32LARGE-ASM: LBB0_2:
 ; 32LARGE-ASM: LBB0_3:
 ; 32LARGE-ASM: LBB0_4:
 ; 32LARGE-ASM: LBB0_5:
 ; 32LARGE-ASM: LBB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
-; 32LARGE-ASM:      .csect .rodata[RO]
+; 32LARGE-ASM:      .csect .rodata[RO], 2
 ; 32LARGE-ASM:      .align  2
 ; 32LARGE-ASM: .LJTI0_0:
 ; 32LARGE-ASM:      .long   LBB0_2-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_3-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_4-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table

 ; 64SMALL-ASM:      bctr
 ; 64SMALL-ASM: LBB0_2:
 ; 64SMALL-ASM: LBB0_3:
 ; 64SMALL-ASM: LBB0_4:
 ; 64SMALL-ASM: LBB0_5:
 ; 64SMALL-ASM: LBB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
-; 64SMALL-ASM:      .csect .rodata[RO]
+; 64SMALL-ASM:      .csect .rodata[RO], 2
 ; 64SMALL-ASM:      .align  2
 ; 64SMALL-ASM: .LJTI0_0:
 ; 64SMALL-ASM:      .long   LBB0_2-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_3-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_4-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table

 ; 64LARGE-ASM:      bctr
 ; 64LARGE-ASM: LBB0_2:
 ; 64LARGE-ASM: LBB0_3:
 ; 64LARGE-ASM: LBB0_4:
 ; 64LARGE-ASM: LBB0_5:
 ; 64LARGE-ASM: LBB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
-; 64LARGE-ASM:      .csect .rodata[RO]
+; 64LARGE-ASM:      .csect .rodata[RO], 2
 ; 64LARGE-ASM:      .align  2
 ; 64LARGE-ASM: .LJTI0_0:
 ; 64LARGE-ASM:      .long   LBB0_2-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_3-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_4-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; CHECK: .toc
 ; CHECK: .tc .LJTI0_0[TC],.LJTI0_0

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck --check-prefix=CHECK64 %s
 
 @a = common global i32 0
 @b = constant i32* @a
 
 ;CHECK:         .comm   a[RW],4,2
-;CHECK-NEXT:    .csect .data[RW]
+;CHECK-NEXT:    .csect .data[RW], 2
 ;CHECK-NEXT:    .globl  b
 ;CHECK-NEXT:    .align  2
 ;CHECK-NEXT: b:
 ;CHECK-NEXT:    .long   a
 
 ;CHECK64:       .comm   a[RW],4,2
-;CHECK64-NEXT:  .csect .data[RW]
+;CHECK64-NEXT:  .csect .data[RW], 3
 ;CHECK64-NEXT:  .globl  b
 ;CHECK64-NEXT:  .align  3
 ;CHECK64-NEXT: b:
 ;CHECK64-NEXT:  .llong  a

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo
 declare void @foo(...)
 
 @bar_ptr1 = global void (...)* bitcast (void ()* @bar to void (...)*)
 define void @bar() {
 entry:
   ret void
 }
 
 
-;CHECK:          .csect .data[RW]
+;CHECK:          .csect .data[RW], 2
 ;CHECK-NEXT:     .globl  foo_ptr
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     foo_ptr:
 ;CHECK-NEXT:     .long   foo[DS]
 ;CHECK-NEXT:     .globl  bar_ptr1
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     bar_ptr1:
 ;CHECK-NEXT:     .long   bar[DS]
 ;CHECK-NEXT:     .extern foo[DS]
 
-;CHECK64:         .csect .data[RW]
+;CHECK64:         .csect .data[RW], 3
 ;CHECK64-NEXT:         .globl  foo_ptr
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    foo_ptr:
 ;CHECK64-NEXT:         .llong  foo[DS]
 ;CHECK64-NEXT:         .globl  bar_ptr1
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    bar_ptr1:
 ;CHECK64-NEXT:         .llong  bar[DS]
 ;CHECK64-NEXT:         .extern foo[DS]

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

 @f = common local_unnamed_addr global float 0.000000e+00, align 4
 
 @over_aligned_comm = common local_unnamed_addr global double 0.000000e+00, align 32
 
 @array = common local_unnamed_addr global [33 x i8] zeroinitializer, align 1
 
 ; CHECK-NOT: .toc
 
-; CHECK:      .csect .text[PR]
+; CHECK:      .csect .text[PR], 2
 ; CHECK-NEXT:  .file
 
-; CHECK:      .csect .data[RW]
+; CHECK:      .csect .data[RW], 5
 ; CHECK-NEXT: .globl  ivar
 ; CHECK-NEXT: .align  2
 ; CHECK-NEXT: ivar:
 ; CHECK-NEXT: .long   35
 
 ; CHECK:      .globl  llvar
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: llvar:

 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
 ; SYMS-NEXT:       Index: [[#INDX+1]]
 ; SYMS-NEXT:       SectionLen: 0
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
-; SYMS-NEXT:       SymbolAlignmentLog2: 0
+; SYMS-NEXT:       SymbolAlignmentLog2: 2
 ; SYMS-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYMS-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {

llvm/test/CodeGen/PowerPC/aix-xcoff-lower-comm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,ASM32 %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,ASM64 %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj -r --expand-relocs -t %t.o | FileCheck --check-prefixes=RELOC,SYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @common = common global i32 0, align 4
 @pointer = global i32* @common, align 4
 
 
 ; CHECK:             .comm   common[RW],4,2
-; CHECK-NEXT:        .csect .data[RW]
+; ASM32-NEXT:        .csect .data[RW], 2
+; ASM64-NEXT:        .csect .data[RW], 3
 ; CHECK-NEXT:        .globl  pointer
 ; ASM32-NEXT:        .align  2
 ; ASM64-NEXT:        .align  3
 ; CHECK-NEXT:pointer:
 ; ASM32-NEXT:        .long   common[RW]
 ; ASM64-NEXT:        .llong   common[RW]
 
 

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 @__const.main.cnst4 = private unnamed_addr constant %struct.Merge_cnst4 { i16 16392, i8 0 }
 
 ; Function Attrs: noinline nounwind optnone
 define i32 @main() #0 {
 entry:
   ret i32 0
 }
 
-;CHECK:         .csect .rodata[RO]
+;CHECK:         .csect .rodata[RO], 4
 ;CHECK-NEXT:         .align  4
 ;CHECK-NEXT: .L__const.main.cnst32:
 ;CHECK-NEXT:         .llong  4611686018427387954
 ;CHECK-NEXT:         .long   0                       # 0x0
 ;CHECK-NEXT:         .space  4
 ;CHECK-NEXT:         .llong  0
 ;CHECK-NEXT:         .long   0                       # 0x0
 ;CHECK-NEXT:         .space  4

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 ; Function Attrs: noinline nounwind optnone
 define i8 @foo() #0 {
 entry:
   %0 = load i8*, i8** @p, align 4
   %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
-; CHECK:   .csect .rodata.str2.2[RO]
+; CHECK:   .csect .rodata.str2.2[RO], 2
 ; CHECK-NEXT:   .align  1
 ; CHECK-NEXT: .Lmagic16:
 ; CHECK-NEXT:   .short  264                     # 0x108
 ; CHECK-NEXT:   .short  272                     # 0x110
 ; CHECK-NEXT:   .short  213                     # 0xd5
 ; CHECK-NEXT:   .short  0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str4.4[RO]
+; CHECK-NEXT:   .csect .rodata.str4.4[RO], 2
 ; CHECK-NEXT:   .align  2
 ; CHECK-NEXT: .Lmagic32:
 ; CHECK-NEXT:   .long   464                     # 0x1d0
 ; CHECK-NEXT:   .long   472                     # 0x1d8
 ; CHECK-NEXT:   .long   413                     # 0x19d
 ; CHECK-NEXT:   .long   0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str1.1[RO]
+; CHECK-NEXT:   .csect .rodata.str1.1[RO], 2
 ; CHECK-NEXT: .LstrA:
 ; CHECK-NEXT: .byte   104
 ; CHECK-NEXT: .byte   101
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   111
 ; CHECK-NEXT: .byte   32
 ; CHECK-NEXT: .byte   119

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

 @const_llvar = constant i64 36, align 8
 @const_svar = constant i16 37, align 2
 @const_fvar = constant float 8.000000e+02, align 4
 @const_dvar = constant double 9.000000e+02, align 8
 @const_over_aligned = constant double 9.000000e+02, align 32
 @const_chrarray = constant [4 x i8] c"abcd", align 1
 @const_dblarr = constant [4 x double] [double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00], align 8
 
-; CHECK:               .csect .rodata[RO]
+; CHECK:               .csect .rodata[RO], 5
 ; CHECK-NEXT:          .globl  const_ivar
 ; CHECK-NEXT:          .align  2
 ; CHECK-NEXT:  const_ivar:
 ; CHECK-NEXT:          .long   35
 ; CHECK-NEXT:          .globl  const_llvar
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_llvar:
 ; CHECK-NEXT:          .llong  36

llvm/test/CodeGen/PowerPC/test_func_desc.ll

 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
 
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
 
 
 define i32 @foo() {
 entry:
   ret i32 3
 }
 
 define i32 @main() {
 entry:

 
 define internal i32 @static_foo() {
 entry:
   ret i32 3
 }
 
 ; CHECK: .globl foo[DS]
 ; CHECK: .globl .foo
-; CHECK: .csect foo[DS]
-; 32BIT: .long .foo
+; 32BIT: .csect foo[DS], 2
+; 32BIT-NEXT: .long .foo
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .llong .foo
+; 64BIT: .csect foo[DS], 3
+; 64BIT-NEXT: .llong .foo
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR]
+; CHECK-NEXT: .csect .text[PR], 2
 ; CHECK-LABEL: .foo:
 
 ; CHECK: .globl main[DS]
 ; CHECK: .globl .main
-; CHECK: .csect main[DS]
-; 32BIT: .long .main
+; 32BIT: .csect main[DS], 2
+; 32BIT-NEXT: .long .main
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .llong .main
+; 64BIT: .csect main[DS], 3
+; 64BIT-NEXT: .llong .main
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR]
+; CHECK-NEXT: .csect .text[PR], 2
 ; CHECK-LABEL: .main:
 ; CHECK: bl .foo
 ; CHECK: bl .extern_foo
 ; CHECK: bl .static_foo
 
 ; CHECK: .lglobl .static_foo
-; CHECK: .csect static_foo[DS]
-; 32BIT: .long .static_foo
+; 32BIT: .csect static_foo[DS], 2
+; 32BIT-NEXT: .long .static_foo
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .llong .static_foo
+; 64BIT: .csect static_foo[DS], 3
+; 64BIT-NEXT: .llong .static_foo
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR]
+; CHECK-NEXT: .csect .text[PR], 2
 ; CHECK-LABEL: .static_foo:
 
 ; CHECK-NOT: .csect extern_foo
 
 ; CHECK: .toc
 ; CHECK-NOT: .tc

llvm/test/CodeGen/aix-func-align.ll

+; This test tries to verify if a csect containing code would have the correct alignment.
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
+
+; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
+; RUN:   FileCheck --check-prefix=XCOFF64 %s
+; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
+
+define i32 @foo()  align 32 {
+entry:
+  ret i32 0
+}
+
+define i32 @bar()  align 64 {
+entry:
+  ret i32 0
+}
+
+; CHECK:      .csect .text[PR], 6
+; CHECK-NEXT: .foo:
+
+; CHECK:      .csect .text[PR], 6
+; CHECK-NEXT: .bar:
+
+; SYMS:       Symbol {{[{][[:space:]] *}}Index: [[#INDX:]]{{[[:space:]] *}}Name: .text
+; SYMS-NEXT:    Value (RelocatableAddress): 0x0
+; SYMS-NEXT:    Section: .text
+; SYMS-NEXT:    Type: 0x0
+; SYMS-NEXT:    StorageClass: C_HIDEXT (0x6B)
+; SYMS-NEXT:    NumberOfAuxEntries: 1
+; SYMS-NEXT:    CSECT Auxiliary Entry {
+; SYMS-NEXT:      Index: [[#INDX+1]]
+; SYMS-NEXT:      SectionLen: 72
+; SYMS-NEXT:      ParameterHashIndex: 0x0
+; SYMS-NEXT:      TypeChkSectNum: 0x0
+; SYMS-NEXT:      SymbolAlignmentLog2: 6
+; SYMS-NEXT:      SymbolType: XTY_SD (0x1)
+; SYMS-NEXT:      StorageMappingClass: XMC_PR (0x0)
+; SYMS-NEXT:      StabInfoIndex: 0x0
+; SYMS-NEXT:      StabSectNum: 0x0
+; SYMS-NEXT:    }
+; SYMS-NEXT:  }